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review.coreboot.org / coreboot / 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 / src / soc / intel / cannonlake / fsp_params.c
  1. 9395cf9 soc/intel: Create common function to check PCH slot by Kapil Porwal · 1 year, 8 months ago
  2. afeaa4d soc/intel: Remove unused <cbmem.h> by Elyes HAOUAS · 2 years, 7 months ago
  3. 92b7815 soc/intel/cannonlake: Forbid FSP from disabling HECI1 by Subrata Banik · 2 years, 7 months ago
  4. 805956b soc/intel/cnl: Use Kconfig to disable HECI1 by Subrata Banik · 2 years, 7 months ago
  5. 5f2d114 soc/intel/cannonlake: Rename SA_DEV_SLOT_DSP by Felix Singer · 2 years, 8 months ago
  6. b2a442e soc/intel/cannonlake: Fix PEG1 _PRT generation by Arthur Heymans · 2 years, 10 months ago
  7. 0e90580 soc/intel: transition full control over PM Timer from FSP to coreboot by Michael Niewöhner · 2 years, 11 months ago
  8. 9f0266c soc/intel/cannonlake: Lock PAM registers in finalize by Tim Wawrzynczak · 3 years ago
  9. 5d805f6 soc/intel/cannonlake: Fix PCH-H IRQ constraints by Angel Pons · 3 years ago
  10. 85ebab8 soc/intel/cannonlake: Clean up FSP chipset lockdown configuration by Felix Singer · 3 years, 4 months ago
  11. e4bc55b soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is given by Nico Huber · 3 years, 1 month ago
  12. bc35bed soc/intel/*: Allow configuring 8254 timer via CMOS by Sean Rhodes · 3 years, 1 month ago
  13. c7cfe0b soc/intel: Refactor `xdci_can_enable()` function by Angel Pons · 3 years, 2 months ago
  14. f9bb1b4 soc/intel/cannonlake: Use new IRQ module by Tim Wawrzynczak · 3 years, 2 months ago
  15. 3b374be soc/intel/cannonlake: Use devfn_disable() function for XDCI by Subrata Banik · 3 years, 2 months ago
  16. 6f910e2 soc/intel/cannonlake: Make use of is_devfn_enabled() function by Subrata Banik · 3 years, 2 months ago
  17. b9b6f4d soc/intel: Drop unused lpss functions by Furquan Shaikh · 3 years, 2 months ago
  18. 2a3689f soc/intel/cannonlake: Deduplicate function declaration by Felix Singer · 3 years, 4 months ago
  19. 0a6cf23 soc/intel/cannonlake: Remove unnecessary function by Felix Singer · 3 years, 4 months ago
  20. 4949a3d drivers/intel/fsp1_1,fsp2_0: Refactor logo display by Kyösti Mälkki · 3 years, 7 months ago
  21. 98d580b soc/intel/cannonlake: Allow RP#1 usage for ClkSrc by Jeremy Soller · 3 years, 8 months ago
  22. b1fa231 soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S by Jeremy Soller · 3 years, 8 months ago
  23. 2031221 soc/intel/cannonlake: Change mainboard_silicon_init_params argument by Patrick Rudolph · 3 years, 8 months ago
  24. a1843d8 soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig by Michael Niewöhner · 3 years, 11 months ago
  25. 33f234e3 soc/intel/cannonlake: Fix memory corruptions by John Zhao · 3 years, 10 months ago
  26. bbb8123 soc/intel: Configure PAVP at compile-time by Benjamin Doron · 4 years, 2 months ago
  27. 2854f40 src/soc/intel: Drop unneeded empty lines by Elyes HAOUAS · 4 years ago
  28. 27413d3 soc/intel/cnl: Use the common code to set the PchPmPwrCycDur by V Sowmya · 4 years ago
  29. 056d552 soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default by Michael Niewöhner · 4 years ago
  30. d9e4594 soc/intel/cnl: Enable HECI3 depending on devicetree by Felix Singer · 4 years ago
  31. 119ace0 soc/intel/cnl: Configure FSP option PcieRpSlotImplemented by Nico Huber · 4 years, 11 months ago
  32. 3de90d1 soc/intel/cnl: Set Heci1Disable depending on devicetree config by Felix Singer · 4 years ago
  33. 172bcc8 soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabled by Felix Singer · 4 years, 1 month ago
  34. c25c1eb src: Update bare access to BOOL CONFIG_ vals to CONFIG() by Martin Roth · 4 years, 1 month ago
  35. 3658c62 soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settings by Jamie Chen · 4 years, 5 months ago
  36. d7238eb soc/intel/cannonlake: make satahotplug user configurable via devicetree by Jonas Loeffelholz · 4 years, 2 months ago
  37. e40b948 soc/intel/cannonlake: Add PchPmPwrCycDur to chip options by Sridhar Siricilla · 4 years, 2 months ago
  38. 061cd78 soc/intel/cannonlake: Add RP configuration settings by Christian Walter · 4 years, 3 months ago
  39. 309ccf7 cannonlake: update processor power limits configuration by Sumeet R Pawnikar · 4 years, 3 months ago
  40. e6e9fa6 soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options by Christian Walter · 4 years, 3 months ago
  41. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  42. f5627e8 soc/intel/cannonlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 4 months ago
  43. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  44. 1af482c9 soc/intel/cannonlake: Set correct serirq mode by Jeremy Soller · 5 years ago
  45. fa043c4 soc/intel/cannonlake: Plumb TetonGlacierMode into dt by Edward O'Callaghan · 4 years, 6 months ago
  46. 646109a soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume by Subrata Banik · 4 years, 6 months ago
  47. d137150 {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC by Wim Vervoorn · 4 years, 8 months ago
  48. d367503 soc/intel/cannonlake: Disable USB2 PHY Power gating by Surendranath Gurivireddy · 4 years, 10 months ago
  49. 1f30de0 soc/intel/cannonlake: set FSP param to enable or skip GOP by Michael Niewöhner · 4 years, 10 months ago
  50. 58e9670 soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE by Kane Chen · 4 years, 10 months ago
  51. d5f645c soc/intel: Replace config_of_path() with config_of_soc() by Kyösti Mälkki · 4 years, 11 months ago
  52. 8cced29 soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage by Subrata Banik · 5 years ago
  53. 87bb5f5 soc/intel/cannonlake: Add config for sata devslp pad reset configuration by Aamir Bohra · 5 years ago
  54. 13e902d soc/intel/cannonlake: Allow coreboot to handle SPI lockdown by Subrata Banik · 5 years ago
  55. c42ef56 soc/intel/cannonlake: Add ability to disable Heci1 by Bora Guvendik · 5 years ago
  56. b0b9905 soc/intel/cannonlake: Add config to disable display audio codec by Aamir Bohra · 5 years ago
  57. 662c61d soc/intel/cnl: Add provision to configure SD controller write protect pin by Aamir Bohra · 5 years ago
  58. b9c1850 soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC by Aamir Bohra · 5 years ago
  59. 06cc764 soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage by Subrata Banik · 5 years ago
  60. 990a05d soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown by Subrata Banik · 5 years ago
  61. 47ea451 soc/intel/cannonlake: Correct the data type of serial_io_dev by Aamir Bohra · 5 years ago
  62. 28dc7dc soc/intel: Use config_of_path(SA_DEVFN_ROOT) by Kyösti Mälkki · 5 years ago
  63. 8417485 soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP by Nico Huber · 5 years ago
  64. 903b40a soc/intel: Replace uses of dev_find_slot() by Kyösti Mälkki · 5 years ago
  65. 85d3b40 soc/intel/cannonlake: fix use of legacy 8254 timer by Matt DeVillier · 5 years ago
  66. ddbf2c4 soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD. by Tim Wawrzynczak · 5 years ago
  67. 43a3c51 mb/google/sarien: Disable S5 wake on LAN by default by Eric Lai · 5 years ago
  68. c338507 soc/{amd,intel}/chip: Use local include for chip.h by Elyes HAOUAS · 5 years ago
  69. 78fbe3d soc/intel/cannonlake: Add null reference check for Cnvi and Xdci by Aamir Bohra · 5 years ago
  70. 7f1a0e6 Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" by Lijian Zhao · 5 years ago
  71. 41dad28 soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML by Subrata Banik · 5 years ago
  72. 1dde7cc Replace remaining IS_ENABLED(CONFIG_*) with CONFIG() by Nico Huber · 5 years ago
  73. dffa8d0 soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree by Krishna Prasad Bhat · 5 years ago
  74. 009e6cb soc/intel/cannonlake: Ignore GBE LTR by Lijian Zhao · 5 years ago
  75. 9bc9da9d soc/intel/cannonlake: Configure voltage margining policies by Krzysztof Sywula · 5 years ago
  76. caa85f2 soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports by Krishna Prasad Bhat · 5 years ago
  77. 4dfd8d6 soc/intel/cannonlake: Fix return values for get_param_value by Furquan Shaikh · 5 years ago
  78. 41483c9 soc/intel/cannonlake: Add required FSP UPD changes for CML by Subrata Banik · 6 years ago
  79. cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
  80. 8aadab7 soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN# by Rizwan Qureshi · 5 years ago
  81. 4185de5 soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree by Jeremy Soller · 5 years ago
  82. d01a995 src/soc/intel/cannonlake: Add PsysPmax setting by Gaggery Tsai · 5 years ago
  83. 3bb8c24 soc/intel/cannonlake: Configure serial debug uart by Ronak Kanabar · 6 years ago
  84. 3126964 soc/intel/cannonlake: Provide interface to update TCC offset by John Su · 6 years ago
  85. 55012d1 soc/intel/cannonlake: Add FSP UPD for minimum assertion width by Duncan Laurie · 6 years ago
  86. 09f7382 soc/intel/cannonlake: Enable CNVi based on devicetree by Maulik V Vaghela · 6 years ago
  87. 9bf1d8f soc/intel/cannonlake: SATA and DMI power optimize by Lijian Zhao · 6 years ago
  88. ae75400 soc/intel/cannonlake: Add Acoustic features by Lijian Zhao · 6 years ago
  89. 79152f3 soc/intel/cannonlake: Add options for pcie ltr by Lijian Zhao · 6 years ago
  90. ae4eee1 soc/intel/cannonlake: Remove depreciated UPD selection by Lijian Zhao · 6 years ago
  91. 7cf9862 soc/intel/cannonlake: Disable Legacy PME for Root ports by Subrata Banik · 6 years ago
  92. d44221f Move compiler.h to commonlib by Nico Huber · 6 years ago
  93. 742c6fe soc/intel/cannonlake: Move the FSP related callbacks to separate files by Rizwan Qureshi · 6 years ago