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review.coreboot.org / coreboot / 3dbea29ee65c99ae09690765f20869b46464e66a / src / soc / intel / braswell / ramstage.c
  1. b0eb594 soc/braswell: Set max frequency to be turbo frequency by Hannah Williams · 9 years ago
  2. 45a221d soc/braswell: Fix P-state table by Subrata Banik · 9 years ago
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. 94b856e FSP 1.1: Move common FSP code by Lee Leahy · 9 years ago
  5. e73da80 braswell: Switch to using common ACPI _SWS code by Duncan Laurie · 9 years ago
  6. 789f2b6 fsp1_1: provide binding to UEFI version by Aaron Durbin · 9 years ago
  7. 3247172 Braswell: Add Braswell SOC support by Lee Leahy · 9 years ago
  8. 25509ee Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  9. 77ff0b1 Braswell: Use Baytrail as Comparison Base by Lee Leahy · 9 years ago