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review.coreboot.org / coreboot / 3dbea29ee65c99ae09690765f20869b46464e66a / src / soc / intel / baytrail / spi.c
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  2. 4460703 Drop "See file CREDITS..." comment by Stefan Reinauer · 9 years ago
  3. 4d3de7e bootstate: remove need for #ifdef ENV_RAMSTAGE by Aaron Durbin · 9 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 18ea2d3 baytrail: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  6. 9ef9d85 bootstate: use structure pointers for scheduling callbacks by Aaron Durbin · 9 years ago
  7. bde6d30 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer by Kevin Paul Herbert · 10 years ago
  8. f2612a1 x86: Initialize SPI controller explicitly during PCH init by David Hendricks · 10 years ago
  9. ec9293f spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions. by Gabe Black · 10 years ago
  10. 87f3b4e spi: Remove the spi_set_speed and spi_cs_is_valid functions. by Gabe Black · 10 years ago
  11. 99a3bba intel/baytrail: Spelling fixes by Martin Roth · 10 years ago
  12. 4177db5 baytrail/rambi: spi, charger, and audio updates by Aaron Durbin · 10 years ago
  13. 1110495 SPI: Split writes using spi_crop_chunk() by Kyösti Mälkki · 10 years ago
  14. 93d9f92 spi: Change spi_xfer to work in units of bytes instead of bits. by Gabe Black · 10 years ago
  15. 1e18735 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave. by Gabe Black · 10 years ago
  16. 9a7d7bc baytrail: add initial support by Aaron Durbin · 11 years ago