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review.coreboot.org / coreboot / 3d45c4077665a17735c69576638dc510f96a2dff / src / cpu / intel
  1. 3d45c40 timestamps: Stash early timestamps in CAR_GLOBAL by Kyösti Mälkki · 11 years ago
  2. e28bd4a timestamps intel: Move timestamp scratchpad to chipset by Kyösti Mälkki · 11 years ago
  3. 8eaf1e7 cpu/intel/model_67x: Add missing include by Kyösti Mälkki · 11 years ago
  4. 4c3ab73 cpu: Fix spelling by Martin Roth · 11 years ago
  5. 2c516ed usbdebug: Drop old includes by Kyösti Mälkki · 11 years ago
  6. 8ee04d7 usbdebug: Put ehci_debug_info in CAR_GLOBAL by Kyösti Mälkki · 11 years ago
  7. 7cced0d ec: Add romstage function for checking and rebooting EC by Duncan Laurie · 11 years ago
  8. e49679d usbdebug: Drop temporary disables of log output by Kyösti Mälkki · 11 years ago
  9. 22dcdd9 Add support for Intel Nehalem CPU by Vladimir Serbinenko · 11 years ago
  10. 66da043 haswell: allow for disabled hyperthreading by Aaron Durbin · 11 years ago
  11. 4e01cfb cpu/intel/haswell/Kconfig: Intend help text with two spaces by Paul Menzel · 11 years ago
  12. 5b54d35 haswell: enable cache-as-ram migration by Aaron Durbin · 11 years ago
  13. 38c326d x86: add thread support by Aaron Durbin · 11 years ago
  14. 3f5f6d8 Drop prototype guarding for romcc by Stefan Reinauer · 11 years ago
  15. 648d166 copy_and_run: drop boot_complete parameter by Stefan Reinauer · 11 years ago
  16. 39ecc65 haswell: use asmlinkage for assembly-called funcs by Aaron Durbin · 11 years ago
  17. 7cb1ba9 haswell: use tsc for udelay() by Aaron Durbin · 11 years ago
  18. c46cc6f haswell: 24MHz monotonic time implementation by Aaron Durbin · 11 years ago
  19. 2c88cc0 Intel microcode: Return when `microcode_updates` is `NULL` by Vladimir Serbinenko · 11 years ago
  20. 23f5016 haswell: enable ROM caching by Aaron Durbin · 11 years ago
  21. 13cc952 haswell: keep ROM cache enabled by Aaron Durbin · 11 years ago
  22. 0f0fe10 haswell: use new interface to disable rom caching by Aaron Durbin · 11 years ago
  23. af3158c lynxpoint: split clearing and enabling of smm by Aaron Durbin · 11 years ago
  24. 8dddc30 haswell: Add microcode for ULT C0 stepping 0x40651 by Duncan Laurie · 11 years ago
  25. d02bb62 haswell: vboot path support in romstage by Aaron Durbin · 11 years ago
  26. c0cbd6e haswell: use dynamic cbmem by Aaron Durbin · 11 years ago
  27. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  28. 71c7cdc Intel: Update CPU microcode for 6fx CPUs by Stefan Reinauer · 11 years ago
  29. b70197b Intel: Update CPU microcode for 106cx CPUs by Stefan Reinauer · 11 years ago
  30. b631f9c Intel: Update CPU microcode script by Stefan Reinauer · 11 years ago
  31. 1ad5564 lynxpoint: Add helper functions for reading PM and GPIO base by Duncan Laurie · 11 years ago
  32. b86113f haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option by Aaron Durbin · 11 years ago
  33. f7cdfe5 haswell: implement ramstage caching in SMM region by Aaron Durbin · 12 years ago
  34. 8ce667e haswell: add multipurpose SMM memory region by Aaron Durbin · 12 years ago
  35. 67481ddc haswell: set TSEG as WB cacheable in romstage by Aaron Durbin · 12 years ago
  36. 738af67 haswell: support for parallel SMM relocation by Aaron Durbin · 12 years ago
  37. bf396ff haswell: use s3_resume field in romstage_handoff by Aaron Durbin · 12 years ago
  38. ef4275b x86: protect against abi assumptions from compiler by Aaron Durbin · 12 years ago
  39. e2d9e5b haswell: support for CONFIG_RELOCATABLE_RAMSTAGE by Aaron Durbin · 12 years ago
  40. a146d58 ramstage: prepare for relocation by Aaron Durbin · 12 years ago
  41. 2c3f161 Intel: Update CPU microcode for Sandybridge/Ivybridge CPUs by Stefan Reinauer · 11 years ago
  42. 511c4b7 Intel: Update CPU microcode for 1067x CPUs by Stefan Reinauer · 11 years ago
  43. 8c20399 haswell: wait 10ms after INIT IPI by Aaron Durbin · 12 years ago
  44. 305b1f0 haswell: Parallel AP bringup by Aaron Durbin · 12 years ago
  45. 98ffb42 intel microcode: split up microcode loading stages by Aaron Durbin · 12 years ago
  46. 7492ec1 haswell: add romstage_after_car() function by Aaron Durbin · 12 years ago
  47. 2ad1dba haswell: move call site of save_mrc_data() by Aaron Durbin · 12 years ago
  48. 38d9423 haswell: romstage: pass stack pointer and MTRRs by Aaron Durbin · 12 years ago
  49. a267161 haswell: unify romstage logic by Aaron Durbin · 12 years ago
  50. 3d0071b haswell: adjust CAR usage by Aaron Durbin · 12 years ago
  51. 7af2069 haswell: enable caching before SMM initialization by Aaron Durbin · 12 years ago
  52. 24614af haswell: Clear correct number of MCA banks by Aaron Durbin · 12 years ago
  53. a416bfe haswell: move definition of CORE_THREAD_COUNT_MSR by Aaron Durbin · 12 years ago
  54. 29ffa54 haswell: Use SMM Modules by Aaron Durbin · 12 years ago
  55. 6dccedd x86 intel: Add Firmware Interface Table support by Aaron Durbin · 12 years ago
  56. 51254049 haswell: Add ULT CPUID and updated microcode by Duncan Laurie · 12 years ago
  57. dc278f8 haswell: Properly Guard Engergy Policy by CPUID by Aaron Durbin · 12 years ago
  58. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago
  59. 5a22b14 Fix socket LGA775 by Kyösti Mälkki · 11 years ago
  60. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  61. 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster by Stefan Reinauer · 12 years ago
  62. 8cc8468 Intel: Replace MSR 0xcd with MSR_FSB_FREQ by Patrick Georgi · 12 years ago
  63. 644e83b speedstep: Deduplicate some MSR identifiers by Patrick Georgi · 12 years ago
  64. 223af0d document Intel VMX locking behavior by Mike Frysinger · 12 years ago
  65. 6fe0cab Extend CBFS to support arbitrary ROM source media. by Hung-Te Lin · 12 years ago
  66. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  67. a42e2f4 Add spinlock to serialize Intel microcode updates by Stefan Reinauer · 12 years ago
  68. 455f4b4 Fix CONFIG_MAX_CPU set to 1 CPU build problem by Stefan Reinauer · 12 years ago
  69. 08067ba ivybridge: Catch unknown CPU revisions by Stefan Reinauer · 12 years ago
  70. f5a11aa Initialize the VMX MSR by Marc Jones · 12 years ago
  71. 5986eda Revert "Remove code that enables/disables VMX in coreboot on chromebooks." by Marc Jones · 12 years ago
  72. bb9dff5 sandybridge: Correct reporting of cores and threads by Stefan Reinauer · 12 years ago
  73. d16d576 Leave power control registers unlocked by Sameer Nanda · 12 years ago
  74. 68d7c7a cpu/intel/model_1067x: Add proper c-state/p-state/thermal support by Nico Huber · 12 years ago
  75. bf10bc3 intel/socket_BGA956: enable speedstep, CAR, MMX, SSE by Patrick Georgi · 12 years ago
  76. a74af56 Overhaul speedstep code by Nico Huber · 12 years ago
  77. 252d39b Fix some indentation flaws and break very long lines by Nico Huber · 12 years ago
  78. ad874e3 Correct FSB reading in speedstep ACPI by Nico Huber · 12 years ago
  79. 41392df Merge cpu/intel/acpi.h into cpu/intel/speedstep.h by Nico Huber · 12 years ago
  80. bef3d34 Add support for socket LGA775 by Stefan Tauner · 12 years ago
  81. e5fe3ac Fix typo in mPGA603 socket by Kyösti Mälkki · 12 years ago
  82. 0279036 Remove chip.h files without config structure by Kyösti Mälkki · 12 years ago
  83. 00b579a buildsystem: Make CPU microcode updating more configurable by Alexandru Gagniuc · 12 years ago
  84. 0a78f91 Intel model_106cx: change CAR to HT-capable by Kyösti Mälkki · 12 years ago
  85. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  86. 0db6820 Synchronize rdtsc instructions by Stefan Reinauer · 12 years ago
  87. df0fbc7 Intel CPUs: Fix counting of CPU cores by Kyösti Mälkki · 12 years ago
  88. 51676b1 Revert "Use broadcast SIPI to startup siblings" by Sven Schnelle · 12 years ago
  89. a2701c6 Revert "remove CONFIG_SERIAL_CPU_INIT" by Sven Schnelle · 12 years ago
  90. 5563211 CPU: Add option to set TCC activation offset by Duncan Laurie · 12 years ago
  91. d6aca0b ACPI: Add a method to notify OS to re-read _PPC by Duncan Laurie · 12 years ago
  92. 0eefa00 ACPI: Add function to write _PPC using NVS by Duncan Laurie · 12 years ago
  93. 0b7b7b6 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs by Stefan Reinauer · 12 years ago
  94. c65a36e Enable Microcode in CBFS for all SandyBridge/IvyBridge systems by Stefan Reinauer · 12 years ago
  95. c0f2cfb Fix comment to reference IvyBridge, too by Stefan Reinauer · 12 years ago
  96. 6d29c73 Include SandyBridge Microcode when IvyBridge is enabled by Stefan Reinauer · 12 years ago
  97. 0aa5b09 Fix date output in Microcode update by Stefan Reinauer · 12 years ago
  98. 22935e1 CPU: Set flex ratio to nominal TDP ratio in bootblock by Duncan Laurie · 12 years ago
  99. 4e4320f CPU: Update ivybridge PP1 current limit value by Duncan Laurie · 12 years ago
  100. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago