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review.coreboot.org / coreboot / 215f27856399b1e4cfe30268fad61bf821af3c19 / src / southbridge
  1. 1d89f14 Intel 82801dx: compile early_smbus as separate object by Kyösti Mälkki · 12 years ago
  2. 26b00e6 Refactor some alignment handling by Patrick Georgi · 12 years ago
  3. a20132b Do not produce temp s3.rom if the board doesn't need it. by zbao · 12 years ago
  4. e380b0f More portable s3 scratch space creation by Patrick Georgi · 12 years ago
  5. 9bcdbf8 Add Southbridge support for S3. by zbao · 12 years ago
  6. 2c2e78d Unify IO APIC address specification by Patrick Georgi · 12 years ago
  7. 8e07382 Add support for Intel Panther Point PCH by Stefan Reinauer · 12 years ago
  8. 01bd79f Add sb800 spi support. by zbao · 12 years ago
  9. 6b89b4c Add support for RDC R8610 Southbridge by Rudolf Marek · 12 years ago
  10. 8a85bcc i82801gx: Support power-on-after-power-fail better by Patrick Georgi · 13 years ago
  11. c07466b i82801gx: Use CMOS variable if available for power-on on power failure by Patrick Georgi · 13 years ago
  12. 35e1c86 VIA southbridge K8T890: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
  13. c5fc7db Move C labels to start-of-line by Patrick Georgi · 12 years ago
  14. 399fcdd AMD southbridge: remove sp5100 by Kyösti Mälkki · 12 years ago
  15. b05bf5b amd/sb600: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  16. c877d22 Force SB600 bootblock to use I/O for PCI config by Dave Frodin · 13 years ago
  17. 5257c27 Force SB700 bootblock code to use I/O for PCI config cycles. by Dave Frodin · 13 years ago
  18. 2eacc0e Force SB800 bootblock to use I/O for PCI config by Dave Frodin · 13 years ago
  19. da52aed Fixes Fam10/SR5650 cpu not recognized message. by Dave Frodin · 13 years ago
  20. a22f78b nvidia/mcp55: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  21. 0e992be amd/sb700: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  22. c46f450 intel/i82801cx: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  23. e0ddbc7 sis/sis966: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  24. 7389378 intel/i82801ex: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  25. 62246f7 intel/sch: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  26. 024d8d9 amd/sb800: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  27. 334328a Avoid ../../.. paths in ASL files by Patrick Georgi · 12 years ago
  28. 472efa6 Remove whitespace. by Patrick Georgi · 12 years ago
  29. 152738f amd/amd8111: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  30. a842aec intel/82801dx: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  31. 131c936 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper by Kerry Sheh · 12 years ago
  32. b06bd8d i3100: configure pci irqs by Sven Schnelle · 13 years ago
  33. 56f2a6d CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir by Kerry Sheh · 13 years ago
  34. f61ad93 i3100: add sata_ports_implemented option by Sven Schnelle · 13 years ago
  35. ab46c15 i3100: Add init sequence by Sven Schnelle · 13 years ago
  36. 0f1dc4e Add subsystem callbacks for VT8237x and VT890 family of chipsets by Rudolf Marek · 13 years ago
  37. a31bb07 Unify ID_SECTION_OFFSET and mark it deprecated by Patrick Georgi · 13 years ago
  38. 75fb40e Add missing HAVE_HARD_RESET by Sven Schnelle · 13 years ago
  39. b5d81eb rs780: correct comment in switching_gpp_configurations() by Jonathan A. Kollasch · 13 years ago
  40. f3fe3d2 rs780: use bitwise rather than boolean not by Jonathan A. Kollasch · 13 years ago
  41. 8bd41cd rs780: power down GPPSB SB lane pads in correct PCIe core by Jonathan A. Kollasch · 13 years ago
  42. f154c01 Persimmon audio codec verb patch. by Marc Jones · 13 years ago
  43. 4c132bb Fix AMD 8132 and 8151 southbridge builds by Kyösti Mälkki · 13 years ago
  44. 7519d77 RS780: print the vgainfo by Denis 'GNUtoo' Carikli · 13 years ago
  45. b532057 make GPIOs and misc configurable via devicetree by Florian Zumbiehl · 13 years ago
  46. 98236ca make INT[EFGH]# of vt8237 configurable as gpio via devicetree by Florian Zumbiehl · 13 years ago
  47. 6a3e8d6 some black magic for initializing the old version of the k8t800 by Florian Zumbiehl · 13 years ago
  48. 1b940fd implement usb2 termination and dpll delay setting for vt8237r by Florian Zumbiehl · 13 years ago
  49. 28bdd8d i3100: Add HAVE_HARD_RESET by Sven Schnelle · 13 years ago
  50. 912d891 vt8237: add support for setting the power state after loss of power by Florian Zumbiehl · 13 years ago
  51. 50dadfb compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD by Florian Zumbiehl · 13 years ago
  52. be7d8dc support for different location of HT registers in old version of K8T800 by Florian Zumbiehl · 13 years ago
  53. 2e2b84e move function from header file to .c file by Stefan Reinauer · 13 years ago
  54. 0802ad9 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible by Florian Zumbiehl · 13 years ago
  55. 1e1e859 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() by Florian Zumbiehl · 13 years ago
  56. 7b1d295 add support for 1106:3188 (host controller of the old version of k8t800) by Florian Zumbiehl · 13 years ago
  57. 86bb007 in vt8237r_enable(), write function enables only to ISA bridge config space by Florian Zumbiehl · 13 years ago
  58. 3cd0ae2 Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues. by Patrick Georgi · 13 years ago
  59. e037f9f add support for writing to SMBus with vt8237 by Florian Zumbiehl · 13 years ago
  60. 8c4cf18 add support for 1106:3188 (host controller of the old version of k8t800) by Florian Zumbiehl · 13 years ago
  61. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  62. 20fc631 Fix usb debug dongle support by Sven Schnelle · 13 years ago
  63. af3dce9 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c. by Stefan Reinauer · 13 years ago
  64. 914377e Get rid of the old romstage-as-bootblock ROM layout by Patrick Georgi · 13 years ago
  65. 0f8590f sb600: Implement EHCI workaround by Patrick Georgi · 13 years ago
  66. 9bfa1c8 Added smbus block read/write for amd8111 by Oskar Enoksson · 13 years ago
  67. b2f173e i82801gx: Fix port status in AHCI mode by Sven Schnelle · 13 years ago
  68. 906f9ae i82801gx: Add setting for C4onC3 mode by Sven Schnelle · 13 years ago
  69. 718afbe i82801gx: Add write and read/write block functions by Sven Schnelle · 13 years ago
  70. 3c97679 i82801gx: Don't set I/O base address to static value by Sven Schnelle · 13 years ago
  71. f3b0500 SB800: Hide unused gpp ports by Kerry Sheh · 13 years ago
  72. 1465385 sch: strip quotes around cmc.bin filename by Patrick Georgi · 13 years ago
  73. 2588db4 i82801dx: Replace romstage printk's by Kyösti Mälkki · 13 years ago
  74. 328a694 AMD CPU and chipset fixes for compilation with gcc 4.6 by Stefan Reinauer · 13 years ago
  75. ab87254 use acpi.h include instead of manually adding acpi_slp_type. by Stefan Reinauer · 13 years ago
  76. 971ebd8 Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6 by Stefan Reinauer · 13 years ago
  77. a251dee Use default table creator macro for all SSDTs by Stefan Reinauer · 13 years ago
  78. 390a337 amd/sb600: Enable COM2 at all times in early setup by Patrick Georgi · 13 years ago
  79. 55437c5 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION by Kerry Sheh · 13 years ago
  80. 0e6344e SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode by Kerry Sheh · 13 years ago
  81. d7e856b9 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE by Kerry Sheh · 13 years ago
  82. 75df106 mainboard: complete the sb800 devicetree even device is off by Kerry Sheh · 13 years ago
  83. d4a0e7d sb800: Add sata ahci/raid mode kconfig option by Kerry Sheh · 13 years ago
  84. 03f82bd Use ACPI text fields consistently with all other boards by Stefan Reinauer · 13 years ago
  85. 3c59158 AMD SB800 early console use fix by efdesign98 · 13 years ago
  86. 8c69b1d rs780: hide unused gfx ports and gpp ports by Kerry Sheh · 13 years ago
  87. 4e22a3b Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods by Tobias Diedrich · 14 years ago
  88. 6209c82 AMD SB800 southbridge update by Kerry She · 13 years ago
  89. feed329 AMD F14 southbridge update by Kerry She · 13 years ago
  90. 16d3ec6 Adjust some code/comment of sb700 sata init by Wang Qing Pei · 14 years ago
  91. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  92. 4edbe00 Move AMD SB800 early clock setup. by Scott Duplichan · 13 years ago
  93. 5a91692 Set SB800 ROM decode size based on kconfig. by Marc Jones · 13 years ago
  94. 23b2152 Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and by Rudolf Marek · 13 years ago
  95. 811787a i82801gx: read RTC status register to prevent IRQ storm by Sven Schnelle · 13 years ago
  96. 3e706b6 amd southbirdge sb800 wrapper, pci bridge fix by Kerry She · 13 years ago
  97. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  98. 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago
  99. d1cb0ee sb800: move spi prefetch and fast read mode to sb bootblock. by Stefan Reinauer · 13 years ago
  100. 8fed77a ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic by Scott Duplichan · 13 years ago