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review.coreboot.org / coreboot / 0a18d64d00a9fcfd096c14f28e7b4d62bca0a829 / src / northbridge / intel / sandybridge / northbridge.c
  1. 5e29f00 Intel and GFXUMA: drop redundant use of lb_add_memory_range() by Kyösti Mälkki · 12 years ago
  2. 7f189cc Intel Sandybridge and UMA: use mmio_resource() by Kyösti Mälkki · 12 years ago
  3. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 12 years ago
  4. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  5. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  6. 496f4a0 SandyBridge: Add another PCI device ID for northbridge by Walter Murphy · 12 years ago
  7. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  8. bb11e60 Hook up MRC cache update by Stefan Reinauer · 12 years ago
  9. 1244f4b Rework Sandybridge MRC cache handling by Stefan Reinauer · 12 years ago
  10. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  11. 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
  12. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago