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review.coreboot.org / coreboot / 00c8c4a31632150fa711493f39e727da950ebe9f / src / southbridge / amd
  1. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  2. 4edbe00 Move AMD SB800 early clock setup. by Scott Duplichan · 13 years ago
  3. 5a91692 Set SB800 ROM decode size based on kconfig. by Marc Jones · 13 years ago
  4. 3e706b6 amd southbirdge sb800 wrapper, pci bridge fix by Kerry She · 13 years ago
  5. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  6. 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago
  7. d1cb0ee sb800: move spi prefetch and fast read mode to sb bootblock. by Stefan Reinauer · 13 years ago
  8. 8fed77a ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic by Scott Duplichan · 13 years ago
  9. 486e032 Revert changes to set the sb800 to AHCI mode. by Marc Jones · 13 years ago
  10. 44c1d31 re-indent, so files conform to coding guidelines. by Stefan Reinauer · 13 years ago
  11. 76d53b2 trivial remove blanks at the end of line by Kerry She · 13 years ago
  12. 991f880 This patch fix a AMD sb800 wrapper compile warning: by Kerry She · 13 years ago
  13. 3f0075b cimx_wrapper/sb800: Fix indent in late.c:sb800_enable() by Peter Stuge · 13 years ago
  14. a64ab46 Update gpp port configuration. by Scott Duplichan · 13 years ago
  15. be8fae1 Program the I/O APIC ID. by Scott Duplichan · 13 years ago
  16. f191c72 Enable AHCI mode and hide IDE controller to reduce boot time. by Scott Duplichan · 13 years ago
  17. e78ae24 Configure CIMx to use 33 MHz fast mode for SPD read. by Scott Duplichan · 13 years ago
  18. faafd14 by Kerry She · 13 years ago
  19. eb995c2 by Kerry She · 13 years ago
  20. 3e4fb9d more ifdef -> if fixes. by Stefan Reinauer · 13 years ago
  21. d4814bd more ifdef -> if fixes by Stefan Reinauer · 13 years ago
  22. 305f2f5 drop dead code from sb800 bootblock by Stefan Reinauer · 13 years ago
  23. 582748f Fix some more misuses of ifdef/if defined by Stefan Reinauer · 13 years ago
  24. b3ae186 * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value by Stefan Reinauer · 13 years ago
  25. 484281b by Marc Jones · 13 years ago
  26. 5005bb06 Unify use of post_code by Alexandru Gagniuc · 13 years ago
  27. 61aee5f In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__. by Stefan Reinauer · 13 years ago
  28. d3de3ee Add the SR5650 & SP5100 to the Kconfig and Makefile.inc by Zheng Bao · 13 years ago
  29. c342223 SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx. by Zheng Bao · 13 years ago
  30. 98fcc09 Add AMD SR56x0 support. by Zheng Bao · 13 years ago
  31. ea1c0a7 Fix power_on_after_fail handling on AMD SB600 by Josef Kellermann · 13 years ago
  32. 199c694 It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. by Rudolf Marek · 13 years ago
  33. 855224b Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600 by Josef Kellermann · 13 years ago
  34. dd6c1e6 SERIAL_POST was renamed to CONSOLE_POST a while ago by Stefan Reinauer · 14 years ago
  35. cf37a59 Removed LPC DMA Deadlock workaround... by Josef Kellermann · 14 years ago
  36. 63e62b0 This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code. by Frank Vibrans · 14 years ago
  37. 74ad66c Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC. by Rudolf Marek · 14 years ago
  38. 20ecc5a RS690: Provide support for MMCONF. by Josef Kellermannseppk · 14 years ago
  39. a96b218 Fix subvendor/subdevice programming on RS690 by Josef Kellermann · 14 years ago
  40. 86bd99a by Rudolf Marek · 14 years ago
  41. 1c2734f Fix Bimini build by Stefan Reinauer · 14 years ago
  42. a5c949e Trivial. Re-indent the code. by Zheng Bao · 14 years ago
  43. 066cbe0 Set the phy via weak function. As Rudolf called. by Zheng Bao · 14 years ago
  44. 9dcca3b Set the SB800 SATA PHY correctly. by Zheng Bao · 14 years ago
  45. a302b58 Change fadt revision back to 3. by Zheng Bao · 14 years ago
  46. 72cc87f Now bimini can boot linux to login. by Zheng Bao · 14 years ago
  47. a4da254 S3 feanture of SB800. Compiliant with SB700. by Zheng Bao · 14 years ago
  48. 79c04d5 Move some board specific functions to sb800.h. by Zheng Bao · 14 years ago
  49. d098575 This sb800 code is derived from sb700. by Zheng Bao · 14 years ago
  50. a19c622 remove the code which is not ready to release. by Zheng Bao · 14 years ago
  51. 752ab0d remove the code which is not ready to release. by Zheng Bao · 14 years ago
  52. fb433be drop unused files by Stefan Reinauer · 14 years ago
  53. 09e0e9a change a readable way to fix SB800 CIMX "multi-character constant warning". by Kerry She · 14 years ago
  54. e925965 src/southbridge/amd/cimx_wrapper: Run dos2unix on the files. by Uwe Hermann · 14 years ago
  55. d6a1373 AMD SB800: Drop component prefix from filenames. by Uwe Hermann · 14 years ago
  56. 84f59ae Add AMD SB800 southbridge support via cimx_wrapper. by Kerry She · 14 years ago
  57. 40992d3 Add RS785(RS880) support. Just few pci_ids. by Zheng Bao · 14 years ago
  58. 8098e42 Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code by Nils Jacobs · 14 years ago
  59. 84be0f5 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) by Nils Jacobs · 14 years ago
  60. ef15ff4 -Clean up some comments. by Nils Jacobs · 14 years ago
  61. bb9bcee Set the ROMSIZE as 4MB. by Zheng Bao · 14 years ago
  62. c436953 Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well. by Rudolf Marek · 14 years ago
  63. e8191b4 I was bitten by the rename, this is part of r6165. by Rudolf Marek · 14 years ago
  64. 3310934 Following patch makes just one fadt.c file. For SB700. by Rudolf Marek · 14 years ago
  65. 6e7efb7 Add TINY_BOOTBLOCK support for AMD SB700. by Uwe Hermann · 14 years ago
  66. 42b1c43 Merge enable_rom.c files into bootblock.c files. by Uwe Hermann · 14 years ago
  67. 4a778db Add missing instruction break. by Zheng Bao · 14 years ago
  68. 836ae29 first round name simplification. drop the <component>_ prefix. by stepan · 14 years ago
  69. 29cb06a Before lane reversal, by Zheng Bao · 14 years ago
  70. 6b8c721 Trivial. Reindent and dos2unix. by Zheng Bao · 14 years ago
  71. e89d8a5 AMD SB600: Add TINY_BOOTBLOCK support. by Uwe Hermann · 14 years ago
  72. 1f7d3c5 AMD-8111: Add TINY_BOOTBLOCK support. by Uwe Hermann · 14 years ago
  73. 88dc531 This patch solves crashes and BSODs that occur when booting Win7 with by Scott Duplichan · 14 years ago
  74. 9bd9a90 Unify DIMM SPD addressing. For Geode, change the by Patrick Georgi · 14 years ago
  75. 1c00927 Revert sblk/sblink change, use sblk like the rest of the codebase does. by Uwe Hermann · 14 years ago
  76. d7acdfb This patch enables SB700 option PrefetchEnSPIFromHost in early setup. by Scott Duplichan · 14 years ago
  77. 676d029 In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set by Liu Tao · 14 years ago
  78. dfecd27 We currently read the CPU HT speed from HT chain 0's register. by Liu Tao · 14 years ago
  79. c6a1062 Add more missing GPL-headers, fix inconsistencies in others. by Uwe Hermann · 14 years ago
  80. 51eafde Enable or disable the power button in Kconfig by Peter Stuge · 14 years ago
  81. f2573bd Fix a stupid bug in rs780 and rs690 code. by Zheng Bao · 14 years ago
  82. 74d1a6e We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it. by Uwe Hermann · 14 years ago
  83. 470e182 Same applies for SB600. by Rudolf Marek · 14 years ago
  84. e522164 by Rudolf Marek · 14 years ago
  85. 14cc927 Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install by Rudolf Marek · 14 years ago
  86. 2a5101a Trivial. Spelling check. by Zheng Bao · 14 years ago
  87. a3bd1b1 RS780 function ProgK8TempMmioBase is setting a reserved by Scott Duplichan · 14 years ago
  88. 5692c57 - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 by Patrick Georgi · 14 years ago
  89. ae3f2b3 Allow selecting the physical USB Debug Port on AMD SB700. by Uwe Hermann · 14 years ago
  90. 8463dd9 Rename build system variables to be more intuitive, and by Patrick Georgi · 14 years ago
  91. 65e6034 Only show the USB Debug Port kconfig option to the user if a mainboard by Uwe Hermann · 14 years ago
  92. dc3aa7a Various Debug Port southbridge implementation fixes / cosmetics. by Uwe Hermann · 14 years ago
  93. ff492b1 Make SB600/SB700 more similar for easier diffs (trivial). by Uwe Hermann · 14 years ago
  94. b015d02 Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure. by Uwe Hermann · 14 years ago
  95. 7df50a8 Here is a proposed way how to handle the SATA PHY settings on SB700. It by Rudolf Marek · 14 years ago
  96. 50b78b6 Print an error and correct pci scan limits. Skip sb700 ISA DMA init if needed. by Juhana Helovuo · 14 years ago
  97. a4c0a1d Make timer2 the default choice for TSC initialization. by Patrick Georgi · 14 years ago
  98. 625a0cb Remove unused ide0_enable and sata0_enable entries from SB7xx and SB600. by Rudolf Marek · 14 years ago
  99. 543f767 Tilapila supports both dual slot and single slot. The difference should be by Wang Qing Pei · 14 years ago
  100. ae7a425 Look for actual framebuffer size instead of hardcoding UMA by Rudolf Marek · 14 years ago