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review.coreboot.org / coreboot / 00b5f533615eac269d73af5f0e6c69cb498ca7d9 / src / cpu / intel / slot_1
  1. 00b5f53 treewide [Kconfig]: Remove useless comment by Elyes HAOUAS · 3 years, 7 months ago
  2. e76ce87 arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits by Kyösti Mälkki · 4 years, 3 months ago
  3. 99e0c7d src/cpu: Drop unneeded empty lines by Elyes HAOUAS · 4 years ago
  4. 268d257 cpu/intel/slot_1: Select 16KiB bootblock if console is enabled by Keith Hui · 4 years, 3 months ago
  5. c4b7027 src: Remove leading blank lines from SPDX header by Elyes HAOUAS · 4 years, 3 months ago
  6. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  7. 7a0bcb7 src/cpu: Replace GPLv2 long form headers with SPDX header by Elyes HAOUAS · 4 years, 3 months ago
  8. c49d7a3 src/: Replace GPL boilerplate with SPDX headers by Patrick Georgi · 4 years, 3 months ago
  9. ac95903 treewide: replace GPLv2 long form headers with SPDX header by Patrick Georgi · 4 years, 3 months ago
  10. 02363b5 treewide: Move "is part of the coreboot project" line in its own comment by Patrick Georgi · 4 years, 3 months ago
  11. 3fa3bf9 cpu/intel/slot_1: Cache romstage XIP execution by Arthur Heymans · 4 years, 9 months ago
  12. 1fa240a cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK by Arthur Heymans · 4 years, 9 months ago
  13. c05b1a6 Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol by Arthur Heymans · 4 years, 9 months ago
  14. 092fe55 intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER by Kyösti Mälkki · 4 years, 10 months ago
  15. 0d6ddf8 cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE by Kyösti Mälkki · 4 years, 10 months ago
  16. 838d8b0 AUTHORS: Move src/cpu/intel copyrights into AUTHORS file by Martin Roth · 5 years ago
  17. b28b6b5 arch/x86: Flip HAVE_MONOTONIC_TIMER default by Kyösti Mälkki · 5 years ago
  18. 8abf66e cpu/x86: Flip SMM_TSEG default by Kyösti Mälkki · 5 years ago
  19. d2b9ec1 src: Remove unneeded include "{arch,cpu}/cpu.h" by Elyes HAOUAS · 6 years ago
  20. aea8eec nb/intel/i440bx: Switch to POSTCAR_STAGE by Kyösti Mälkki · 6 years ago
  21. 54d6a28 cpu/intel/slot_1: Switch to different CAR setup by Kyösti Mälkki · 6 years ago
  22. e307343 src/cpu: Remove unneeded includes by Elyes HAOUAS · 6 years ago
  23. f3ec5ed cpu/intel/slot_1: Increase CAR size to 8KiB by Keith Hui · 7 years ago
  24. cdc5048 cpu/intel: Wrap lines at 80 columns by Lee Leahy · 7 years ago
  25. 26eeb0f cpu/intel: Fix brace issues detected by checkpatch.pl by Lee Leahy · 7 years ago
  26. 9d62e7e cpu/intel: Fix the spacing issues by Lee Leahy · 7 years ago
  27. 7b5f12b9 cpu/intel: Indent with tabs by Lee Leahy · 7 years ago
  28. 8160a2f intel post-car: Split legacy sockets by Kyösti Mälkki · 8 years ago
  29. 0cd338e Remove non-ascii & unprintable characters by Martin Roth · 8 years ago
  30. 07921540d intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP by Kyösti Mälkki · 8 years ago
  31. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  32. 439356f x86: remove cpu_incs as romstage Make variable by Aaron Durbin · 9 years ago
  33. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  34. 773485b intel CAR: Fix DCACHE_RAM_BASE for old sockets by Kyösti Mälkki · 10 years ago
  35. dc112e3 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF by Edward O'Callaghan · 10 years ago
  36. f7c55148 cpu: Trivial - drop trailing blank lines at EOF by Edward O'Callaghan · 10 years ago
  37. c06af9e Drop redundant select CACHE_AS_RAM by Kyösti Mälkki · 10 years ago
  38. 2c38f50 cpu/intel: Make all Intel CPUs load microcode from CBFS by Alexandru Gagniuc · 11 years ago
  39. 4c3ab73 cpu: Fix spelling by Martin Roth · 11 years ago
  40. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  41. 0279036 Remove chip.h files without config structure by Kyösti Mälkki · 12 years ago
  42. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  43. 1ac19e2 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. by Keith Hui · 13 years ago
  44. b14fb6a Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory. by Keith Hui · 14 years ago
  45. af8b2b9 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. by Uwe Hermann · 14 years ago
  46. 6529c2a Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x. by Keith Hui · 14 years ago
  47. 5e9c1cd Add missing include of model_6bx for slot_1. by Keith Hui · 14 years ago
  48. 6f2d20e Convert all Intel 440BX boards to Cache-as-RAM (CAR). by Uwe Hermann · 14 years ago
  49. 8463dd9 Rename build system variables to be more intuitive, and by Patrick Georgi · 14 years ago
  50. dd6ad34 license header fixes by Nils Jacobs · 14 years ago
  51. e1ec158 Add proper Slot 1 CPU support code/infrastructure. by Keith Hui · 14 years ago