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review.coreboot.org / coreboot / refs/heads/main / . / src / northbridge / intel / pineview / acpi / hostbridge.asl
blob: 5eae0cb74f9e22c89861af65b659c91d4b3b722c [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]2
3#include <arch/ioapic.h>
4
5Name(_HID,EISAID("PNP0A08")) // PCIe
6Name(_CID,EISAID("PNP0A03")) // PCI
7
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]8Name(_BBN, 0)
9
10Device (MCHC)
11{
12 Name(_ADR, 0x00000000) /* 0:0.0 */
13
14 OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
15 Field (MCHP, DWordAcc, NoLock, Preserve)
16 {
17 Offset (0x40), /* EPBAR */
18 EPEN, 1, /* Enable */
19 , 11,
20 EPBR, 24, /* EPBAR */
21
22 Offset (0x48), /* MCHBAR */
23 MHEN, 1, /* Enable */
24 , 13,
25 MHBR, 22, /* MCHBAR */
26
Angel Pons4d962b22020-07-07 03:00:24 +0200[diff] [blame]27 Offset (0x60), /* PCIe BAR */
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]28 PXEN, 1, /* Enable */
29 PXSZ, 2, /* BAR size */
30 , 23,
31 PXBR, 10, /* PCIec BAR */
32
33 Offset (0x68), /* DMIBAR */
34 DMEN, 1, /* Enable */
Angel Pons5f201ef2020-07-07 03:21:20 +0200[diff] [blame]35 , 11,
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]36 DMBR, 20, /* DMIBAR */
37
Angel Pons4d962b22020-07-07 03:00:24 +0200[diff] [blame]38 /* ... */
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]39
40 Offset (0x90), /* PAM0 */
41 , 4,
42 PM0H, 2,
43 , 2,
44 Offset (0x91), /* PAM1 */
45 PM1L, 2,
46 , 2,
47 PM1H, 2,
48 , 2,
49 Offset (0x92), /* PAM2 */
50 PM2L, 2,
51 , 2,
52 PM2H, 2,
53 , 2,
54 Offset (0x93), /* PAM3 */
55 PM3L, 2,
56 , 2,
57 PM3H, 2,
58 , 2,
59 Offset (0x94), /* PAM4 */
60 PM4L, 2,
61 , 2,
62 PM4H, 2,
63 , 2,
64 Offset (0x95), /* PAM5 */
65 PM5L, 2,
66 , 2,
67 PM5H, 2,
68 , 2,
69 Offset (0x96), /* PAM6 */
70 PM6L, 2,
71 , 2,
72 PM6H, 2,
73 , 2,
74
75 Offset (0xa0), /* Top of Memory */
Angel Pons4d962b22020-07-07 03:00:24 +0200[diff] [blame]76 TOM, 8,
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]77
78 Offset (0xb0), /* Top of Low Used Memory */
79 , 4,
80 TLUD, 12,
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]81 }
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]82}
83
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]84Name (MCRS, ResourceTemplate()
85{
86 /* Bus Numbers */
87 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
88 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
89
90 /* IO Region 0 */
91 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
92 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
93
94 /* PCI Config Space */
95 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
96
97 /* IO Region 1 */
98 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
99 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
100
101 /* VGA memory (0xa0000-0xbffff) */
102 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
103 Cacheable, ReadWrite,
104 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
105 0x00020000,,, ASEG)
106
107 /* OPROM reserved (0xc0000-0xc3fff) */
108 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
109 Cacheable, ReadWrite,
110 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
111 0x00004000,,, OPR0)
112
113 /* OPROM reserved (0xc4000-0xc7fff) */
114 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
115 Cacheable, ReadWrite,
116 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
117 0x00004000,,, OPR1)
118
119 /* OPROM reserved (0xc8000-0xcbfff) */
120 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
121 Cacheable, ReadWrite,
122 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
123 0x00004000,,, OPR2)
124
125 /* OPROM reserved (0xcc000-0xcffff) */
126 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
127 Cacheable, ReadWrite,
128 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
129 0x00004000,,, OPR3)
130
131 /* OPROM reserved (0xd0000-0xd3fff) */
132 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
133 Cacheable, ReadWrite,
134 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
135 0x00004000,,, OPR4)
136
137 /* OPROM reserved (0xd4000-0xd7fff) */
138 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
139 Cacheable, ReadWrite,
140 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
141 0x00004000,,, OPR5)
142
143 /* OPROM reserved (0xd8000-0xdbfff) */
144 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
145 Cacheable, ReadWrite,
146 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
147 0x00004000,,, OPR6)
148
149 /* OPROM reserved (0xdc000-0xdffff) */
150 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
151 Cacheable, ReadWrite,
152 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
153 0x00004000,,, OPR7)
154
155 /* BIOS Extension (0xe0000-0xe3fff) */
156 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
157 Cacheable, ReadWrite,
158 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
159 0x00004000,,, ESG0)
160
161 /* BIOS Extension (0xe4000-0xe7fff) */
162 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
163 Cacheable, ReadWrite,
164 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
165 0x00004000,,, ESG1)
166
167 /* BIOS Extension (0xe8000-0xebfff) */
168 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
169 Cacheable, ReadWrite,
170 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
171 0x00004000,,, ESG2)
172
173 /* BIOS Extension (0xec000-0xeffff) */
174 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
175 Cacheable, ReadWrite,
176 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
177 0x00004000,,, ESG3)
178
179 /* System BIOS (0xf0000-0xfffff) */
180 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
181 Cacheable, ReadWrite,
182 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
183 0x00010000,,, FSEG)
184
185 /* PCI Memory Region (Top of memory-0xfebfffff) */
186 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
187 Cacheable, ReadWrite,
188 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
189 IO_APIC_ADDR,,, PM01)
190
191 /* TPM Area (0xfed40000-0xfed44fff) */
192 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
193 Cacheable, ReadWrite,
194 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
195 0x00005000,,, TPMR)
196})
197
Angel Pons4d962b22020-07-07 03:00:24 +0200[diff] [blame]198/* Current Resource Settings */
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]199Method (_CRS, 0, Serialized)
200{
201 /* Find PCI resource area in MCRS */
202 CreateDwordField(MCRS, ^PM01._MIN, PMIN)
203 CreateDwordField(MCRS, ^PM01._MAX, PMAX)
204 CreateDwordField(MCRS, ^PM01._LEN, PLEN)
205
Angel Pons4d962b22020-07-07 03:00:24 +0200[diff] [blame]206 /*
207 * Fix up PCI memory region:
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]208 * Enter actual TOLUD. The TOLUD register contains bits 27-31 of
209 * the top of memory address.
210 */
Angel Ponsbfc80092020-07-07 03:03:43 +0200[diff] [blame]211 PMIN = ^MCHC.TLUD << 27
212 PLEN = PMAX - PMIN + 1
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]213
214 Return (MCRS)
215}