Alexandru Gagniuc | ffd4a61 | 2013-12-25 03:00:39 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * Allwinner A10 platform dram register definition. |
| 3 | * |
| 4 | * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c |
| 5 | * and earlier U-Boot Allwiner A10 SPL work |
| 6 | * |
| 7 | * Copyright (C) 2007-2012 Allwinner Technology Co., Ltd. |
| 8 | * Berg Xing <bergxing@allwinnertech.com> |
| 9 | * Tom Cubie <tangliang@allwinnertech.com> |
| 10 | * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 11 | * Subject to the GNU GPL v2, or (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #ifndef CPU_ALLWINNER_A10_DRAMC_H |
| 15 | #define CPU_ALLWINNER_A10_DRAMC_H |
| 16 | |
| 17 | #include <types.h> |
| 18 | |
| 19 | #define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) |
| 20 | #define DRAM_CCR_DQS_GATE (0x1 << 14) |
| 21 | #define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) |
| 22 | #define DRAM_CCR_ITM_OFF (0x1 << 28) |
| 23 | #define DRAM_CCR_DATA_TRAINING (0x1 << 30) |
| 24 | #define DRAM_CCR_INIT (0x1 << 31) |
| 25 | |
| 26 | #define DRAM_MEMORY_TYPE_DDR1 1 |
| 27 | #define DRAM_MEMORY_TYPE_DDR2 2 |
| 28 | #define DRAM_MEMORY_TYPE_DDR3 3 |
| 29 | #define DRAM_MEMORY_TYPE_LPDDR2 4 |
| 30 | #define DRAM_MEMORY_TYPE_LPDDR 5 |
| 31 | #define DRAM_DCR_TYPE (0x1 << 0) |
| 32 | #define DRAM_DCR_TYPE_DDR2 0x0 |
| 33 | #define DRAM_DCR_TYPE_DDR3 0x1 |
| 34 | #define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) |
| 35 | #define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) |
| 36 | #define DRAM_DCR_IO_WIDTH_8BIT 0x0 |
| 37 | #define DRAM_DCR_IO_WIDTH_16BIT 0x1 |
| 38 | #define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) |
| 39 | #define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) |
| 40 | #define DRAM_DCR_CHIP_DENSITY_256M 0x0 |
| 41 | #define DRAM_DCR_CHIP_DENSITY_512M 0x1 |
| 42 | #define DRAM_DCR_CHIP_DENSITY_1024M 0x2 |
| 43 | #define DRAM_DCR_CHIP_DENSITY_2048M 0x3 |
| 44 | #define DRAM_DCR_CHIP_DENSITY_4096M 0x4 |
| 45 | #define DRAM_DCR_CHIP_DENSITY_8192M 0x5 |
| 46 | #define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) |
| 47 | #define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) |
| 48 | #define DRAM_DCR_BUS_WIDTH_32BIT 0x3 |
| 49 | #define DRAM_DCR_BUS_WIDTH_16BIT 0x1 |
| 50 | #define DRAM_DCR_BUS_WIDTH_8BIT 0x0 |
| 51 | #define DRAM_DCR_NR_DLLCR_32BIT 5 |
| 52 | #define DRAM_DCR_NR_DLLCR_16BIT 3 |
| 53 | #define DRAM_DCR_NR_DLLCR_8BIT 2 |
| 54 | #define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) |
| 55 | #define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) |
| 56 | #define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) |
| 57 | #define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) |
| 58 | #define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) |
| 59 | #define DRAM_DCR_MODE_SEQ 0x0 |
| 60 | #define DRAM_DCR_MODE_INTERLEAVE 0x1 |
| 61 | |
| 62 | #define DRAM_CSR_FAILED (0x1 << 20) |
| 63 | |
| 64 | #define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) |
| 65 | #define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) |
| 66 | #define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) |
| 67 | #define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) |
| 68 | #define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) |
| 69 | #define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) |
| 70 | #define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) |
| 71 | #define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) |
| 72 | #define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) |
| 73 | #define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) |
| 74 | #define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) |
| 75 | #define DRAM_MCR_RESET (0x1 << 12) |
| 76 | #define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) |
| 77 | #define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) |
| 78 | #define DRAM_MCR_DCLK_OUT (0x1 << 16) |
| 79 | |
| 80 | #define DRAM_DLLCR_NRESET (0x1 << 30) |
| 81 | #define DRAM_DLLCR_DISABLE (0x1 << 31) |
| 82 | |
| 83 | #define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) |
| 84 | #define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) |
| 85 | |
| 86 | #define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) |
| 87 | #define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) |
| 88 | |
| 89 | #define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) |
| 90 | #define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) |
| 91 | #define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) |
| 92 | #define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) |
| 93 | #define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) |
| 94 | #define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) |
| 95 | #define DRAM_MR_POWER_DOWN (0x1 << 12) |
| 96 | |
| 97 | #define DRAM_CSEL_MAGIC 0x16237495 |
| 98 | |
| 99 | struct a1x_dramc { |
| 100 | u32 ccr; /* 0x00 controller configuration register */ |
| 101 | u32 dcr; /* 0x04 dram configuration register */ |
| 102 | u32 iocr; /* 0x08 i/o configuration register */ |
| 103 | u32 csr; /* 0x0c controller status register */ |
| 104 | u32 drr; /* 0x10 dram refresh register */ |
| 105 | u32 tpr0; /* 0x14 dram timing parameters register 0 */ |
| 106 | u32 tpr1; /* 0x18 dram timing parameters register 1 */ |
| 107 | u32 tpr2; /* 0x1c dram timing parameters register 2 */ |
| 108 | u32 gdllcr; /* 0x20 global dll control register */ |
| 109 | u8 res0[0x28]; |
| 110 | u32 rslr0; /* 0x4c rank system latency register */ |
| 111 | u32 rslr1; /* 0x50 rank system latency register */ |
| 112 | u8 res1[0x8]; |
| 113 | u32 rdgr0; /* 0x5c rank dqs gating register */ |
| 114 | u32 rdgr1; /* 0x60 rank dqs gating register */ |
| 115 | u8 res2[0x34]; |
| 116 | u32 odtcr; /* 0x98 odt configuration register */ |
| 117 | u32 dtr0; /* 0x9c data training register 0 */ |
| 118 | u32 dtr1; /* 0xa0 data training register 1 */ |
| 119 | u32 dtar; /* 0xa4 data training address register */ |
| 120 | u32 zqcr0; /* 0xa8 zq control register 0 */ |
| 121 | u32 zqcr1; /* 0xac zq control register 1 */ |
| 122 | u32 zqsr; /* 0xb0 zq status register */ |
| 123 | u32 idcr; /* 0xb4 initializaton delay configure reg */ |
| 124 | u8 res3[0x138]; |
| 125 | u32 mr; /* 0x1f0 mode register */ |
| 126 | u32 emr; /* 0x1f4 extended mode register */ |
| 127 | u32 emr2; /* 0x1f8 extended mode register */ |
| 128 | u32 emr3; /* 0x1fc extended mode register */ |
| 129 | u32 dllctr; /* 0x200 dll control register */ |
| 130 | u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ |
| 131 | /* 0x208 dll control register 1(byte 1) */ |
| 132 | /* 0x20c dll control register 2(byte 2) */ |
| 133 | /* 0x210 dll control register 3(byte 3) */ |
| 134 | /* 0x214 dll control register 4(byte 4) */ |
| 135 | u32 dqtr0; /* 0x218 dq timing register */ |
| 136 | u32 dqtr1; /* 0x21c dq timing register */ |
| 137 | u32 dqtr2; /* 0x220 dq timing register */ |
| 138 | u32 dqtr3; /* 0x224 dq timing register */ |
| 139 | u32 dqstr; /* 0x228 dqs timing register */ |
| 140 | u32 dqsbtr; /* 0x22c dqsb timing register */ |
| 141 | u32 mcr; /* 0x230 mode configure register */ |
| 142 | u8 res[0x8]; |
| 143 | u32 ppwrsctl; /* 0x23c pad power save control */ |
| 144 | u32 apr; /* 0x240 arbiter period register */ |
| 145 | u32 pldtr; /* 0x244 priority level data threshold reg */ |
| 146 | u8 res5[0x8]; |
| 147 | u32 hpcr[32]; /* 0x250 host port configure register */ |
| 148 | u8 res6[0x10]; |
| 149 | u32 csel; /* 0x2e0 controller select register */ |
| 150 | }; |
| 151 | |
| 152 | struct dram_para { |
| 153 | u32 clock; |
| 154 | u32 type; |
| 155 | u32 rank_num; |
| 156 | u32 density; |
| 157 | u32 io_width; |
| 158 | u32 bus_width; |
| 159 | u32 cas; |
| 160 | u32 zq; |
| 161 | u32 odt_en; |
| 162 | u32 size; |
| 163 | u32 tpr0; |
| 164 | u32 tpr1; |
| 165 | u32 tpr2; |
| 166 | u32 tpr3; |
| 167 | u32 tpr4; |
| 168 | u32 tpr5; |
| 169 | u32 emr1; |
| 170 | u32 emr2; |
| 171 | u32 emr3; |
| 172 | }; |
| 173 | |
| 174 | unsigned long dramc_init(struct dram_para *para); |
| 175 | |
| 176 | #endif /* CPU_ALLWINNER_A10_DRAMC_H */ |