Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 5 | * Copyright 2013 Google Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
Stefan Reinauer | 5605f1b | 2013-03-21 18:43:51 -0700 | [diff] [blame] | 23 | #include <device/pci_def.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 24 | #include "pch.h" |
| 25 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 26 | #ifdef __SIMPLE_DEVICE__ |
| 27 | static pci_devfn_t pch_get_lpc_device(void) |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 28 | { |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 29 | return PCI_DEV(0, 0x1f, 0); |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 30 | } |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 31 | #else |
| 32 | static struct device *pch_get_lpc_device(void) |
| 33 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 34 | return pcidev_on_root(0x1f, 0); |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 35 | } |
| 36 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | |
| 38 | int pch_silicon_revision(void) |
| 39 | { |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 40 | static int pch_revision_id = -1; |
| 41 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | if (pch_revision_id < 0) |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 43 | pch_revision_id = pci_read_config8(pch_get_lpc_device(), |
| 44 | PCI_REVISION_ID); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | return pch_revision_id; |
| 46 | } |
| 47 | |
Tristan Corrick | d3f01b2 | 2018-12-06 22:46:58 +1300 | [diff] [blame] | 48 | int pch_silicon_id(void) |
| 49 | { |
| 50 | static int pch_id = -1; |
| 51 | |
| 52 | if (pch_id < 0) |
| 53 | pch_id = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID); |
| 54 | |
| 55 | return pch_id; |
| 56 | } |
| 57 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | int pch_silicon_type(void) |
| 59 | { |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 60 | static int pch_type = -1; |
| 61 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | if (pch_type < 0) |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 63 | pch_type = pci_read_config8(pch_get_lpc_device(), |
| 64 | PCI_DEVICE_ID + 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | return pch_type; |
| 66 | } |
| 67 | |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 68 | int pch_is_lp(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 69 | { |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 70 | return pch_silicon_type() == PCH_TYPE_LPT_LP; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | } |
| 72 | |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 73 | u16 get_pmbase(void) |
| 74 | { |
| 75 | static u16 pmbase; |
| 76 | |
| 77 | if (!pmbase) |
| 78 | pmbase = pci_read_config16(pch_get_lpc_device(), |
| 79 | PMBASE) & 0xfffc; |
| 80 | return pmbase; |
| 81 | } |
| 82 | |
| 83 | u16 get_gpiobase(void) |
| 84 | { |
| 85 | static u16 gpiobase; |
| 86 | |
| 87 | if (!gpiobase) |
| 88 | gpiobase = pci_read_config16(pch_get_lpc_device(), |
| 89 | GPIOBASE) & 0xfffc; |
| 90 | return gpiobase; |
| 91 | } |
| 92 | |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 93 | #ifndef __SMM__ |
| 94 | |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 95 | /* Put device in D3Hot Power State */ |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 96 | static void pch_enable_d3hot(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 97 | { |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 98 | u32 reg32 = pci_read_config32(dev, PCH_PCS); |
| 99 | reg32 |= PCH_PCS_PS_D3HOT; |
| 100 | pci_write_config32(dev, PCH_PCS, reg32); |
| 101 | } |
| 102 | |
Frans Hendriks | e6bf51f | 2019-05-01 10:48:31 +0200 | [diff] [blame] | 103 | /* Set bit in function disable register to hide this device */ |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 104 | void pch_disable_devfn(struct device *dev) |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 105 | { |
| 106 | switch (dev->path.pci.devfn) { |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 107 | case PCI_DEVFN(19, 0): /* Audio DSP */ |
| 108 | RCBA32_OR(FD, PCH_DISABLE_ADSPD); |
| 109 | break; |
| 110 | case PCI_DEVFN(20, 0): /* XHCI */ |
| 111 | RCBA32_OR(FD, PCH_DISABLE_XHCI); |
| 112 | break; |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 113 | case PCI_DEVFN(21, 0): /* DMA */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 114 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 115 | pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 116 | break; |
| 117 | case PCI_DEVFN(21, 1): /* I2C0 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 118 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 119 | pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 120 | break; |
| 121 | case PCI_DEVFN(21, 2): /* I2C1 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 122 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 123 | pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 124 | break; |
| 125 | case PCI_DEVFN(21, 3): /* SPI0 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 126 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 127 | pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 128 | break; |
| 129 | case PCI_DEVFN(21, 4): /* SPI1 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 130 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 131 | pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 132 | break; |
| 133 | case PCI_DEVFN(21, 5): /* UART0 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 134 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 135 | pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 136 | break; |
| 137 | case PCI_DEVFN(21, 6): /* UART1 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 138 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 139 | pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 140 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 142 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 143 | break; |
| 144 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 145 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 146 | break; |
| 147 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 148 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 149 | break; |
| 150 | case PCI_DEVFN(22, 3): /* KT */ |
| 151 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 152 | break; |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 153 | case PCI_DEVFN(23, 0): /* SDIO */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 154 | pch_enable_d3hot(dev); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 155 | pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); |
| 156 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 157 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 158 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 159 | break; |
| 160 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 161 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 162 | break; |
| 163 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 164 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 165 | break; |
| 166 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 167 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 168 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 169 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 170 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 171 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 172 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 173 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 174 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 175 | break; |
| 176 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 177 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 178 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 179 | case PCI_DEVFN(31, 0): /* LPC */ |
| 180 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 181 | break; |
| 182 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 183 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 184 | break; |
| 185 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 186 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 187 | break; |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 188 | case PCI_DEVFN(31, 5): /* SATA #2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 190 | break; |
| 191 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 192 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 193 | break; |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | #define IOBP_RETRY 1000 |
| 198 | static inline int iobp_poll(void) |
| 199 | { |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame^] | 200 | unsigned int try; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 201 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 202 | for (try = IOBP_RETRY; try > 0; try--) { |
| 203 | u16 status = RCBA16(IOBPS); |
| 204 | if ((status & IOBPS_READY) == 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 205 | return 1; |
| 206 | udelay(10); |
| 207 | } |
| 208 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 209 | printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 210 | return 0; |
| 211 | } |
| 212 | |
Aaron Durbin | c17aac3 | 2013-06-19 13:12:48 -0500 | [diff] [blame] | 213 | u32 pch_iobp_read(u32 address) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 214 | { |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 215 | u16 status; |
| 216 | |
| 217 | if (!iobp_poll()) |
| 218 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 219 | |
| 220 | /* Set the address */ |
| 221 | RCBA32(IOBPIRI) = address; |
| 222 | |
| 223 | /* READ OPCODE */ |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 224 | status = RCBA16(IOBPS); |
| 225 | status &= ~IOBPS_MASK; |
| 226 | status |= IOBPS_READ; |
| 227 | RCBA16(IOBPS) = status; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 228 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 229 | /* Undocumented magic */ |
| 230 | RCBA16(IOBPU) = IOBPU_MAGIC; |
| 231 | |
| 232 | /* Set ready bit */ |
| 233 | status = RCBA16(IOBPS); |
| 234 | status |= IOBPS_READY; |
| 235 | RCBA16(IOBPS) = status; |
| 236 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 237 | if (!iobp_poll()) |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 238 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 239 | |
| 240 | /* Check for successful transaction */ |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 241 | status = RCBA16(IOBPS); |
| 242 | if (status & IOBPS_TX_MASK) { |
| 243 | printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); |
| 244 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 245 | } |
| 246 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 247 | /* Read IOBP data */ |
| 248 | return RCBA32(IOBPD); |
| 249 | } |
| 250 | |
Aaron Durbin | c17aac3 | 2013-06-19 13:12:48 -0500 | [diff] [blame] | 251 | void pch_iobp_write(u32 address, u32 data) |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 252 | { |
| 253 | u16 status; |
Aaron Durbin | c17aac3 | 2013-06-19 13:12:48 -0500 | [diff] [blame] | 254 | |
| 255 | if (!iobp_poll()) |
| 256 | return; |
| 257 | |
| 258 | /* Set the address */ |
| 259 | RCBA32(IOBPIRI) = address; |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 260 | |
| 261 | /* WRITE OPCODE */ |
| 262 | status = RCBA16(IOBPS); |
| 263 | status &= ~IOBPS_MASK; |
| 264 | status |= IOBPS_WRITE; |
| 265 | RCBA16(IOBPS) = status; |
| 266 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 267 | RCBA32(IOBPD) = data; |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 268 | |
| 269 | /* Undocumented magic */ |
| 270 | RCBA16(IOBPU) = IOBPU_MAGIC; |
| 271 | |
| 272 | /* Set ready bit */ |
| 273 | status = RCBA16(IOBPS); |
| 274 | status |= IOBPS_READY; |
| 275 | RCBA16(IOBPS) = status; |
| 276 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 277 | if (!iobp_poll()) |
| 278 | return; |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 279 | |
| 280 | /* Check for successful transaction */ |
| 281 | status = RCBA16(IOBPS); |
| 282 | if (status & IOBPS_TX_MASK) { |
| 283 | printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); |
| 284 | return; |
| 285 | } |
| 286 | |
| 287 | printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 288 | } |
| 289 | |
Aaron Durbin | c17aac3 | 2013-06-19 13:12:48 -0500 | [diff] [blame] | 290 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) |
| 291 | { |
| 292 | u32 data = pch_iobp_read(address); |
| 293 | |
| 294 | /* Update the data */ |
| 295 | data &= andvalue; |
| 296 | data |= orvalue; |
| 297 | |
| 298 | pch_iobp_write(address, data); |
| 299 | } |
| 300 | |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 301 | void pch_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 302 | { |
| 303 | u32 reg32; |
| 304 | |
Aaron Durbin | c0254e6 | 2013-06-20 01:20:30 -0500 | [diff] [blame] | 305 | /* PCH PCIe Root Ports are handled in PCIe driver. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 306 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) |
Aaron Durbin | c0254e6 | 2013-06-20 01:20:30 -0500 | [diff] [blame] | 307 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 308 | |
| 309 | if (!dev->enabled) { |
| 310 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 311 | |
| 312 | /* Ensure memory, io, and bus master are all disabled */ |
| 313 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 314 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 315 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 316 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 317 | |
Aaron Durbin | 3fcd356 | 2013-06-19 13:20:37 -0500 | [diff] [blame] | 318 | /* Disable this device if possible */ |
| 319 | pch_disable_devfn(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 320 | } else { |
| 321 | /* Enable SERR */ |
| 322 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 323 | reg32 |= PCI_COMMAND_SERR; |
| 324 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | struct chip_operations southbridge_intel_lynxpoint_ops = { |
| 329 | CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge") |
| 330 | .enable_dev = pch_enable, |
| 331 | }; |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 332 | |
| 333 | #endif /* __SMM__ */ |