Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <stdint.h> |
| 16 | #include <string.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 18 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 20 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 21 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 22 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 23 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Patrick Rudolph | da9302a | 2019-03-24 17:01:41 +0100 | [diff] [blame] | 24 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 25 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 26 | #include "ec/google/chromeec/ec.h" |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 27 | #include <cbfs.h> |
| 28 | |
| 29 | #include <southbridge/intel/bd82x6x/chip.h> |
| 30 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 31 | void mainboard_pch_lpc_setup(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 32 | { |
Nico Huber | e036aae | 2019-11-17 01:24:44 +0100 | [diff] [blame] | 33 | /* Enable additional 0x200..0x207 for EC */ |
| 34 | pci_or_config16(PCH_LPC_DEV, LPC_EN, GAMEL_LPC_EN); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 35 | } |
| 36 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 37 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 38 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 39 | /* |
| 40 | * GFX INTA -> PIRQA (MSI) |
| 41 | * D28IP_P3IP WLAN INTA -> PIRQB |
| 42 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 43 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 44 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 45 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 46 | * D31IP_TTIP THRT INTC -> PIRQA |
| 47 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 48 | * |
| 49 | * TRACKPAD -> PIRQE (Edge Triggered) |
| 50 | * TOUCHSCREEN -> PIRQG (Edge Triggered) |
| 51 | */ |
| 52 | |
| 53 | /* Device interrupt pin register (board specific) */ |
| 54 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 55 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 56 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 57 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 58 | RCBA32(D28IP) = (INTA << D28IP_P3IP); |
| 59 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 60 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 61 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 62 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 63 | |
| 64 | /* Device interrupt route registers */ |
| 65 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 66 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 67 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 68 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 69 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 70 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 71 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 72 | } |
| 73 | |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 74 | static uint8_t *locate_spd(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 75 | { |
| 76 | const int gpio_vector[] = {41, 42, 43, 10, -1}; |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 77 | uint8_t *spd_file; |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 78 | size_t spd_file_len; |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 79 | int spd_index = get_gpios(gpio_vector); |
| 80 | |
| 81 | printk(BIOS_DEBUG, "spd index %d\n", spd_index); |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 82 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 83 | &spd_file_len); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 84 | if (!spd_file) |
| 85 | die("SPD data not found."); |
| 86 | |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 87 | if (spd_file_len < ((spd_index + 1) * 256)) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 88 | printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); |
| 89 | spd_index = 0; |
| 90 | } |
| 91 | |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 92 | if (spd_file_len < 256) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 93 | die("Missing SPD data."); |
| 94 | |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 95 | return spd_file + spd_index * 256; |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 96 | } |
| 97 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 98 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 99 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 100 | struct pei_data pei_data_template = { |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 101 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 102 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 103 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 104 | .epbar = DEFAULT_EPBAR, |
| 105 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 106 | .smbusbar = SMBUS_IO_BASE, |
| 107 | .wdbbar = 0x4000000, |
| 108 | .wdbsize = 0x1000, |
| 109 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 110 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 111 | .pmbase = DEFAULT_PMBASE, |
| 112 | .gpiobase = DEFAULT_GPIOBASE, |
| 113 | .thermalbase = 0xfed08000, |
| 114 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 115 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 116 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 117 | .ec_present = 1, |
| 118 | .ddr3lv_support = 1, |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 119 | // 0 = leave channel enabled |
| 120 | // 1 = disable dimm 0 on channel |
| 121 | // 2 = disable dimm 1 on channel |
| 122 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 123 | .dimm_channel0_disabled = 2, |
| 124 | .dimm_channel1_disabled = 2, |
| 125 | .max_ddr3_freq = 1600, |
| 126 | .usb_port_config = { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 127 | /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ |
| 128 | { 0, 3, 0x0000 }, /* P0: Empty */ |
| 129 | { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ |
| 130 | { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ |
| 131 | { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ |
| 132 | { 0, 3, 0x0000 }, /* P4: Empty */ |
| 133 | { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ |
| 134 | { 0, 3, 0x0000 }, /* P6: Empty */ |
| 135 | { 0, 3, 0x0000 }, /* P7: Empty */ |
| 136 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 137 | { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ |
| 138 | { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ |
| 139 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 140 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 141 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 142 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 143 | }, |
| 144 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 145 | *pei_data = pei_data_template; |
Matt DeVillier | 4af1fe2 | 2019-08-24 23:54:41 -0500 | [diff] [blame] | 146 | /* LINK has 2 channels of memory down, so spd_data[0] and [2] |
| 147 | both need to be populated */ |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 148 | memcpy(pei_data->spd_data[0], locate_spd(), |
| 149 | sizeof(pei_data->spd_data[0])); |
Matt DeVillier | 4af1fe2 | 2019-08-24 23:54:41 -0500 | [diff] [blame] | 150 | memcpy(pei_data->spd_data[2], pei_data->spd_data[0], |
| 151 | sizeof(pei_data->spd_data[0])); |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 155 | /* enabled power USB oc pin */ |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 156 | { 0, 0, -1 }, /* P0: Empty */ |
| 157 | { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ |
| 158 | { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ |
| 159 | { 1, 0, -1 }, /* P3: SDCARD (no OC) */ |
| 160 | { 0, 0, -1 }, /* P4: Empty */ |
| 161 | { 1, 0, -1 }, /* P5: WWAN (no OC) */ |
| 162 | { 0, 0, -1 }, /* P6: Empty */ |
| 163 | { 0, 0, -1 }, /* P7: Empty */ |
| 164 | { 1, 0, -1 }, /* P8: Camera (no OC) */ |
| 165 | { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ |
| 166 | { 0, 0, -1 }, /* P10: Empty */ |
| 167 | { 0, 0, -1 }, /* P11: Empty */ |
| 168 | { 0, 0, -1 }, /* P12: Empty */ |
| 169 | { 0, 0, -1 }, /* P13: Empty */ |
| 170 | }; |
| 171 | |
Peter Lemenkov | 498f1cc | 2019-02-07 10:48:10 +0100 | [diff] [blame] | 172 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 173 | { |
Matt DeVillier | 4af1fe2 | 2019-08-24 23:54:41 -0500 | [diff] [blame] | 174 | /* LINK has 2 channels of memory down, so spd_data[0] and [2] |
| 175 | both need to be populated */ |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 176 | memcpy(&spd[0], locate_spd(), 128); |
Matt DeVillier | 4af1fe2 | 2019-08-24 23:54:41 -0500 | [diff] [blame] | 177 | memcpy(&spd[2], &spd[0], 128); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 178 | } |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 179 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 180 | void mainboard_early_init(int s3resume) |
| 181 | { |
| 182 | if (!s3resume) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 183 | /* This is the fastest way to let users know |
| 184 | * the Intel CPU is now alive. |
| 185 | */ |
| 186 | google_chromeec_kbbacklight(100); |
| 187 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 188 | } |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 189 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 190 | int mainboard_should_reset_usb(int s3resume) |
| 191 | { |
| 192 | return !s3resume; |
| 193 | } |