Kerry She | 6401fdb | 2011-05-07 09:15:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <boot/tables.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <cpu/amd/mtrr.h> |
| 27 | #include <device/pci_def.h> |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame^] | 28 | #include "SBPLATFORM.h" |
Kerry She | 6401fdb | 2011-05-07 09:15:02 +0000 | [diff] [blame] | 29 | #include "chip.h" |
| 30 | |
| 31 | uint64_t uma_memory_base, uma_memory_size; |
| 32 | |
| 33 | u8 is_dev3_present(void); |
| 34 | void set_pcie_dereset(void); |
| 35 | void set_pcie_reset(void); |
| 36 | void enable_int_gfx(void); |
| 37 | |
| 38 | /* GPIO6. */ |
| 39 | void enable_int_gfx(void) |
| 40 | { |
Kerry She | 6401fdb | 2011-05-07 09:15:02 +0000 | [diff] [blame] | 41 | volatile u8 *gpio_reg; |
| 42 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame^] | 43 | #ifdef UNUSED_CODE |
| 44 | RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */ |
| 45 | RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */ |
| 46 | #endif |
| 47 | /* make sure the Acpi MMIO(fed80000) is accessible */ |
| 48 | RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); |
Kerry She | 6401fdb | 2011-05-07 09:15:02 +0000 | [diff] [blame] | 49 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame^] | 50 | gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */ |
Kerry She | 6401fdb | 2011-05-07 09:15:02 +0000 | [diff] [blame] | 51 | |
| 52 | *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */ |
| 53 | *(gpio_reg + 170) = 0x1; /* gpio_gate */ |
| 54 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame^] | 55 | gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */ |
Kerry She | 6401fdb | 2011-05-07 09:15:02 +0000 | [diff] [blame] | 56 | |
| 57 | *(gpio_reg + 0x6) = 0x8; |
| 58 | *(gpio_reg + 170) = 0x0; |
| 59 | } |
| 60 | |
| 61 | void set_pcie_dereset() |
| 62 | { |
| 63 | } |
| 64 | |
| 65 | void set_pcie_reset(void) |
| 66 | { |
| 67 | } |
| 68 | |
| 69 | u8 is_dev3_present(void) |
| 70 | { |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | |
| 75 | /************************************************* |
| 76 | * enable the dedicated function in A785E-I board. |
| 77 | * This function called early than rs780_enable. |
| 78 | *************************************************/ |
| 79 | static void a785e_i_enable(device_t dev) |
| 80 | { |
| 81 | /* Leave it for furture use. */ |
| 82 | /* struct mainboard_config *mainboard = |
| 83 | (struct mainboard_config *)dev->chip_info; */ |
| 84 | |
| 85 | printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); |
| 86 | |
| 87 | #if (CONFIG_GFXUMA == 1) |
| 88 | msr_t msr, msr2; |
| 89 | |
| 90 | /* TOP_MEM: the top of DRAM below 4G */ |
| 91 | msr = rdmsr(TOP_MEM); |
| 92 | printk |
| 93 | (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 94 | __func__, msr.lo, msr.hi); |
| 95 | |
| 96 | /* TOP_MEM2: the top of DRAM above 4G */ |
| 97 | msr2 = rdmsr(TOP_MEM2); |
| 98 | printk |
| 99 | (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", |
| 100 | __func__, msr2.lo, msr2.hi); |
| 101 | |
| 102 | /* refer to UMA Size Consideration in 780 BDG. */ |
| 103 | switch (msr.lo) { |
| 104 | case 0x10000000: /* 256M system memory */ |
| 105 | uma_memory_size = 0x4000000; /* 64M recommended UMA */ |
| 106 | break; |
| 107 | |
| 108 | case 0x20000000: /* 512M system memory */ |
| 109 | uma_memory_size = 0x8000000; /* 128M recommended UMA */ |
| 110 | break; |
| 111 | |
| 112 | default: /* 1GB and above system memory */ |
| 113 | uma_memory_size = 0x10000000; /* 256M recommended UMA */ |
| 114 | break; |
| 115 | } |
| 116 | |
| 117 | uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ |
| 118 | printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", |
| 119 | __func__, uma_memory_size, uma_memory_base); |
| 120 | |
| 121 | /* TODO: TOP_MEM2 */ |
| 122 | #else |
| 123 | uma_memory_size = 0x8000000; /* 128M recommended UMA */ |
| 124 | uma_memory_base = 0x38000000; /* 1GB system memory supposed */ |
| 125 | #endif |
| 126 | |
| 127 | set_pcie_dereset(); |
| 128 | enable_int_gfx(); |
| 129 | } |
| 130 | |
| 131 | int add_mainboard_resources(struct lb_memory *mem) |
| 132 | { |
| 133 | /* UMA is removed from system memory in the northbridge code, but |
| 134 | * in some circumstances we want the memory mentioned as reserved. |
| 135 | */ |
| 136 | #if (CONFIG_GFXUMA == 1) |
| 137 | printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", |
| 138 | uma_memory_base, uma_memory_size); |
| 139 | lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, |
| 140 | uma_memory_size); |
| 141 | #endif |
| 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | struct chip_operations mainboard_ops = { |
| 146 | CHIP_NAME("ADVANSUS A785E-I Mainboard") |
| 147 | .enable_dev = a785e_i_enable, |
| 148 | }; |