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review.coreboot.org / coreboot / fea6bd16909a29854539c431497ccc460f3cdf7a / . / src / mainboard / lenovo / x60 / dock.c
blob: b64d864f4997116f303f358754c6b34fed2c9788 [file] [log] [blame]
Sven Schnellefea6bd12011-04-01 07:28:56 +0000[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
22#include <console/console.h>
23#include <device/device.h>
24#include <arch/io.h>
25#include <boot/tables.h>
26#include <delay.h>
27#include <arch/io.h>
28#include "dock.h"
29#include "southbridge/intel/i82801gx/i82801gx.h"
30#include "superio/nsc/pc87392/pc87392.h"
31
32static void dlpc_write_register(int reg, int value)
33{
34 outb(reg, 0x164e);
35 outb(value, 0x164f);
36}
37
38static u8 dlpc_read_register(int reg)
39{
40 outb(reg, 0x164e);
41 return inb(0x164f);
42}
43
44static void dock_write_register(int reg, int value)
45{
46 outb(reg, 0x2e);
47 outb(value, 0x2f);
48}
49
50static u8 dock_read_register(int reg)
51{
52 outb(reg, 0x2e);
53 return inb(0x2f);
54}
55
56static void dlpc_gpio_set_mode(int port, int mode)
57{
58 dlpc_write_register(0xf0, port);
59 dlpc_write_register(0xf1, mode);
60}
61
62static void dock_gpio_set_mode(int port, int mode, int irq)
63{
64 dock_write_register(0xf0, port);
65 dock_write_register(0xf1, mode);
66 dock_write_register(0xf2, irq);
67}
68
69static void dlpc_gpio_init(void)
70{
71 /* Select GPIO module */
72 dlpc_write_register(0x07, 0x07);
73 /* GPIO Base Address 0x1680 */
74 dlpc_write_register(0x60, 0x16);
75 dlpc_write_register(0x61, 0x80);
76
77 /* Activate GPIO */
78 dlpc_write_register(0x30, 0x01);
79
80 dlpc_gpio_set_mode(0x00, 3);
81 dlpc_gpio_set_mode(0x01, 3);
82 dlpc_gpio_set_mode(0x02, 0);
83 dlpc_gpio_set_mode(0x03, 3);
84 dlpc_gpio_set_mode(0x04, 4);
85 dlpc_gpio_set_mode(0x20, 4);
86 dlpc_gpio_set_mode(0x21, 4);
87 dlpc_gpio_set_mode(0x23, 4);
88}
89
90int dlpc_init(void)
91{
92 int timeout = 1000;
93
94 /* Enable 14.318MHz CLK on CLKIN */
95 dlpc_write_register(0x29, 0xa0);
96 while(!(dlpc_read_register(0x29) & 0x10) && timeout--)
97 udelay(1000);
98
99 if (!timeout)
100 return 1;
101
102 /* Select DLPC module */
103 dlpc_write_register(0x07, 0x19);
104 /* DLPC Base Address 0x164c */
105 dlpc_write_register(0x60, 0x16);
106 dlpc_write_register(0x61, 0x4c);
107 /* Activate DLPC */
108 dlpc_write_register(0x30, 0x01);
109
110 outb(0x07, 0x164c);
111
112 timeout = 1000;
113
114 while(!(inb(0x164c) & 8) && timeout--)
115 udelay(1000);
116
117 if (!timeout) {
118 /* docking failed, disable DLPC switch */
119 outb(0x00, 0x164c);
120 dlpc_write_register(0x30, 0x00);
121 return 1;
122 }
123
124 dlpc_gpio_init();
125
126 return 0;
127}
128
129int dock_connect(void)
130{
131 int timeout = 1000;
132
133 /* Assert D_PLTRST# */
134 outb(0xfe, 0x1680);
135 udelay(1000);
136 /* Deassert D_PLTRST# */
137 outb(0xff, 0x1680);
138
139 /* startup 14.318MHz Clock */
140 dock_write_register(0x29, 0x06);
141 /* wait until clock is settled */
142 while(!(dock_read_register(0x29) & 0x08) && timeout--)
143 udelay(1000);
144
145 if (!timeout)
146 return 1;
147
148 /* Pin 6: CLKRUN
149 * Pin 72: #DR1
150 * Pin 19: #SMI
151 * Pin 73: #MTR
152 */
153 dock_write_register(0x24, 0x37);
154
155 /* PNF active HIGH */
156 dock_write_register(0x25, 0xa0);
157
158 /* disable FDC */
159 dock_write_register(0x26, 0x01);
160
161 /* Enable GPIO IRQ to #SMI */
162 dock_write_register(0x28, 0x02);
163
164 /* select GPIO */
165 dock_write_register(0x07, 0x07);
166
167 /* set base address */
168 dock_write_register(0x60, 0x16);
169 dock_write_register(0x61, 0x20);
170
171 /* init GPIO pins */
172 dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE |
173 PC87392_GPIO_PIN_PULLUP, 0x00);
174
175 dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE |
176 PC87392_GPIO_PIN_PULLUP,
177 PC87392_GPIO_PIN_TRIGGERS_SMI);
178
179 dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00);
180 dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00);
181 dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00);
182 dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00);
183 dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00);
184 dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02);
185
186 dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE |
187 PC87392_GPIO_PIN_PULLUP,
188 PC87392_GPIO_PIN_TRIGGERS_SMI);
189
190 dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00);
191 dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00);
192 dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00);
193 dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00);
194 dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00);
195 dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP |
196 PC87392_GPIO_PIN_OE , 0x00);
197
198 dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00);
199
200 dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
201 PC87392_GPIO_PIN_OE, 0x00);
202
203 dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
204 PC87392_GPIO_PIN_OE, 0x00);
205
206 dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00);
207 dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00);
208 dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00);
209 dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00);
210 dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00);
211 dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00);
212
213 dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00);
214 dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00);
215 dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00);
216 dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00);
217 dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00);
218
219 dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP |
220 PC87392_GPIO_PIN_OE, 0x00);
221
222 dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00);
223 dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00);
224
225 /* enable GPIO */
226 dock_write_register(0x30, 0x01);
227
228 outb(0x00, 0x1628);
229 outb(0x00, 0x1623);
230 outb(0x82, 0x1622);
231 outb(0xff, 0x1624);
232
233 /* Enable USB and Ultrabay power */
234 outb(0x03, 0x1628);
235 return 0;
236}
237
238void dock_disconnect(void)
239{
240 /* disconnect LPC bus */
241 outb(0x00, 0x164c);
242 /* Assert PLTRST and DLPCPD */
243 outb(0xfc, 0x1680);
244}
245
246int dock_present(void)
247{
248 return !((inb(DEFAULT_GPIOBASE + 0x0c) >> 13) & 1);
249}