Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Duncan Laurie | 7fab00c | 2013-05-22 09:51:11 -0700 | [diff] [blame] | 3 | // XHCI Controller 0:14.0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | |
Duncan Laurie | 7fab00c | 2013-05-22 09:51:11 -0700 | [diff] [blame] | 5 | Device (XHCI) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | { |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 7 | Name (_ADR, 0x00140000) |
| 8 | |
| 9 | Name (PLSD, 5) // Port Link State - RxDetect |
| 10 | Name (PLSP, 7) // Port Link State - Polling |
| 11 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 12 | OperationRegion (XPRT, PCI_Config, 0, 0x100) |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 13 | Field (XPRT, AnyAcc, NoLock, Preserve) |
| 14 | { |
| 15 | Offset (0x0), |
| 16 | DVID, 16, |
| 17 | Offset (0x10), |
| 18 | , 16, |
| 19 | XMEM, 16, // MEM_BASE |
| 20 | Offset (0x74), |
| 21 | D0D3, 2, |
| 22 | , 6, |
| 23 | PMEE, 1, // PME_EN |
| 24 | , 6, |
| 25 | PMES, 1, // PME_STS |
| 26 | Offset (0xb0), |
| 27 | , 13, |
| 28 | MB13, 1, |
| 29 | MB14, 1, |
| 30 | Offset (0xd0), |
| 31 | PR2R, 32, // USB2PR |
| 32 | PR2M, 32, // USB2PRM |
| 33 | PR3R, 32, // USB3PR |
| 34 | PR3M, 32, // USB3PRM |
| 35 | } |
| 36 | |
| 37 | // Clear status bits |
| 38 | Method (LPCL, 0, Serialized) |
| 39 | { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 40 | OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 41 | Field (XREG, DWordAcc, Lock, Preserve) |
| 42 | { |
| 43 | Offset (0x510), // PORTSCNUSB3[0] |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 44 | PSC0, 32, |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 45 | Offset (0x520), // PORTSCNUSB3[1] |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 46 | PSC1, 32, |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 47 | Offset (0x530), // PORTSCNUSB3[2] |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 48 | PSC2, 32, |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 49 | Offset (0x540), // PORTSCNUSB3[3] |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 50 | PSC3, 32, |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 51 | } |
| 52 | |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 53 | // Port Enabled/Disabled (Bit 1) |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 54 | Name (PEDB, 1 << 1) |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 55 | |
| 56 | // Change Status (Bits 23:17) |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 57 | Name (CHST, 0x7f << 17) |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 58 | |
| 59 | // Port 0 |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 60 | Local0 = PSC0 & ~PEDB |
| 61 | PSC0 = Local0 | CHST |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 62 | |
| 63 | // Port 1 |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 64 | Local0 = PSC1 & ~PEDB |
| 65 | PSC1 = Local0 | CHST |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 66 | |
| 67 | // Port 2 |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 68 | Local0 = PSC2 & ~PEDB |
| 69 | PSC2 = Local0 | CHST |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 70 | |
| 71 | // Port 3 |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 72 | Local0 = PSC3 & ~PEDB |
| 73 | PSC3 = Local0 | CHST |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | Method (LPS0, 0, Serialized) |
| 77 | { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 78 | OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 79 | Field (XREG, DWordAcc, Lock, Preserve) |
| 80 | { |
| 81 | Offset (0x510), // PORTSCNUSB3 |
| 82 | , 5, |
| 83 | PLS1, 4, // [8:5] Port Link State |
| 84 | PPR1, 1, // [9] Port Power |
| 85 | , 7, |
| 86 | CSC1, 1, // [17] Connect Status Change |
| 87 | , 1, |
| 88 | WRC1, 1, // [19] Warm Port Reset Change |
| 89 | , 11, |
| 90 | WPR1, 1, // [31] Warm Port Reset |
| 91 | Offset (0x520), // PORTSCNUSB3 |
| 92 | , 5, |
| 93 | PLS2, 4, // [8:5] Port Link State |
| 94 | PPR2, 1, // [9] Port Power |
| 95 | , 7, |
| 96 | CSC2, 1, // [17] Connect Status Change |
| 97 | , 1, |
| 98 | WRC2, 1, // [19] Warm Port Reset Change |
| 99 | , 11, |
| 100 | WPR2, 1, // [31] Warm Port Reset |
| 101 | Offset (0x530), // PORTSCNUSB3 |
| 102 | , 5, |
| 103 | PLS3, 4, // [8:5] Port Link State |
| 104 | PPR3, 1, // [9] Port Power |
| 105 | , 7, |
| 106 | CSC3, 1, // [17] Connect Status Change |
| 107 | , 1, |
| 108 | WRC3, 1, // [19] Warm Port Reset Change |
| 109 | , 11, |
| 110 | WPR3, 1, // [31] Warm Port Reset |
| 111 | Offset (0x540), // PORTSCNUSB3 |
| 112 | , 5, |
| 113 | PLS4, 4, // [8:5] Port Link State |
| 114 | PPR4, 1, // [9] Port Power |
| 115 | , 7, |
| 116 | CSC4, 1, // [17] Connect Status Change |
| 117 | , 1, |
| 118 | WRC4, 1, // [19] Warm Port Reset Change |
| 119 | , 11, |
| 120 | WPR4, 1, // [31] Warm Port Reset |
| 121 | } |
| 122 | |
| 123 | // Wait for all powered ports to finish polling |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 124 | Local0 = 10 |
| 125 | While ((PPR1 == 1 && PLS1 == PLSP || PPR2 == 1 && PLS2 == PLSP) || |
| 126 | (PPR3 == 1 && PLS3 == PLSP || PPR4 == 1 && PLS4 == PLSP)) |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 127 | { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 128 | If (Local0 == 0) { |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 129 | Break |
| 130 | } |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 131 | Local0-- |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 132 | Stall (10) |
| 133 | } |
| 134 | |
| 135 | // For each USB3 Port: |
| 136 | // If port is disconnected (PLS=5 PP=1 CSC=0) |
| 137 | // 1) Issue warm reset (WPR=1) |
| 138 | // 2) Poll for warm reset complete (WRC=0) |
| 139 | // 3) Write 1 to port status to clear |
| 140 | |
| 141 | // Local# indicate if port is reset |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 142 | Local1 = 0 |
| 143 | Local2 = 0 |
| 144 | Local3 = 0 |
| 145 | Local4 = 0 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 146 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 147 | If (PLS1 == PLSD && (CSC1 == 0 && PPR1 == 1)) { |
| 148 | WPR1 = 1 // Issue warm reset |
| 149 | Local1 = 1 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 150 | } |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 151 | If (PLS2 == PLSD && (CSC2 == 0 && PPR2 == 1)) { |
| 152 | WPR2 = 1 // Issue warm reset |
| 153 | Local2 = 1 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 154 | } |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 155 | If (PLS3 == PLSD && (CSC3 == 0 && PPR3 == 1)) { |
| 156 | WPR3 = 1 // Issue warm reset |
| 157 | Local3 = 1 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 158 | } |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 159 | If (PLS4 == PLSD && (CSC4 == 0 && PPR4 == 1)) { |
| 160 | WPR4 = 1 // Issue warm reset |
| 161 | Local4 = 1 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | // Poll for warm reset complete on all ports that were reset |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 165 | Local0 = 10 |
| 166 | While ((Local1 == 1 && WRC1 == 0 || Local2 == 1 && WRC2 == 0) || |
| 167 | (Local3 == 1 && WRC3 == 0 || Local4 == 1 && WRC4 == 0)) |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 168 | { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 169 | If (Local0 == 0) { |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 170 | Break |
| 171 | } |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 172 | Local0-- |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 173 | Stall (10) |
| 174 | } |
| 175 | |
| 176 | // Clear status bits in all ports |
| 177 | LPCL () |
| 178 | } |
| 179 | |
Duncan Laurie | 568ce5c | 2013-07-30 16:15:14 -0700 | [diff] [blame] | 180 | Method (_PSC, 0, NotSerialized) |
| 181 | { |
| 182 | Return (^D0D3) |
| 183 | } |
| 184 | |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 185 | Method (_PS0, 0, Serialized) |
| 186 | { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 187 | If (^DVID == 0xFFFF) { |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 188 | Return () |
| 189 | } |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 190 | If (^XMEM == 0xFFFF || ^XMEM == 0) { |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 191 | Return () |
| 192 | } |
| 193 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 194 | OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 195 | Field (XREG, DWordAcc, Lock, Preserve) |
| 196 | { |
| 197 | Offset (0x0e0), // AUX Reset Control 1 |
| 198 | , 15, |
| 199 | AX15, 1, |
| 200 | Offset (0x154), // AUX Domain PM Control Register 2 |
| 201 | , 31, |
| 202 | CLK2, 1, |
| 203 | Offset (0x16c), // AUX Clock Control |
| 204 | , 2, |
| 205 | CLK0, 1, |
| 206 | , 11, |
| 207 | CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable |
| 208 | } |
| 209 | |
| 210 | // If device is in D3, set back to D0 |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 211 | Local0 = ^D0D3 |
| 212 | if (Local0 == 3) { |
| 213 | ^D0D3 = 0 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 214 | } |
| 215 | |
Angel Pons | fe91192 | 2020-10-25 23:08:04 +0100 | [diff] [blame^] | 216 | #if CONFIG(INTEL_LYNXPOINT_LP) |
| 217 | // Clear PCI 0xB0[14:13] |
| 218 | ^MB13 = 0 |
| 219 | ^MB14 = 0 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 220 | |
Angel Pons | fe91192 | 2020-10-25 23:08:04 +0100 | [diff] [blame^] | 221 | // Clear MMIO 0x816C[14,2] |
| 222 | CLK0 = 0 |
| 223 | CLK1 = 0 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 224 | |
| 225 | // Set MMIO 0x8154[31] |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 226 | CLK2 = 1 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 227 | |
Angel Pons | fe91192 | 2020-10-25 23:08:04 +0100 | [diff] [blame^] | 228 | // Handle per-port reset if needed |
| 229 | LPS0 () |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 230 | |
Angel Pons | fe91192 | 2020-10-25 23:08:04 +0100 | [diff] [blame^] | 231 | // Set MMIO 0x80e0[15] |
| 232 | AX15 = 1 |
| 233 | #else |
| 234 | // Set MMIO 0x8154[31] |
| 235 | CLK2 = 1 |
| 236 | #endif |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 237 | |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 238 | Return () |
| 239 | } |
| 240 | |
| 241 | Method (_PS3, 0, Serialized) |
| 242 | { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 243 | If (^DVID == 0xFFFF) { |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 244 | Return () |
| 245 | } |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 246 | If (^XMEM == 0xFFFF || ^XMEM == 0) { |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 247 | Return () |
| 248 | } |
| 249 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 250 | OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 251 | Field (XREG, DWordAcc, Lock, Preserve) |
| 252 | { |
| 253 | Offset (0x0e0), // AUX Reset Control 1 |
| 254 | , 15, |
| 255 | AX15, 1, |
| 256 | Offset (0x154), // AUX Domain PM Control Register 2 |
| 257 | , 31, |
| 258 | CLK2, 1, |
| 259 | Offset (0x16c), // AUX Clock Control |
| 260 | , 2, |
| 261 | CLK0, 1, |
| 262 | , 11, |
| 263 | CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable |
| 264 | } |
| 265 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 266 | ^PMES = 1 // Clear PME Status |
| 267 | ^PMEE = 1 // Enable PME |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 268 | |
| 269 | // If device is in D3, set back to D0 |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 270 | Local0 = ^D0D3 |
| 271 | if (Local0 == 3) { |
| 272 | ^D0D3 = 0 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 273 | } |
| 274 | |
Angel Pons | fe91192 | 2020-10-25 23:08:04 +0100 | [diff] [blame^] | 275 | #if CONFIG(INTEL_LYNXPOINT_LP) |
| 276 | // Set PCI 0xB0[14:13] |
| 277 | ^MB13 = 1 |
| 278 | ^MB14 = 1 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 279 | |
Angel Pons | fe91192 | 2020-10-25 23:08:04 +0100 | [diff] [blame^] | 280 | // Set MMIO 0x816C[14,2] |
| 281 | CLK0 = 1 |
| 282 | CLK1 = 1 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 283 | |
| 284 | // Clear MMIO 0x8154[31] |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 285 | CLK2 = 0 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 286 | |
Angel Pons | fe91192 | 2020-10-25 23:08:04 +0100 | [diff] [blame^] | 287 | // Clear MMIO 0x80e0[15] |
| 288 | AX15 = 0 |
| 289 | #else |
| 290 | // Clear MMIO 0x8154[31] |
| 291 | CLK2 = 0 |
| 292 | #endif |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 293 | |
| 294 | // Put device in D3 |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 295 | ^D0D3 = 3 |
Duncan Laurie | 80fd5c4 | 2013-07-19 08:41:38 -0700 | [diff] [blame] | 296 | |
| 297 | Return () |
| 298 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 299 | |
Angel Pons | 59ea8ef | 2020-10-25 21:28:09 +0100 | [diff] [blame] | 300 | Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 301 | |
| 302 | // Leave USB ports on for to allow Wake from USB |
| 303 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 304 | Method (_S3D, 0) // Highest D State in S3 State |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 305 | { |
Duncan Laurie | 568ce5c | 2013-07-30 16:15:14 -0700 | [diff] [blame] | 306 | Return (3) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 307 | } |
| 308 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 309 | Method (_S4D, 0) // Highest D State in S4 State |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 310 | { |
Duncan Laurie | 568ce5c | 2013-07-30 16:15:14 -0700 | [diff] [blame] | 311 | Return (3) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 312 | } |
| 313 | |
| 314 | Device (HUB7) |
| 315 | { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 316 | Name (_ADR, 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 317 | |
Matt DeVillier | 8b96fd2 | 2017-04-17 18:25:09 -0500 | [diff] [blame] | 318 | // GPLD: Generate Port Location Data (PLD) |
| 319 | Method (GPLD, 1, Serialized) { |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 320 | Name (PCKG, Package () { |
Matt DeVillier | 8b96fd2 | 2017-04-17 18:25:09 -0500 | [diff] [blame] | 321 | Buffer (0x10) {} |
| 322 | }) |
| 323 | |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 324 | // REV: Revision 2 for ACPI 5.0 |
| 325 | CreateField (DerefOf (PCKG [0]), 0, 7, REV) |
| 326 | REV = 2 |
Matt DeVillier | 8b96fd2 | 2017-04-17 18:25:09 -0500 | [diff] [blame] | 327 | |
| 328 | // VISI: Port visibility to user per port |
Angel Pons | e53dfe0 | 2020-10-25 20:53:29 +0100 | [diff] [blame] | 329 | CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) |
| 330 | VISI = Arg0 |
Matt DeVillier | 8b96fd2 | 2017-04-17 18:25:09 -0500 | [diff] [blame] | 331 | Return (PCKG) |
| 332 | } |
| 333 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 334 | Device (PRT1) { Name (_ADR, 1) } // USB Port 0 |
| 335 | Device (PRT2) { Name (_ADR, 2) } // USB Port 1 |
| 336 | Device (PRT3) { Name (_ADR, 3) } // USB Port 2 |
| 337 | Device (PRT4) { Name (_ADR, 4) } // USB Port 3 |
| 338 | Device (PRT5) { Name (_ADR, 5) } // USB Port 4 |
| 339 | Device (PRT6) { Name (_ADR, 6) } // USB Port 5 |
Matt DeVillier | a672d15 | 2017-04-17 18:26:58 -0500 | [diff] [blame] | 340 | Device (PRT7) { Name (_ADR, 7) } // USB Port 6 |
| 341 | Device (SSP1) { Name (_ADR, 10) } // USB Port 10 |
| 342 | Device (SSP2) { Name (_ADR, 11) } // USB Port 11 |
| 343 | Device (SSP3) { Name (_ADR, 12) } // USB Port 12 |
| 344 | Device (SSP4) { Name (_ADR, 13) } // USB Port 13 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 345 | } |
| 346 | } |