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review.coreboot.org / coreboot / fddf9162a3f82ab6da5b29d3bf88b1d46b04f56d / . / src / vendorcode / google / chromeos / Kconfig
blob: 74f23d60ac53122788a6c01681748a7f45ffa59f [file] [log] [blame]
Patrick Georgic49d7a32020-05-08 22:50:46 +0200[diff] [blame]1## SPDX-License-Identifier: GPL-2.0-only
Stefan Reinauerb89a7612012-03-30 01:01:51 +0200[diff] [blame]2
Kyösti Mälkkib1b9c932013-10-17 16:38:25 +0300[diff] [blame]3config MAINBOARD_HAS_CHROMEOS
4 def_bool n
5
6menu "ChromeOS"
7 depends on MAINBOARD_HAS_CHROMEOS
8
Stefan Reinauerb89a7612012-03-30 01:01:51 +0200[diff] [blame]9config CHROMEOS
Kyösti Mälkkib1b9c932013-10-17 16:38:25 +0300[diff] [blame]10 bool "Build for ChromeOS"
Kyösti Mälkki04f5c4e2013-10-17 16:38:56 +0300[diff] [blame]11 default n
Aaron Durbind10f9d52016-08-10 11:37:14 -0500[diff] [blame]12 select ELOG if BOOT_DEVICE_SUPPORTS_WRITES
Stefan Reinauer4bddb752015-05-28 13:48:47 -0700[diff] [blame]13 select COLLECT_TIMESTAMPS
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700[diff] [blame]14 select VBOOT
Kyösti Mälkki84d10cc2021-02-10 17:53:34 +0200[diff] [blame]15 select CHROMEOS_NVS if ACPI_SOC_NVS
Patrick Rudolph28cee592018-03-08 15:43:12 +0100[diff] [blame]16 select VPD
Philipp Deppenwiesea558ca92018-07-28 23:30:49 +0200[diff] [blame]17 select VBOOT_SLOTS_RW_AB
Stefan Reinauerb89a7612012-03-30 01:01:51 +0200[diff] [blame]18 help
Stefan Reinauer9aea04a2012-03-30 12:01:06 -0700[diff] [blame]19 Enable ChromeOS specific features like the GPIO sub table in
20 the coreboot table. NOTE: Enabling this option on an unsupported
21 board will most likely break your build.
Stefan Reinauerb89a7612012-03-30 01:01:51 +0200[diff] [blame]22
Kyösti Mälkkib1b9c932013-10-17 16:38:25 +0300[diff] [blame]23if CHROMEOS
Stefan Reinauerf17789c2012-04-03 11:22:15 -0700[diff] [blame]24
Stefan Reinauer9aea04a2012-03-30 12:01:06 -0700[diff] [blame]25config CHROMEOS_RAMOOPS
Jon Murphyc4e90452022-06-28 10:36:23 -0600[diff] [blame]26 bool "Reserve space for ChromeOS ramoops"
Stefan Reinauer9aea04a2012-03-30 12:01:06 -0700[diff] [blame]27 default y
28
Stefan Reinauer9aea04a2012-03-30 12:01:06 -0700[diff] [blame]29config CHROMEOS_RAMOOPS_RAM_SIZE
30 hex "Size of preserved RAM"
31 default 0x00100000
32 depends on CHROMEOS_RAMOOPS
Stefan Reinauerf17789c2012-04-03 11:22:15 -0700[diff] [blame]33
Felix Durairaj5d935b32015-11-20 16:18:42 -0800[diff] [blame]34config HAVE_REGULATORY_DOMAIN
35 bool "Add regulatory domain methods"
36 default n
37 help
38 This option is needed to add ACPI regulatory domain methods
39
Aaron Durbinf56c7782017-01-10 17:44:42 -0600[diff] [blame]40config CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME
41 bool
42 default y
43 depends on TPM2 && RESUME_PATH_SAME_AS_BOOT
44 help
Angel Pons43d9f8b2022-03-08 10:47:19 +0100[diff] [blame]45 Disable the platform hierarchy on resume path if the firmware
Aaron Durbinf56c7782017-01-10 17:44:42 -0600[diff] [blame]46 is involved in resume. The hierarchy is disabled prior to jumping
47 to the OS. Note that this option is sepcific to TPM2 boards.
48 This option is auto selected if CHROMEOS because it matches with
49 vboot_reference model which disables the platform hierarchy in
50 the boot loader. However, those operations need to be symmetric
51 on normal boot as well as resume and coreboot is only involved
52 in the resume piece w.r.t. the platform hierarchy.
53
You-Cheng Syu85bb8742019-03-12 13:02:18 +0800[diff] [blame]54config CHROMEOS_USE_EC_WATCHDOG_FLAG
55 bool
56 default n
57 help
58 Use the AP watchdog flag stored in EC.
59
Karthikeyan Ramasubramanianb9042cb2020-08-20 16:04:58 -0600[diff] [blame]60config CHROMEOS_CSE_BOARD_RESET_OVERRIDE
61 bool
62 default n
63 depends on SOC_INTEL_CSE_LITE_SKU
64 help
65 On some boards that run old firmware version in cr50, Embedded Controller (EC) needs
66 to trigger the cold reset of Application Processor (AP) when CSE jumps from RO to RW
67 so that cr50 resets the TPM state. This is required on boards where the cr50 firmware
68 does not understand the new cr50 strap config (applicable only to boards using strap
69 config 0xe). Enabling this config will help to override the default global reset.
70
Nick Vaccaroedecf462020-09-22 17:15:49 -0700[diff] [blame]71config CHROMEOS_DRAM_PART_NUMBER_IN_CBI
72 def_bool n
73 depends on EC_GOOGLE_CHROMEEC
74 help
75 Some boards declare the DRAM part number in the CBI instead of the SPD. This option
76 allows those boards to declare that their DRAM part number is stored in the CBI.
77
Kyösti Mälkki84d10cc2021-02-10 17:53:34 +0200[diff] [blame]78config CHROMEOS_NVS
79 bool
80 depends on ACPI_SOC_NVS
81
Shelley Chenfddf9162024-01-03 14:00:07 -0800[diff] [blame^]82config CHROMEOS_FW_SPLASH_SCREEN
83 bool "Display Splash Screen in firmware"
84 default n
85 select BMP_LOGO
86 select HAVE_CUSTOM_BMP_LOGO
87 help
88 Select this option to display the manufacturer's logo or
89 custom image (OEM splash screen) early in the boot process.
90 This can enhance the user experience by providing visual
91 feedback while the system starts up. For example, ChromeOS
92 devices use this option to show their logo before the operating
93 system loads.
94
95config CHROMEOS_LOGO_PATH
96 string "Path to ChromeOS logo file"
97 depends on CHROMEOS_FW_SPLASH_SCREEN
98 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
99
100config CHROMEBOOK_PLUS_LOGO_PATH
101 string "Path to Chromebook Plus logo file"
102 depends on CHROMEOS_FW_SPLASH_SCREEN
103 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
104
Daisuke Nojiri742fc8d2014-10-10 10:51:06 -0700[diff] [blame]105endif # CHROMEOS
Kyösti Mälkkib1b9c932013-10-17 16:38:25 +0300[diff] [blame]106endmenu