src/mainboard/google/brya/variants/anraggar/overridetree.cb

chip soc/intel/alderlake
	register "sagv" = "SaGv_Enabled"

	# EMMC Tx CMD Delay
	# Refer to EDS-Vol2-42.3.7.
	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"

	# EMMC TX DATA Delay 1
	# Refer to EDS-Vol2-42.3.8.
	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"

	# EMMC TX DATA Delay 2
	# Refer to EDS-Vol2-42.3.9.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"

	# EMMC RX CMD/DATA Delay 1
	# Refer to EDS-Vol2-42.3.10.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"

	# EMMC RX CMD/DATA Delay 2
	# Refer to EDS-Vol2-42.3.12.
	# [17:16] stands for Rx Clock before Output Buffer,
	#         00: Rx clock after output buffer,
	#         01: Rx clock before output buffer,
	#         10: Automatic selection based on working mode.
	#         11: Reserved
	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10051"

	# EMMC Rx Strobe Delay
	# Refer to EDS-Vol2-42.3.11.
	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"

	# SOC Aux orientation override:
	# This is a bitfield that corresponds to up to 4 TCSS ports.
	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
	# TcssAuxOri = 0100b
	# Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
	# Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
	# motherboard to USBC connector
	register "tcss_aux_ori" = "4"

	register "typec_aux_bias_pads[1]" = "{
		.pad_auxp_dc = GPP_E22,
		.pad_auxn_dc = GPP_E23
	}"

	# FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn
	# bypass rails implemented.
	register "ext_fivr_settings" = "{
		.configure_ext_fivr = 0,
	}"

	# Intel Common SoC Config
	#+-------------+------------------------------+
	#| Field	|  Value			|
	#+-------------+------------------------------+
	#| I2C0	| TPM. Early init is		|
	#|		| required to set up a BAR	|
	#|		| for TPM communication	|
	#| I2C1	| Touchscreen			|
	#| I2C2	| Sub-board(PSensor)/WCAM	|
	#| I2C3	| Audio			|
	#| I2C5	| Trackpad			|
	#+-------------+------------------------------+
	register "common_soc_config" = "{
		.i2c[0] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST_PLUS,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST_PLUS,
				.scl_lcnt = 55,
				.scl_hcnt = 30,
				.sda_hold = 7,
			}
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 160,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 157,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 157,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
		.i2c[5] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 152,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
	}"

	device domain 0 on
		device ref dtt on
			chip drivers/intel/dptf
				## sensor information
				register "options.tsr[0].desc" = ""Memory""
				register "options.tsr[1].desc" = ""Charger""
				register "options.tsr[2].desc" = ""Ambient""

				# TODO: below values are initial reference values only
				## Passive Policy
				register "policies.passive" = "{
					[0] = DPTF_PASSIVE(CPU,    	CPU,    	95, 5000),
					[1] = DPTF_PASSIVE(CPU,    	TEMP_SENSOR_0,	75, 5000),
					[2] = DPTF_PASSIVE(CHARGER,    TEMP_SENSOR_1,	75, 5000),
					[3] = DPTF_PASSIVE(CPU,    	TEMP_SENSOR_2,	75, 5000),
				}"

				## Critical Policy
				register "policies.critical" = "{
					[0] = DPTF_CRITICAL(CPU,    		105, SHUTDOWN),
					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,	85, SHUTDOWN),
					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,	85, SHUTDOWN),
					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,	85, SHUTDOWN),
				}"

				register "controls.power_limits" = "{
					.pl1 = {
							.min_power = 3000,
							.max_power = 6000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 200
						},
					.pl2 = {
							.min_power = 25000,
							.max_power = 25000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 1000
						}
				}"

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf" = "{
					[0] = { 255, 1700 },
					[1] = {  24, 1500 },
					[2] = {  16, 1000 },
					[3] = {   8,  500 }
				}"

				device generic 0 on end
			end
		end
		device ref igpu on
			chip drivers/gfx/generic
				register "device_count" = "4"
				# DDIA for eDP
				register "device[0].name" = ""LCD""
				# DDIB for HDMI
				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
				register "device[1].name" = ""DD01""
				# TCP0 (DP-1) for port C0
				register "device[2].name" = ""DD02""
				register "device[2].use_pld" = "true"
				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
				# TCP1 (DP-2) for port C1
				register "device[3].name" = ""DD03""
				register "device[3].use_pld" = "true"
				register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
				device generic 0 on end
			end
		end
		device ref ipu on
			chip drivers/intel/mipi_camera
				register "acpi_uid" = "0x50000"
				register "acpi_name" = ""IPU0""
				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"

				register "cio2_num_ports" = "1"
				register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
				register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
				register "cio2_prt[0]" = "1"
				device generic 0 on end
			end
		end
		device ref i2c1 on
			chip drivers/i2c/hid
				register "generic.hid" = ""ILTK0001""
				register "generic.desc" = ""ILITEK Touchscreen""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
				register "generic.detect" = "1"
				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
				register "generic.reset_delay_ms" = "200"
				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
				register "generic.enable_delay_ms" = "12"
				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
				register "generic.stop_off_delay_ms" = "2"
				register "generic.has_power_resource" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 41 on end
			end
			chip drivers/generic/gpio_keys
				register "name" = ""PENH""
				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
				register "key.wake_gpe" = "GPE0_DW2_15"
				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
				register "key.dev_name" = ""EJCT""
				register "key.linux_code" = "SW_PEN_INSERTED"
				register "key.linux_input_type" = "EV_SW"
				register "key.label" = ""pen_eject""
				device generic 0 on end
			end
		end
		device ref i2c2 on
			chip drivers/intel/mipi_camera
				register "acpi_hid" = ""OVTIDB10""
				register "acpi_uid" = "0"
				register "acpi_name" = ""CAM0""
				register "chip_name" = ""Ov 13b10 Camera""
				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"

				register "ssdb.lanes_used" = "4"
				register "ssdb.vcm_type" = "0x0C"
				register "vcm_name" = ""VCM0""
				register "num_freq_entries" = "1"
				register "link_freq[0]" = "560 * MHz"
				register "remote_name" = ""IPU0""

				register "has_power_resource" = "1"
				#Controls
				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"

				register "gpio_panel.gpio[0].gpio_num" = "GPP_F18"  # EN_PP2800_WCAM_X
				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1200_WCAM_X
				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3"   # WCAM_RST_L

				#_ON
				register "on_seq.ops_cnt" = "4"
				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"

				#_OFF
				register "off_seq.ops_cnt" = "4"
				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"

				device i2c 36 on end
			end
			chip drivers/intel/mipi_camera
				register "acpi_uid" = "2"
				register "acpi_name" = ""VCM0""
				register "chip_name" = ""DW9714 VCM ""
				register "device_type" = "INTEL_ACPI_CAMERA_VCM"

				register "vcm_compat" = ""dongwoon,dw9714""

				register "has_power_resource" = "1"
				#Controls
				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_AFVDD

				#_ON
				register "on_seq.ops_cnt" = "1"
				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"

				#_OFF
				register "off_seq.ops_cnt" = "1"
				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"

				device i2c 0C on end
			end
			chip drivers/intel/mipi_camera
				register "acpi_uid" = "1"
				register "acpi_name" = ""NVM0""
				register "chip_name" = ""GT24P64E""
				register "device_type" = "INTEL_ACPI_CAMERA_NVM"

				register "nvm_size" = "0x2000"
				register "nvm_pagesize" = "1"
				register "nvm_readonly" = "1"
				register "nvm_width" = "0x10"
				register "nvm_compat" = ""atmel,24c64""

				device i2c 50 on end
			end
		end
		device ref i2c3 on
			chip drivers/i2c/generic
				register "hid" = ""10EC5650""
				register "name" = ""RT58""
				register "desc" = ""Realtek RT5650""
				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
				register "property_count" = "1"
				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
				register "property_list[0].name" = ""realtek,jd-mode""
				register "property_list[0].integer" = "2"
				device i2c 1a on end
			end
		end
		device ref i2c5 on
			chip drivers/i2c/hid
				register "generic.hid" = ""PNP0C50""
				register "generic.desc" = ""PRIMAX Touchpad""
				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
				register "generic.wake" = "GPE0_DW2_14"
				register "generic.detect" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 15 on end
			end
		end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				register "enable_cnvi_ddr_rfim" = "true"
				register "add_acpi_dma_property" = "true"
				device generic 0 on end
			end
		end
		device ref pcie_rp4 on
			# PCIe 4 WLAN
			register "pch_pcie_rp[PCH_RP(4)]" = "{
				.clk_src = 2,
				.clk_req = 2,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			chip drivers/wifi/generic
				register "wake" = "GPE0_DW1_03"
				register "add_acpi_dma_property" = "true"
				device pci 00.0 on end
			end
		end
		device ref pch_espi on
			chip ec/google/chromeec
				use conn0 as mux_conn[0]
				use conn1 as mux_conn[1]
				device pnp 0c09.0 on end
			end
		end
		device ref pmc hidden
			chip drivers/intel/pmc_mux
				device generic 0 on
					chip drivers/intel/pmc_mux/conn
						use usb2_port1 as usb2_port
						use tcss_usb3_port1 as usb3_port
						device generic 0 alias conn0 on end
					end
					chip drivers/intel/pmc_mux/conn
						use usb2_port2 as usb2_port
						use tcss_usb3_port2 as usb3_port
						device generic 1 alias conn1 on end
					end
				end
			end
		end
		device ref tcss_xhci on
			chip drivers/usb/acpi
				device ref tcss_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C0 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
						device ref tcss_usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C1 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
						device ref tcss_usb3_port2 on end
					end
				end
			end
		end
		device ref xhci on
			register "usb2_ports" = "{
				[0] = USB2_PORT_TYPE_C(OC_SKIP),	/* Type-C MB (7.5 inch) */
				[1] = USB2_PORT_TYPE_C(OC_SKIP),	/* Type-C DB (7.1 inch) */
				[2] = USB2_PORT_MID(OC_SKIP),		/* Type-A MB (6.4 inch) */
				[3] = USB2_PORT_MID(OC_SKIP),		/* Type-A DB (6.2 inch) */
				[4] = USB2_PORT_SHORT(OC_SKIP),	/* LTE (3.3 inch) */
				[5] = USB2_PORT_SHORT(OC_SKIP),	/* UFC (3.7 inch) */
				[7] = USB2_PORT_SHORT(OC_SKIP),	/* Bluetooth port for PCIe WLAN (2.5 inch) */
				[9] = USB2_PORT_SHORT(OC_SKIP),	/* Bluetooth port for CNVi WLAN */
			}"
			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref usb2_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C1 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref usb2_port2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A0 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
						device ref usb2_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb2_port4 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 LTE""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port5 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 UFC""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port6 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""PCIe Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
						device ref usb2_port8 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""CNVi Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
						device ref usb2_port10 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A0 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
						device ref usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb3_port2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 WWAN""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb3_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 WLAN""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb3_port4 on end
					end
				end
			end
		end
		device ref hda on
			chip drivers/sof
				register "spkr_tplg" = "rt5650_sp"
				register "jack_tplg" = "rt5650_hp"
				register "mic_tplg" = "_2ch_pdm0"
				device generic 0 on end
			end
		end
	end
end