Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Stefan Reinauer | b89a761 | 2012-03-30 01:01:51 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | b1b9c93 | 2013-10-17 16:38:25 +0300 | [diff] [blame] | 3 | config MAINBOARD_HAS_CHROMEOS |
| 4 | def_bool n |
| 5 | |
| 6 | menu "ChromeOS" |
| 7 | depends on MAINBOARD_HAS_CHROMEOS |
| 8 | |
Stefan Reinauer | b89a761 | 2012-03-30 01:01:51 +0200 | [diff] [blame] | 9 | config CHROMEOS |
Kyösti Mälkki | b1b9c93 | 2013-10-17 16:38:25 +0300 | [diff] [blame] | 10 | bool "Build for ChromeOS" |
Kyösti Mälkki | 04f5c4e | 2013-10-17 16:38:56 +0300 | [diff] [blame] | 11 | default n |
Aaron Durbin | d10f9d5 | 2016-08-10 11:37:14 -0500 | [diff] [blame] | 12 | select ELOG if BOOT_DEVICE_SUPPORTS_WRITES |
Stefan Reinauer | 4bddb75 | 2015-05-28 13:48:47 -0700 | [diff] [blame] | 13 | select COLLECT_TIMESTAMPS |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 14 | select VBOOT |
Patrick Rudolph | 28cee59 | 2018-03-08 15:43:12 +0100 | [diff] [blame] | 15 | select VPD |
Philipp Deppenwiese | a558ca9 | 2018-07-28 23:30:49 +0200 | [diff] [blame] | 16 | select VBOOT_SLOTS_RW_AB |
Stefan Reinauer | b89a761 | 2012-03-30 01:01:51 +0200 | [diff] [blame] | 17 | help |
Stefan Reinauer | 9aea04a | 2012-03-30 12:01:06 -0700 | [diff] [blame] | 18 | Enable ChromeOS specific features like the GPIO sub table in |
| 19 | the coreboot table. NOTE: Enabling this option on an unsupported |
| 20 | board will most likely break your build. |
Stefan Reinauer | b89a761 | 2012-03-30 01:01:51 +0200 | [diff] [blame] | 21 | |
Kyösti Mälkki | b1b9c93 | 2013-10-17 16:38:25 +0300 | [diff] [blame] | 22 | if CHROMEOS |
Stefan Reinauer | f17789c | 2012-04-03 11:22:15 -0700 | [diff] [blame] | 23 | |
Aaron Durbin | eeb7737 | 2017-03-08 11:23:11 -0600 | [diff] [blame] | 24 | config CR50_IMMEDIATELY_COMMIT_FW_SECDATA |
| 25 | bool |
Philipp Deppenwiese | c07f8fb | 2018-02-27 19:40:52 +0100 | [diff] [blame] | 26 | default y if TPM_CR50 |
Aaron Durbin | eeb7737 | 2017-03-08 11:23:11 -0600 | [diff] [blame] | 27 | |
Stefan Reinauer | 9aea04a | 2012-03-30 12:01:06 -0700 | [diff] [blame] | 28 | config CHROMEOS_RAMOOPS |
| 29 | bool "Reserve space for Chrome OS ramoops" |
| 30 | default y |
| 31 | |
Stefan Reinauer | 9aea04a | 2012-03-30 12:01:06 -0700 | [diff] [blame] | 32 | config CHROMEOS_RAMOOPS_RAM_SIZE |
| 33 | hex "Size of preserved RAM" |
| 34 | default 0x00100000 |
| 35 | depends on CHROMEOS_RAMOOPS |
Stefan Reinauer | f17789c | 2012-04-03 11:22:15 -0700 | [diff] [blame] | 36 | |
Felix Durairaj | 5d935b3 | 2015-11-20 16:18:42 -0800 | [diff] [blame] | 37 | config HAVE_REGULATORY_DOMAIN |
| 38 | bool "Add regulatory domain methods" |
| 39 | default n |
| 40 | help |
| 41 | This option is needed to add ACPI regulatory domain methods |
| 42 | |
Aaron Durbin | f56c778 | 2017-01-10 17:44:42 -0600 | [diff] [blame] | 43 | config CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME |
| 44 | bool |
| 45 | default y |
| 46 | depends on TPM2 && RESUME_PATH_SAME_AS_BOOT |
| 47 | help |
| 48 | Disable the platform heirarchy on resume path if the firmware |
| 49 | is involved in resume. The hierarchy is disabled prior to jumping |
| 50 | to the OS. Note that this option is sepcific to TPM2 boards. |
| 51 | This option is auto selected if CHROMEOS because it matches with |
| 52 | vboot_reference model which disables the platform hierarchy in |
| 53 | the boot loader. However, those operations need to be symmetric |
| 54 | on normal boot as well as resume and coreboot is only involved |
| 55 | in the resume piece w.r.t. the platform hierarchy. |
| 56 | |
You-Cheng Syu | 85bb874 | 2019-03-12 13:02:18 +0800 | [diff] [blame] | 57 | config CHROMEOS_USE_EC_WATCHDOG_FLAG |
| 58 | bool |
| 59 | default n |
| 60 | help |
| 61 | Use the AP watchdog flag stored in EC. |
| 62 | |
Cheng-Yi Chiang | cfde82c | 2019-10-14 12:10:51 +0800 | [diff] [blame] | 63 | config CHROMEOS_DSM_CALIB |
| 64 | bool |
| 65 | default n |
| 66 | help |
| 67 | On some boards, there are calibrated parameters for Dynamic Speaker Management(DSM) |
| 68 | stored in VPD. Enable this config to read and parse these VPD values and write them |
| 69 | to ACPI DSD table in device driver. These parameters will be applied by kernel driver |
| 70 | through device property at boot. |
| 71 | |
Karthikeyan Ramasubramanian | b9042cb | 2020-08-20 16:04:58 -0600 | [diff] [blame] | 72 | config CHROMEOS_CSE_BOARD_RESET_OVERRIDE |
| 73 | bool |
| 74 | default n |
| 75 | depends on SOC_INTEL_CSE_LITE_SKU |
| 76 | help |
| 77 | On some boards that run old firmware version in cr50, Embedded Controller (EC) needs |
| 78 | to trigger the cold reset of Application Processor (AP) when CSE jumps from RO to RW |
| 79 | so that cr50 resets the TPM state. This is required on boards where the cr50 firmware |
| 80 | does not understand the new cr50 strap config (applicable only to boards using strap |
| 81 | config 0xe). Enabling this config will help to override the default global reset. |
| 82 | |
Nick Vaccaro | edecf46 | 2020-09-22 17:15:49 -0700 | [diff] [blame] | 83 | config CHROMEOS_DRAM_PART_NUMBER_IN_CBI |
| 84 | def_bool n |
| 85 | depends on EC_GOOGLE_CHROMEEC |
| 86 | help |
| 87 | Some boards declare the DRAM part number in the CBI instead of the SPD. This option |
| 88 | allows those boards to declare that their DRAM part number is stored in the CBI. |
| 89 | |
Daisuke Nojiri | 742fc8d | 2014-10-10 10:51:06 -0700 | [diff] [blame] | 90 | endif # CHROMEOS |
Kyösti Mälkki | b1b9c93 | 2013-10-17 16:38:25 +0300 | [diff] [blame] | 91 | endmenu |