Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 4 | #include <bootstate.h> |
| 5 | #include <cbfs.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 6 | #include <console/console.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <fsp/api.h> |
| 10 | #include <fsp/util.h> |
| 11 | #include <intelblocks/fast_spi.h> |
| 12 | #include <soc/iomap.h> |
| 13 | #include <soc/intel/common/vbt.h> |
| 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/ramstage.h> |
| 16 | #include <soc/fiamux.h> |
| 17 | #include <spi-generic.h> |
Julien Viard de Galbert | 2d0aaa7 | 2018-02-26 18:32:59 +0100 | [diff] [blame] | 18 | #include <soc/hob_mem.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 19 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 20 | static struct device_operations pci_domain_ops = { |
| 21 | .read_resources = &pci_domain_read_resources, |
| 22 | .set_resources = &pci_domain_set_resources, |
| 23 | .scan_bus = &pci_domain_scan_bus, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 27 | .read_resources = noop_read_resources, |
| 28 | .set_resources = noop_set_resources, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 29 | .init = denverton_init_cpus, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 30 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 31 | .acpi_fill_ssdt = generate_cpu_entries, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 32 | #endif |
| 33 | }; |
| 34 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 35 | static void soc_enable_dev(struct device *dev) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 36 | { |
| 37 | /* Set the operations if it is a special bus type */ |
| 38 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 39 | dev->ops = &pci_domain_ops; |
| 40 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 41 | dev->ops = &cpu_bus_ops; |
| 42 | } |
| 43 | |
Julien Viard de Galbert | 2d0aaa7 | 2018-02-26 18:32:59 +0100 | [diff] [blame] | 44 | static void soc_init(void *data) |
| 45 | { |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 46 | fsp_silicon_init(); |
Julien Viard de Galbert | 2d0aaa7 | 2018-02-26 18:32:59 +0100 | [diff] [blame] | 47 | soc_save_dimm_info(); |
| 48 | } |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 49 | |
| 50 | static void soc_final(void *data) {} |
| 51 | |
| 52 | static void soc_silicon_init_params(FSPS_UPD *silupd) |
| 53 | { |
| 54 | size_t num; |
| 55 | uint16_t supported_hsio_lanes; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 56 | BL_HSIO_INFORMATION *hsio_config; |
| 57 | BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data(); |
| 58 | |
| 59 | /* Configure FIA MUX PCD */ |
| 60 | supported_hsio_lanes = |
| 61 | (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed; |
| 62 | |
Julien Viard de Galbert | f528195 | 2017-11-06 13:19:58 +0100 | [diff] [blame] | 63 | num = mainboard_get_hsio_config(&hsio_config); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 64 | |
| 65 | if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config)) |
| 66 | die("HSIO Configuration is invalid, please correct it!"); |
| 67 | |
| 68 | /* Check the requested FIA MUX Configuration */ |
| 69 | if (!(&hsio_config->FiaConfig)) { |
| 70 | die("Requested FIA MUX Configuration is invalid," |
| 71 | " please correct it!"); |
| 72 | } |
| 73 | |
| 74 | /* Initialize PCIE Bifurcation & HSIO configuration */ |
| 75 | silupd->FspsConfig.PcdBifurcationPcie0 = hsio_config->PcieBifCtr[0]; |
| 76 | silupd->FspsConfig.PcdBifurcationPcie1 = hsio_config->PcieBifCtr[1]; |
| 77 | |
| 78 | silupd->FspsConfig.PcdFiaMuxConfigRequestPtr = |
| 79 | (uint32_t)&hsio_config->FiaConfig; |
| 80 | } |
| 81 | |
| 82 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
| 83 | { |
| 84 | const struct microcode *microcode_file; |
| 85 | size_t microcode_len; |
| 86 | |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame] | 87 | microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 88 | |
| 89 | if ((microcode_file != NULL) && (microcode_len != 0)) { |
| 90 | /* Update CPU Microcode patch base address/size */ |
| 91 | silupd->FspsConfig.PcdCpuMicrocodePatchBase = |
| 92 | (uint32_t)microcode_file; |
| 93 | silupd->FspsConfig.PcdCpuMicrocodePatchSize = |
| 94 | (uint32_t)microcode_len; |
| 95 | } |
| 96 | |
| 97 | soc_silicon_init_params(silupd); |
| 98 | mainboard_silicon_init_params(silupd); |
| 99 | } |
| 100 | |
| 101 | struct chip_operations soc_intel_denverton_ns_ops = { |
| 102 | CHIP_NAME("Intel Denverton-NS SOC") |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 103 | .enable_dev = soc_enable_dev, |
| 104 | .init = soc_init, |
| 105 | .final = soc_final |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 106 | }; |
| 107 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 108 | struct pci_operations soc_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 109 | .set_subsystem = pci_dev_set_subsystem, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 110 | }; |
| 111 | |
| 112 | /* |
| 113 | * spi_flash init() needs to run unconditionally on every boot (including |
| 114 | * resume) to allow write protect to be disabled for eventlog and nvram |
| 115 | * updates. This needs to be done as early as possible in ramstage. Thus, add a |
| 116 | * callback for entry into BS_PRE_DEVICE. |
| 117 | */ |
| 118 | static void spi_flash_init_cb(void *unused) |
| 119 | { |
| 120 | fast_spi_init(); |
| 121 | } |
| 122 | |
| 123 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); |