Sean Rhodes | 2e665eb | 2021-06-01 22:55:07 +0100 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | # Disable DEEP |
| 3 | register "deep_s3_enable_ac" = "0" |
| 4 | register "deep_s3_enable_dc" = "0" |
| 5 | register "deep_s5_enable_ac" = "0" |
| 6 | register "deep_s5_enable_dc" = "0" |
| 7 | register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
| 8 | |
| 9 | # Enable "Intel Speed Shift Technology" |
| 10 | register "eist_enable" = "1" |
| 11 | |
| 12 | # Disable DPTF |
| 13 | register "dptf_enable" = "0" |
| 14 | |
| 15 | register "common_soc_config" = "{ |
| 16 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 17 | }" |
| 18 | |
| 19 | # Send an extra VR mailbox command for the PS4 exit issue |
| 20 | # register "SendVrMbxCmd" = "2" |
| 21 | |
| 22 | # Graphics (soc/intel/skylake/graphics.c) |
| 23 | register "panel_cfg" = "{ |
| 24 | .up_delay_ms= 200,// T3 |
| 25 | .down_delay_ms= 0,// T10 |
| 26 | .cycle_delay_ms = 500,// T12 |
| 27 | .backlight_on_delay_ms=50,// T7 |
| 28 | .backlight_off_delay_ms = 0,// T9 |
| 29 | .backlight_pwm_hz = 200, |
| 30 | }" |
| 31 | |
| 32 | # IGD Displays |
| 33 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 34 | |
| 35 | # CPU (soc/intel/skylake/chip.c) |
| 36 | # Power limit |
| 37 | register "power_limits_config" = "{ |
| 38 | .tdp_pl1_override = 20, |
| 39 | .tdp_pl2_override = 30, |
| 40 | }" |
| 41 | |
| 42 | # FSP configuration |
| 43 | register "SaGv" = "SaGv_Enabled" |
| 44 | |
| 45 | # Serial I/O |
| 46 | register "SerialIoDevMode" = "{ |
| 47 | [PchSerialIoIndexI2C0]= PchSerialIoPci, |
| 48 | [PchSerialIoIndexI2C1]= PchSerialIoPci, |
| 49 | [PchSerialIoIndexI2C2]= PchSerialIoPci, |
| 50 | [PchSerialIoIndexI2C3]= PchSerialIoPci, |
| 51 | [PchSerialIoIndexI2C4]= PchSerialIoDisabled, |
| 52 | [PchSerialIoIndexI2C5]= PchSerialIoPci, |
| 53 | [PchSerialIoIndexSpi0]= PchSerialIoPci, |
| 54 | [PchSerialIoIndexSpi1]= PchSerialIoPci, |
| 55 | [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
| 56 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 57 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 58 | }" |
| 59 | |
| 60 | # Power |
| 61 | register "PmConfigSlpS3MinAssert" = "3" # 50ms |
| 62 | register "PmConfigSlpS4MinAssert" = "3" # 1s |
| 63 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 64 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 65 | |
| 66 | # Thermal |
| 67 | register "tcc_offset" = "5" |
| 68 | |
| 69 | # PM Util (soc/intel/skylake/pmutil.c) |
| 70 | # GPE configuration |
| 71 | # Note that GPE events called out in ASL code rely on this |
| 72 | # route. i.e. If this route changes then the affected GPE |
| 73 | # offset bits also need to be changed. |
| 74 | # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) |
| 75 | register "gpe0_dw0" = "GPP_B" |
| 76 | register "gpe0_dw1" = "GPP_C" |
| 77 | register "gpe0_dw2" = "GPP_E" |
| 78 | |
| 79 | # Enable the correct decode ranges on the LPC bus. |
| 80 | register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66" |
| 81 | |
| 82 | # Actual device tree. |
| 83 | device cpu_cluster 0 on |
| 84 | device lapic 0 on end |
| 85 | end |
| 86 | |
| 87 | device domain 0 on |
| 88 | device pci 00.0 on end # Host Bridge |
| 89 | device pci 02.0 on end # Integrated Graphics Device |
| 90 | device pci 04.0 on end # SA Thermal Device |
| 91 | device pci 14.0 on # USB xHCI |
| 92 | # USB2 |
| 93 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 1 |
| 94 | register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A port 2 |
| 95 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 96 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # uSD Card |
| 97 | register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A port 3 |
| 98 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Camera |
| 99 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Actual Bluetooth port |
| 100 | |
| 101 | # USB3 |
| 102 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 103 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" |
| 104 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" |
| 105 | end |
| 106 | device pci 14.1 off end # USB xDCI (OTG) |
| 107 | device pci 14.2 on end # Thermal Subsystem |
| 108 | device pci 15.0 on # I2C #0 |
| 109 | chip drivers/i2c/hid |
| 110 | register "generic.hid" = ""StarPoint"" |
| 111 | register "generic.desc" = ""Touchpad"" |
| 112 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" |
| 113 | register "generic.probed" = "1" |
| 114 | register "hid_desc_reg_offset" = "0x20" |
| 115 | device i2c 2c on end |
| 116 | end |
| 117 | end |
| 118 | device pci 15.1 on end # I2C #1 |
| 119 | device pci 15.2 off end # I2C #2 |
| 120 | device pci 15.3 off end # I2C #3 |
| 121 | device pci 16.0 on end # Management Engine Interface 1 |
| 122 | device pci 16.1 off end # Management Engine Interface 2 |
| 123 | device pci 16.2 off end # Management Engine IDE-R |
| 124 | device pci 16.3 off end # Management Engine KT Redirection |
| 125 | device pci 16.4 off end # Management Engine Interface 3 |
| 126 | device pci 17.0 on # SATA |
| 127 | register "SataSalpSupport" = "0" |
| 128 | register "SataMode" = "0" |
| 129 | |
| 130 | # Port 1 |
| 131 | register "SataPortsEnable[1]" = "1" |
| 132 | register "SataPortsDevSlp[1]" = "0" |
| 133 | |
| 134 | # Port 2 |
| 135 | register "SataPortsEnable[2]" = "1" |
| 136 | register "SataPortsDevSlp[2]" = "0" |
| 137 | end |
| 138 | device pci 19.0 on end # UART #2 |
| 139 | device pci 19.1 off end # I2C #4 |
| 140 | device pci 19.2 off end # I2C #5 |
| 141 | device pci 1c.0 off end # PCI Express Port 1 |
| 142 | device pci 1c.1 off end # PCI Express Port 2 |
| 143 | device pci 1c.2 off end # PCI Express Port 3 |
| 144 | device pci 1c.3 off end # PCI Express Port 4 |
| 145 | device pci 1c.4 off end # PCI Express Port 5 |
| 146 | device pci 1c.5 on # PCI Express Port 6 (WLAN) |
| 147 | register "PcieRpEnable[5]" = "1" |
| 148 | register "PcieRpClkReqSupport[5]" = "1" |
| 149 | register "PcieRpClkReqNumber[5]" = "4" |
| 150 | register "PcieRpClkSrcNumber[5]" = "4" |
| 151 | register "PcieRpLtrEnable[5]" = "1" |
| 152 | chip drivers/wifi/generic |
| 153 | device pci 00.0 on end |
| 154 | end |
| 155 | end |
| 156 | device pci 1c.6 off end # PCI Express Port 7 |
| 157 | device pci 1c.7 off end # PCI Express Port 8 |
| 158 | device pci 1d.0 on # PCI Express Port 9(SSD x4) |
| 159 | device pci 00.0 on end |
| 160 | register "PcieRpEnable[8]" = "1" |
| 161 | register "PcieRpClkReqSupport[8]" = "1" |
| 162 | register "PcieRpClkReqNumber[8]" = "0" |
| 163 | register "PcieRpClkSrcNumber[8]" = "0" |
| 164 | register "PcieRpLtrEnable[8]" = "1" |
| 165 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" |
| 166 | end |
| 167 | device pci 1d.1 off end # PCI Express Port 10 |
| 168 | device pci 1d.2 off end # PCI Express Port 11 |
| 169 | device pci 1d.3 off end # PCI Express Port 12 |
| 170 | device pci 1e.0 on end # UART #0 |
| 171 | device pci 1e.1 off end # UART #1 |
| 172 | device pci 1e.2 off end # GSPI #0 |
| 173 | device pci 1e.3 off end # GSPI #1 |
| 174 | device pci 1e.4 off end # eMMC |
| 175 | device pci 1e.5 off end # SDIO |
| 176 | device pci 1e.6 off end # SDCard |
| 177 | device pci 1f.0 on # LPC Interface |
| 178 | # LPC configuration from lspci -s 1f.0 -xxx |
| 179 | # Address 0x84: Decode 0x680 - 0x68F |
| 180 | register "gen1_dec" = "0x000c0681" |
| 181 | # Address 0x88: Decode |
| 182 | register "gen2_dec" = "0x000c1641" |
| 183 | # Address 0x8C: Decode 0x200 - 0x2FF |
| 184 | register "gen3_dec" = "0x00000069" |
| 185 | # Address 0x90: Decode 0x80 - 0x8F (Port 80) |
| 186 | register "gen4_dec" = "0x0000006d" |
| 187 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 188 | |
| 189 | chip ec/starlabs/it8987 |
| 190 | # Port 4Eh/4Fh |
| 191 | device pnp 4e.0 on # IO Interface |
| 192 | end |
| 193 | end |
| 194 | end |
| 195 | device pci 1f.1 off end # P2SB |
| 196 | device pci 1f.2 on end # Power Management Controller |
| 197 | device pci 1f.3 on end # Intel HDA |
| 198 | subsystemid 0x10ec 0x111e |
| 199 | device pci 1f.4 on end # SMBus |
| 200 | device pci 1f.5 off end # PCH SPI |
| 201 | device pci 1f.6 off end # GbE |
| 202 | end |
| 203 | end |