src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb

chip soc/intel/skylake
	# Disable DEEP
	register "deep_s3_enable_ac" = "0"
	register "deep_s3_enable_dc" = "0"
	register "deep_s5_enable_ac" = "0"
	register "deep_s5_enable_dc" = "0"
	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"

	# Enable "Intel Speed Shift Technology"
	register "eist_enable" = "1"

	# Disable DPTF
	register "dptf_enable" = "0"

	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	# register "SendVrMbxCmd" = "2"

# Graphics (soc/intel/skylake/graphics.c)
	register "panel_cfg" = "{
		.up_delay_ms= 200,// T3
		.down_delay_ms= 0,// T10
		.cycle_delay_ms = 500,// T12
		.backlight_on_delay_ms=50,// T7
		.backlight_off_delay_ms = 0,// T9
		.backlight_pwm_hz = 200,
	}"

	# IGD Displays
	register "gfx" = "GMA_STATIC_DISPLAYS(0)"

# CPU (soc/intel/skylake/chip.c)
	# Power limit
	register "power_limits_config" = "{
		.tdp_pl1_override = 20,
		.tdp_pl2_override = 30,
	}"

	# FSP configuration
	register "SaGv" = "SaGv_Enabled"

	# Serial I/O
	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]= PchSerialIoPci,
		[PchSerialIoIndexI2C1]= PchSerialIoPci,
		[PchSerialIoIndexI2C2]= PchSerialIoPci,
		[PchSerialIoIndexI2C3]= PchSerialIoPci,
		[PchSerialIoIndexI2C4]= PchSerialIoDisabled,
		[PchSerialIoIndexI2C5]= PchSerialIoPci,
		[PchSerialIoIndexSpi0]= PchSerialIoPci,
		[PchSerialIoIndexSpi1]= PchSerialIoPci,
		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
	}"

	# Power
	register "PmConfigSlpS3MinAssert" = "3"		# 50ms
	register "PmConfigSlpS4MinAssert" = "3"		# 1s
	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
	register "PmConfigSlpAMinAssert" = "3"		# 2s

	# Thermal
	register "tcc_offset" = "5"

# PM Util (soc/intel/skylake/pmutil.c)
	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_C"
	register "gpe0_dw2" = "GPP_E"

	# Enable the correct decode ranges on the LPC bus.
	register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66"

# Actual device tree.
	device cpu_cluster 0 on
		device lapic 0 on end
	end

	device domain 0 on
		device pci 00.0 on  end			# Host Bridge
		device pci 02.0 on  end			# Integrated Graphics Device
		device pci 04.0 on  end			# SA Thermal Device
		device pci 14.0 on			# USB xHCI
			# USB2
			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C port 1
			register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-A port 2
			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# uSD Card
			register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"		# Type-A port 3
			register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"		# Camera
			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Actual Bluetooth port

			# USB3
			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
		end
		device pci 14.1 off end			# USB xDCI (OTG)
		device pci 14.2 on  end			# Thermal Subsystem
		device pci 15.0 on			# I2C #0
			chip drivers/i2c/hid
				register "generic.hid" = ""StarPoint""
				register "generic.desc" = ""Touchpad""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
				register "generic.probed" = "1"
				register "hid_desc_reg_offset" = "0x20"
				device i2c 2c on end
			end
		end
		device pci 15.1 on  end	# I2C #1
		device pci 15.2 off end	# I2C #2
		device pci 15.3 off end	# I2C #3
		device pci 16.0 on  end	# Management Engine Interface 1
		device pci 16.1 off end	# Management Engine Interface 2
		device pci 16.2 off end	# Management Engine IDE-R
		device pci 16.3 off end	# Management Engine KT Redirection
		device pci 16.4 off end	# Management Engine Interface 3
		device pci 17.0 on	# SATA
			register "SataSalpSupport" = "0"
			register "SataMode" = "0"

			# Port 1
			register "SataPortsEnable[1]" = "1"
			register "SataPortsDevSlp[1]" = "0"

			# Port 2
			register "SataPortsEnable[2]" = "1"
			register "SataPortsDevSlp[2]" = "0"
		end
		device pci 19.0 on  end			# UART #2
		device pci 19.1 off end			# I2C #4
		device pci 19.2 off end			# I2C #5
		device pci 1c.0 off end			# PCI Express Port 1
		device pci 1c.1 off end			# PCI Express Port 2
		device pci 1c.2 off end			# PCI Express Port 3
		device pci 1c.3 off end			# PCI Express Port 4
		device pci 1c.4 off end			# PCI Express Port 5
		device pci 1c.5 on			# PCI Express Port 6 (WLAN)
			register "PcieRpEnable[5]" = "1"
			register "PcieRpClkReqSupport[5]" = "1"
			register "PcieRpClkReqNumber[5]" = "4"
			register "PcieRpClkSrcNumber[5]" = "4"
			register "PcieRpLtrEnable[5]" = "1"
			chip drivers/wifi/generic
				device pci 00.0 on end
			end
		end
		device pci 1c.6 off end			# PCI Express Port 7
		device pci 1c.7 off end			# PCI Express Port 8
		device pci 1d.0 on			# PCI Express Port 9(SSD x4)
			device pci 00.0 on end
			register "PcieRpEnable[8]" = "1"
			register "PcieRpClkReqSupport[8]" = "1"
			register "PcieRpClkReqNumber[8]" = "0"
			register "PcieRpClkSrcNumber[8]" = "0"
			register "PcieRpLtrEnable[8]" = "1"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
		end
		device pci 1d.1 off end			# PCI Express Port 10
		device pci 1d.2 off end			# PCI Express Port 11
		device pci 1d.3 off end			# PCI Express Port 12
		device pci 1e.0 on  end			# UART #0
		device pci 1e.1 off end			# UART #1
		device pci 1e.2 off end			# GSPI #0
		device pci 1e.3 off end			# GSPI #1
		device pci 1e.4 off end			# eMMC
		device pci 1e.5 off end			# SDIO
		device pci 1e.6 off end			# SDCard
		device pci 1f.0 on			# LPC Interface
			# LPC configuration from lspci -s 1f.0 -xxx
			# Address 0x84: Decode 0x680 - 0x68F
			register "gen1_dec" = "0x000c0681"
			# Address 0x88: Decode
			register "gen2_dec" = "0x000c1641"
			# Address 0x8C: Decode 0x200 - 0x2FF
			register "gen3_dec" = "0x00000069"
			# Address 0x90: Decode 0x80 - 0x8F (Port 80)
			register "gen4_dec" = "0x0000006d"
			register "serirq_mode" = "SERIRQ_CONTINUOUS"

			chip ec/starlabs/it8987
				# Port 4Eh/4Fh
				device pnp 4e.0 on		# IO Interface
				end
			end
		end
		device pci 1f.1 off end			# P2SB
		device pci 1f.2 on  end			# Power Management Controller
		device pci 1f.3 on  end			# Intel HDA
			subsystemid 0x10ec 0x111e
		device pci 1f.4 on  end			# SMBus
		device pci 1f.5 off end			# PCH SPI
		device pci 1f.6 off end			# GbE
	end
end