Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 2 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 3 | #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H |
| 4 | #define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 5 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 6 | #define DEFAULT_TBAR ((u8 *)0xfed1b000) |
Arthur Heymans | 2e464cf | 2018-06-13 00:07:09 +0200 | [diff] [blame] | 7 | |
| 8 | #include <southbridge/intel/common/rcba.h> |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 9 | |
| 10 | #define DEFAULT_PMBASE 0x00000500 |
| 11 | #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) |
| 12 | #define DEFAULT_GPIOBASE 0x00000580 |
| 13 | |
| 14 | |
| 15 | #define APM_CNT 0xb2 |
| 16 | |
| 17 | #define PM1_STS 0x00 |
| 18 | #define PWRBTN_STS (1 << 8) |
| 19 | #define RTC_STS (1 << 10) |
| 20 | #define PM1_EN 0x02 |
| 21 | #define PWRBTN_EN (1 << 8) |
| 22 | #define GBL_EN (1 << 5) |
| 23 | #define PM1_CNT 0x04 |
| 24 | #define SCI_EN (1 << 0) |
| 25 | #define PM_LV2 0x14 |
| 26 | #define PM_LV3 0x15 |
| 27 | #define PM_LV4 0x16 |
| 28 | #define PM_LV5 0x17 |
| 29 | #define PM_LV6 0x18 |
| 30 | #define GPE0_STS 0x20 |
| 31 | #define SMI_EN 0x30 |
| 32 | #define PERIODIC_EN (1 << 14) |
| 33 | #define TCO_EN (1 << 13) |
| 34 | #define APMC_EN (1 << 5) |
| 35 | #define BIOS_EN (1 << 2) |
| 36 | #define EOS (1 << 1) |
| 37 | #define GBL_SMI_EN (1 << 0) |
| 38 | #define SMI_STS 0x34 |
| 39 | #define ALT_GP_SMI_EN 0x38 |
| 40 | #define ALT_GP_SMI_STS 0x3a |
| 41 | |
| 42 | |
| 43 | #define GP_IO_USE_SEL 0x00 |
| 44 | #define GP_IO_SEL 0x04 |
| 45 | #define GP_LVL 0x0c |
| 46 | #define GPO_BLINK 0x18 |
| 47 | #define GPI_INV 0x2c |
| 48 | #define GP_IO_USE_SEL2 0x30 |
| 49 | #define GP_IO_SEL2 0x34 |
| 50 | #define GP_LVL2 0x38 |
| 51 | |
| 52 | #define DEBUG_PERIODIC_SMIS 0 |
| 53 | |
| 54 | #define MAINBOARD_POWER_OFF 0 |
| 55 | #define MAINBOARD_POWER_ON 1 |
| 56 | #define MAINBOARD_POWER_KEEP 2 |
| 57 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 58 | /* D31:F0 LPC bridge */ |
| 59 | #define D31F0_PMBASE 0x40 |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 60 | #define PMBASE D31F0_PMBASE |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 61 | #define D31F0_ACPI_CNTL 0x44 |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 62 | #define ACPI_CNTL D31F0_ACPI_CNTL |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 63 | #define D31F0_GPIO_BASE 0x48 |
| 64 | #define D31F0_GPIO_CNTL 0x4c |
| 65 | #define D31F0_PIRQA_ROUT 0x60 |
| 66 | #define D31F0_PIRQB_ROUT 0x61 |
| 67 | #define D31F0_PIRQC_ROUT 0x62 |
| 68 | #define D31F0_PIRQD_ROUT 0x63 |
| 69 | #define D31F0_SERIRQ_CNTL 0x64 |
| 70 | #define D31F0_PIRQE_ROUT 0x68 |
| 71 | #define D31F0_PIRQF_ROUT 0x69 |
| 72 | #define D31F0_PIRQG_ROUT 0x6a |
| 73 | #define D31F0_PIRQH_ROUT 0x6b |
| 74 | #define D31F0_LPC_IODEC 0x80 |
| 75 | #define D31F0_LPC_EN 0x82 |
Arthur Heymans | de82ac7 | 2018-10-14 13:21:02 +0200 | [diff] [blame] | 76 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 77 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 78 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 79 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 80 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 81 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 82 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 83 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 84 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 85 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 86 | #define D31F0_GEN1_DEC 0x84 |
| 87 | #define D31F0_GEN2_DEC 0x88 |
| 88 | #define D31F0_GEN3_DEC 0x8c |
| 89 | #define D31F0_GEN4_DEC 0x90 |
| 90 | #define D31F0_GEN_PMCON_1 0xa0 |
| 91 | #define D31F0_GEN_PMCON_3 0xa4 |
| 92 | #define D31F0_C5_EXIT_TIMING 0xa8 |
| 93 | #define D31F0_CxSTATE_CNF 0xa9 |
| 94 | #define D31F0_C4TIMING_CNT 0xaa |
| 95 | #define D31F0_GPIO_ROUT 0xb8 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 96 | |
| 97 | /* GEN_PMCON_3 bits */ |
| 98 | #define RTC_BATTERY_DEAD (1 << 2) |
| 99 | #define RTC_POWER_FAILED (1 << 1) |
| 100 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 101 | |
| 102 | |
| 103 | /* D31:F2 SATA */ |
| 104 | #define D31F2_IDE_TIM_PRI 0x40 |
| 105 | #define D31F2_IDE_TIM_SEC 0x42 |
| 106 | #define D31F2_SIDX 0xa0 |
| 107 | #define D31F2_SDAT 0xa4 |
| 108 | |
| 109 | |
| 110 | /* D30:F0 PCI-to-PCI bridge */ |
| 111 | #define D30F0_SMLT 0x1b |
| 112 | |
| 113 | |
| 114 | /* D28:F0-5 PCIe root ports */ |
| 115 | #define D28Fx_XCAP 0x42 |
| 116 | #define D28Fx_SLCAP 0x54 |
| 117 | |
| 118 | |
| 119 | #define SMBUS_IO_BASE 0x0400 |
| 120 | |
| 121 | /* PCI Configuration Space (D31:F3): SMBus */ |
| 122 | #define SMB_BASE 0x20 |
| 123 | #define HOSTC 0x40 |
| 124 | |
| 125 | /* HOSTC bits */ |
| 126 | #define I2C_EN (1 << 2) |
| 127 | #define SMB_SMI_EN (1 << 1) |
| 128 | #define HST_EN (1 << 0) |
| 129 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 130 | #define RCBA_V0CTL 0x0014 |
| 131 | #define RCBA_V1CAP 0x001c |
| 132 | #define RCBA_V1CTL 0x0020 |
| 133 | #define RCBA_V1STS 0x0026 |
| 134 | #define RCBA_PAT 0x0030 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 135 | #define RCBA_CIR1 0x0088 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 136 | #define RCBA_ESD 0x0104 |
| 137 | #define RCBA_ULD 0x0110 |
| 138 | #define RCBA_ULBA 0x0118 |
| 139 | #define RCBA_LCAP 0x01a4 |
| 140 | #define RCBA_LCTL 0x01a8 |
| 141 | #define RCBA_LSTS 0x01aa |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 142 | #define RCBA_CIR2 0x01f4 |
| 143 | #define RCBA_CIR3 0x01fc |
| 144 | #define RCBA_BCR 0x0220 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 145 | #define RCBA_DMIC 0x0234 |
| 146 | #define RCBA_RPFN 0x0238 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 147 | #define RCBA_CIR13 0x0f20 |
| 148 | #define RCBA_CIR5 0x1d40 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 149 | #define RCBA_DMC 0x2010 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 150 | #define RCBA_CIR6 0x2024 |
| 151 | #define RCBA_CIR7 0x2034 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 152 | #define RCBA_HPTC 0x3404 |
Arthur Heymans | d6f3dd8 | 2017-12-27 00:12:35 +0100 | [diff] [blame] | 153 | #define GCS 0x3410 |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 154 | #define RCBA_BUC 0x3414 |
| 155 | #define RCBA_FD 0x3418 /* Function Disable, see below. */ |
| 156 | #define RCBA_CG 0x341c |
| 157 | #define RCBA_FDSW 0x3420 |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 158 | #define RCBA_CIR8 0x3430 |
| 159 | #define RCBA_CIR9 0x350c |
| 160 | #define RCBA_CIR10 0x352c |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 161 | #define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ |
| 162 | |
Arthur Heymans | e5c8077 | 2017-04-12 13:52:12 +0200 | [diff] [blame] | 163 | #define D31IP 0x3100 /* 32bit */ |
| 164 | #define D30IP 0x3104 /* 32bit R0: does not generate interrupt */ |
| 165 | #define D29IP 0x3108 /* 32bit */ |
| 166 | #define D28IP 0x310c /* 32bit */ |
| 167 | #define D27IP 0x3110 /* 32bit */ |
| 168 | #define D26IP 0x3114 /* 32bit */ |
| 169 | #define D25IP 0x3114 /* 32bit */ |
| 170 | |
| 171 | #define D31IR 0x3140 /* 16bit */ |
| 172 | #define D30IR 0x3142 /* 16bit R0: does not generate interrupt */ |
| 173 | #define D29IR 0x3144 /* 16bit */ |
| 174 | #define D28IR 0x3146 /* 16bit */ |
| 175 | #define D27IR 0x3148 /* 16bit */ |
| 176 | #define D26IR 0x314c /* 16bit */ |
| 177 | #define D25IR 0x3150 /* 16bit */ |
| 178 | #define OIC 0x31ff /* 8bit */ |
| 179 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 180 | #define BUC_LAND (1 << 5) /* LAN */ |
| 181 | #define FD_SAD2 (1 << 25) /* SATA #2 */ |
| 182 | #define FD_TTD (1 << 24) /* Thermal Throttle */ |
| 183 | #define FD_PE6D (1 << 21) /* PCIe root port 6 */ |
| 184 | #define FD_PE5D (1 << 20) /* PCIe root port 5 */ |
| 185 | #define FD_PE4D (1 << 19) /* PCIe root port 4 */ |
| 186 | #define FD_PE3D (1 << 18) /* PCIe root port 3 */ |
| 187 | #define FD_PE2D (1 << 17) /* PCIe root port 2 */ |
| 188 | #define FD_PE1D (1 << 16) /* PCIe root port 1 */ |
| 189 | #define FD_EHCI1D (1 << 15) /* EHCI #1 */ |
| 190 | #define FD_LBD (1 << 14) /* LPC bridge */ |
| 191 | #define FD_EHCI2D (1 << 13) /* EHCI #2 */ |
| 192 | #define FD_U5D (1 << 12) /* UHCI #5 */ |
| 193 | #define FD_U4D (1 << 11) /* UHCI #4 */ |
| 194 | #define FD_U3D (1 << 10) /* UHCI #3 */ |
| 195 | #define FD_U2D (1 << 9) /* UHCI #2 */ |
| 196 | #define FD_U1D (1 << 8) /* UHCI #1 */ |
| 197 | #define FD_U6D (1 << 7) /* UHCI #6 */ |
| 198 | #define FD_HDAD (1 << 4) /* HD audio */ |
| 199 | #define FD_SD (1 << 3) /* SMBus */ |
| 200 | #define FD_SAD1 (1 << 2) /* SATA #1 */ |
| 201 | |
| 202 | |
| 203 | #ifndef __ACPI__ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 204 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 205 | #include <device/pci_ops.h> |
| 206 | |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 207 | static inline int lpc_is_mobile(const u16 devid) |
| 208 | { |
| 209 | return (devid == 0x2917) || (devid == 0x2919); |
| 210 | } |
| 211 | #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) |
| 212 | |
Kyösti Mälkki | 1cfafe2 | 2020-01-07 12:00:31 +0200 | [diff] [blame] | 213 | #if ENV_ROMSTAGE |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 214 | int smbus_read_byte(unsigned int device, unsigned int address); |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 215 | int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, |
Arthur Heymans | d4ce1de | 2017-08-04 14:39:26 +0200 | [diff] [blame] | 216 | u8 *buf); |
| 217 | int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); |
| 218 | int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, |
| 219 | const u8 *buf); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 220 | #endif |
Arthur Heymans | c484da1 | 2019-11-09 14:29:04 +0100 | [diff] [blame] | 221 | void i82801jx_lpc_setup(void); |
Arthur Heymans | 7843bd5 | 2019-11-11 21:56:37 +0100 | [diff] [blame] | 222 | void i82801jx_setup_bars(void); |
Arthur Heymans | aa990e9 | 2019-11-11 20:08:12 +0100 | [diff] [blame] | 223 | void i82801jx_early_init(void); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 224 | |
| 225 | #endif |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 226 | |
| 227 | #endif |