Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Uwe Hermann | d436a4b | 2007-05-03 08:50:37 +0000 | [diff] [blame] | 2 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 3 | #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H |
| 4 | #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H |
Uwe Hermann | d436a4b | 2007-05-03 08:50:37 +0000 | [diff] [blame] | 5 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 6 | #if !defined(__ACPI__) |
Vladimir Serbinenko | 41877d8 | 2014-09-01 22:18:01 +0200 | [diff] [blame] | 7 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 8 | void enable_pm(void); |
Kyösti Mälkki | 7a95575 | 2020-01-07 12:18:24 +0200 | [diff] [blame] | 9 | void i82371eb_early_init(void); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 10 | |
| 11 | #if ENV_ROMSTAGE |
| 12 | int smbus_read_byte(u8 device, u8 address); |
| 13 | #endif |
| 14 | |
Stefan Reinauer | 3f5f6d8 | 2013-05-07 20:35:29 +0200 | [diff] [blame] | 15 | #endif |
Uwe Hermann | 4028ce7 | 2010-12-07 19:16:07 +0000 | [diff] [blame] | 16 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 17 | /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the |
| 18 | * 'reg' variable, otherwise it clears those bits. |
| 19 | * |
| 20 | * Examples: |
| 21 | * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5)); |
| 22 | * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR)); |
| 23 | */ |
| 24 | /* TODO: Move into some global header file? */ |
| 25 | #define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits))) |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 26 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 27 | #define XBCS 0x4e /* X-Bus chip select register */ |
| 28 | #define GENCFG 0xb0 /* General configuration register */ |
Keith Hui | 9b4b33a | 2020-01-11 13:49:59 -0500 | [diff] [blame] | 29 | #define GPO2223 (1<<28) /* GPO22/23 */ |
| 30 | #define RTCCFG 0xcb /* Real time clock configuration register */ |
| 31 | #define RTC_POS_DECODE (1<<5) |
| 32 | #define UPPER_RAM_EN (1<<2) |
| 33 | #define RTC_ENABLE (1<<0) |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 34 | |
| 35 | /* IDE */ |
| 36 | #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ |
| 37 | #define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */ |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 38 | #define UDMACTL 0x48 /* Ultra DMA/33 control register */ |
| 39 | #define UDMATIM 0x4a /* Ultra DMA/33 timing register */ |
| 40 | |
| 41 | /* SMBus */ |
| 42 | #define SMBBA 0x90 /* SMBus base address */ |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 43 | #define SMBUS_IO_BASE 0x0f00 |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 44 | #define SMBHSTCFG 0xd2 /* SMBus host configuration */ |
| 45 | |
| 46 | /* Power management (ACPI) */ |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 47 | #define PMSTS 0x00 /* Power Management Status */ |
| 48 | #define PMEN 0x02 /* Power Management Resume Enable */ |
| 49 | #define PWRBTN_EN (1<<8) |
| 50 | #define GBL_EN (1<<5) |
| 51 | #define PMCNTRL 0x04 /* Power Management Control */ |
| 52 | #define SUS_EN (1<<13) /* S0-S5 trigger */ |
| 53 | #define SUS_TYP_MSK (7<<10) |
| 54 | #define SUS_TYP_S0 (5<<10) |
| 55 | #define SUS_TYP_S1 (4<<10) |
| 56 | #define SUS_TYP_S2 (3<<10) |
| 57 | //#define SUS_TYP_S2>---(2<<10) |
| 58 | #define SUS_TYP_S3 (1<<10) |
| 59 | #define SUS_TYP_S5 (0<<10) |
| 60 | #define SCI_EN (1<<0) |
| 61 | #define PMTMR 0x08 /* Power Management Timer */ |
| 62 | #define GPSTS 0x0c /* General Purpose Status */ |
| 63 | #define GPEN 0x0e /* General Purpose Enable */ |
| 64 | #define THRM_EN (1<<0) |
| 65 | #define PCNTRL 0x10 /* Processor control */ |
| 66 | #define GLBSTS 0x18 /* Global Status */ |
| 67 | #define IRQ_RSM_STS (1<<11) |
| 68 | #define EXTSMI_STS (1<<10) |
| 69 | #define GSTBY_STS (1<<8) |
| 70 | #define GP_STS (1<<7) |
| 71 | #define BM1_STS (1<<6) |
| 72 | #define APM_STS (1<<5) |
| 73 | #define DEV_STS (1<<4) |
| 74 | #define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ |
| 75 | #define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ |
| 76 | #define DEVSTS 0x1c /* Device Status */ |
| 77 | #define GLBEN 0x20 /* Global Enable */ |
| 78 | #define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ |
| 79 | #define GSTBY_EN (1<<8) |
| 80 | #define BM_TRP_EN (1<<1) |
| 81 | #define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ |
| 82 | #define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ |
| 83 | #define GLBCTL 0x28 /* Global Control */ |
| 84 | #define EOS (1<<16) /* End of SMI */ |
| 85 | #define SMI_EN (1<<0) /* SMI enable */ |
| 86 | #define DEVCTL 0x2c /* Device Control */ |
| 87 | #define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */ |
| 88 | #define GPO0 0x34 |
| 89 | #define GPO1 0x35 |
| 90 | #define GPO2 0x36 |
| 91 | #define GPO3 0x37 |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 92 | |
Tobias Diedrich | e87c38e | 2010-11-27 09:40:16 +0000 | [diff] [blame] | 93 | #define PMBA 0x40 /* Power management base address */ |
| 94 | #define DEFAULT_PMBASE 0xe400 |
| 95 | #define PM_IO_BASE DEFAULT_PMBASE |
| 96 | #define PMREGMISC 0x80 /* Miscellaneous power management */ |
Uwe Hermann | 115c5b9 | 2010-10-09 17:00:18 +0000 | [diff] [blame] | 97 | |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 98 | /* Bit definitions */ |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 99 | #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ |
| 100 | #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ |
| 101 | #define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */ |
| 102 | #define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */ |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 103 | #define SMB_HST_EN (1 << 0) /* Host Interface Enable */ |
| 104 | #define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ |
| 105 | #define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */ |
| 106 | #define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */ |
| 107 | #define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */ |
| 108 | #define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */ |
| 109 | #define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ |
| 110 | #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ |
| 111 | #define ISA (1 << 0) /* Select ISA */ |
| 112 | #define EIO (0 << 0) /* Select EIO */ |
Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 113 | #define PMIOSE (1 << 0) /* PM I/O Space Enable */ |
Uwe Hermann | 1410c2d | 2007-05-29 10:37:52 +0000 | [diff] [blame] | 114 | |
Uwe Hermann | 9da69f8 | 2007-11-30 02:08:26 +0000 | [diff] [blame] | 115 | #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ |