blob: f30a6acd2320cc5d1f30d11d8611332de6f77453 [file] [log] [blame]
Ravi Sarawadi91ffac82022-05-07 16:37:09 -07001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <arch/io.h>
4#include <device/mmio.h>
5#include <bootstate.h>
6#include <console/console.h>
7#include <cpu/x86/smm.h>
8#include <delay.h>
9#include <device/pci.h>
10#include <intelblocks/cse.h>
11#include <intelblocks/gpio.h>
12#include <intelblocks/lpc_lib.h>
13#include <intelblocks/pcr.h>
14#include <intelblocks/pmclib.h>
15#include <intelblocks/systemagent.h>
16#include <intelblocks/tco.h>
17#include <intelblocks/thermal.h>
18#include <spi-generic.h>
19#include <intelpch/lockdown.h>
20#include <soc/p2sb.h>
21#include <soc/pci_devs.h>
22#include <soc/pcr_ids.h>
23#include <soc/pm.h>
24#include <soc/smbus.h>
25#include <soc/soc_chip.h>
26#include <soc/systemagent.h>
27#include <timer.h>
28
29static void pch_handle_sideband(config_t *config)
30{
31
32}
33
34static void pch_finalize(void)
35{
36 config_t *config = config_of_soc();
37
38 /* TCO Lock down */
39 tco_lockdown();
40
41 /* TODO: Add Thermal Configuration */
42
43 pch_handle_sideband(config);
44
45 pmc_clear_pmcon_sts();
46}
47
48static void tbt_finalize(void)
49{
50 int i;
51 const struct device *dev;
52
53 /* Disable Thunderbolt PCIe root ports bus master */
54 for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
55 dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
56 if (dev)
57 pci_dev_disable_bus_master(dev);
58 }
59}
60
61static void sa_finalize(void)
62{
63 if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
64 sa_lock_pam();
65}
66
Subrata Banikfb970a42022-11-24 19:42:55 +053067static void heci_finalize(void)
68{
69 heci_set_to_d0i3();
70 if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
71 heci1_disable();
72}
73
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070074static void soc_finalize(void *unused)
75{
76 printk(BIOS_DEBUG, "Finalizing chipset.\n");
77
78 pch_finalize();
79 apm_control(APM_CNT_FINALIZE);
80 tbt_finalize();
81 sa_finalize();
Subrata Banikfb970a42022-11-24 19:42:55 +053082 if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
83 CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
84 heci_finalize();
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070085
86 /* Indicate finalize step with post code */
87 post_code(POST_OS_BOOT);
88}
89
90BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
91/*
92 * The purpose of this change is to accommodate more time to push out sending
93 * CSE EOP messages at post.
94 */
95BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);