blob: efbb035aabbe10b7d74a353d360cfe549c075e9d [file] [log] [blame]
Felix Held3f3eca92020-01-23 17:12:32 +01001/* SPDX-License-Identifier: GPL-2.0-or-later */
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +10002
3#include <arch/io.h>
Elyes HAOUAS9b54dfa2020-08-26 18:36:13 +02004#include <device/pnp_def.h>
Kyösti Mälkki3855c012019-03-03 08:45:19 +02005#include <device/pnp_ops.h>
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +10006
7#include "it8772f.h"
Joel Linnfb516612024-03-29 14:08:35 +01008#include "../common/ite.h"
9
10#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100011
12/* NOTICE: This file is deprecated, use ite/common instead */
13
Joel Linnfb516612024-03-29 14:08:35 +010014static void it8772f_enter_conf(pnp_devfn_t dev)
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100015{
16 u16 port = dev >> 8;
17
18 outb(0x87, port);
19 outb(0x01, port);
20 outb(0x55, port);
21 outb((port == 0x4e) ? 0xaa : 0x55, port);
22}
23
Joel Linnfb516612024-03-29 14:08:35 +010024static void it8772f_exit_conf(pnp_devfn_t dev)
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100025{
Felix Held6c244bd2019-10-07 18:47:29 +020026 pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100027}
28
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100029/* Configure a set of GPIOs */
Edward O'Callaghan85836c22014-07-09 20:26:25 +100030void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity,
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100031 u8 pullup, u8 output, u8 enable)
32{
33 set--; /* Set 1 is offset 0 */
34 it8772f_enter_conf(dev);
Joel Linnfb516612024-03-29 14:08:35 +010035 pnp_set_logical_device(dev);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100036 if (set < 5) {
Felix Held6c244bd2019-10-07 18:47:29 +020037 pnp_write_config(dev, GPIO_REG_SELECT(set), select);
38 pnp_write_config(dev, GPIO_REG_ENABLE(set), enable);
39 pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100040 }
Felix Held6c244bd2019-10-07 18:47:29 +020041 pnp_write_config(dev, GPIO_REG_OUTPUT(set), output);
42 pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100043 it8772f_exit_conf(dev);
44}
david80ef7b72015-01-19 17:11:36 +080045
46/* Configure LED GPIOs */
47void it8772f_gpio_led(pnp_devfn_t dev,int set, u8 select, u8 polarity, u8 pullup,
48 u8 output, u8 enable, u8 led_pin_map, u8 led_freq)
49{
50 set--; /* Set 1 is offset 0 */
51 it8772f_enter_conf(dev);
Joel Linnfb516612024-03-29 14:08:35 +010052 pnp_set_logical_device(dev);
david80ef7b72015-01-19 17:11:36 +080053 if (set < 5) {
Felix Held6c244bd2019-10-07 18:47:29 +020054 pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map);
55 pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq);
56 pnp_write_config(dev, GPIO_REG_SELECT(set), select);
57 pnp_write_config(dev, GPIO_REG_ENABLE(set), enable);
58 pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity);
david80ef7b72015-01-19 17:11:36 +080059 }
Felix Held6c244bd2019-10-07 18:47:29 +020060 pnp_write_config(dev, GPIO_REG_OUTPUT(set), output);
61 pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup);
david80ef7b72015-01-19 17:11:36 +080062 it8772f_exit_conf(dev);
63}