Felix Held | 3f3eca9 | 2020-01-23 17:12:32 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 2 | |
| 3 | #include <arch/io.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 4 | #include <device/pnp_ops.h> |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 5 | #include <device/pnp.h> |
| 6 | #include <stdint.h> |
| 7 | #include "ite.h" |
| 8 | |
| 9 | /* Global configuration registers. */ |
Michał Kopeć | a7a40a5 | 2022-07-26 13:10:36 +0200 | [diff] [blame] | 10 | #define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ |
| 11 | #define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ |
| 12 | #define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ |
| 13 | #define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ |
| 14 | #define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */ |
| 15 | #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ |
| 16 | #define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */ |
| 17 | #define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */ |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 18 | #define ITE_CONFIG_REG_APC_PME_CTL2 0xf4 /* APC_PME Control 2 */ |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 19 | |
| 20 | /* Helper procedure */ |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 21 | static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 22 | { |
| 23 | pnp_set_logical_device(dev); |
| 24 | pnp_write_config(dev, reg, value); |
| 25 | } |
| 26 | |
| 27 | /* Enable configuration */ |
Nico Huber | 6167365 | 2016-10-11 11:56:32 +0200 | [diff] [blame] | 28 | void pnp_enter_conf_state(pnp_devfn_t dev) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 29 | { |
| 30 | u16 port = dev >> 8; |
| 31 | |
| 32 | outb(0x87, port); |
| 33 | outb(0x01, port); |
| 34 | outb(0x55, port); |
| 35 | outb((port == 0x4e) ? 0xaa : 0x55, port); |
| 36 | } |
| 37 | |
| 38 | /* Disable configuration */ |
Nico Huber | 6167365 | 2016-10-11 11:56:32 +0200 | [diff] [blame] | 39 | void pnp_exit_conf_state(pnp_devfn_t dev) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 40 | { |
| 41 | ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); |
| 42 | } |
| 43 | |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 44 | void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 45 | { |
| 46 | pnp_enter_conf_state(dev); |
| 47 | ite_sio_write(dev, reg, value); |
| 48 | pnp_exit_conf_state(dev); |
| 49 | } |
| 50 | |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 51 | /* |
| 52 | * in romstage.c |
| 53 | * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) |
| 54 | * and pass: CLKIN_DEV |
| 55 | * ITE_UART_CLK_PREDIVIDE_24 |
| 56 | * ITE_UART_CLK_PREDIVIDE_48 (default) |
| 57 | */ |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 58 | void ite_conf_clkin(pnp_devfn_t dev, u8 predivide) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 59 | { |
| 60 | ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); |
| 61 | } |
| 62 | |
| 63 | /* Bring up early serial debugging output before the RAM is initialized. */ |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 64 | void ite_enable_serial(pnp_devfn_t dev, u16 iobase) |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 65 | { |
| 66 | pnp_enter_conf_state(dev); |
| 67 | pnp_set_logical_device(dev); |
| 68 | pnp_set_enable(dev, 0); |
| 69 | pnp_set_iobase(dev, PNP_IDX_IO0, iobase); |
| 70 | pnp_set_enable(dev, 1); |
| 71 | pnp_exit_conf_state(dev); |
| 72 | } |
Rudolf Marek | a7d14a1 | 2014-05-13 15:57:47 +0200 | [diff] [blame] | 73 | |
| 74 | /* |
| 75 | * |
| 76 | * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off |
| 77 | * this was documented only in IT8712F_V0.9.2! |
| 78 | * |
| 79 | * Enable 3VSBSW#. (For System Suspend-to-RAM) |
| 80 | * 0: 3VSBSW# will be always inactive. |
| 81 | * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. |
| 82 | * |
| 83 | * in romstage.c |
| 84 | * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) |
| 85 | * and pass: GPIO_DEV |
| 86 | */ |
| 87 | |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 88 | void ite_enable_3vsbsw(pnp_devfn_t dev) |
Rudolf Marek | a7d14a1 | 2014-05-13 15:57:47 +0200 | [diff] [blame] | 89 | { |
| 90 | u8 tmp; |
| 91 | pnp_enter_conf_state(dev); |
| 92 | pnp_set_logical_device(dev); |
| 93 | tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC); |
| 94 | tmp |= 0x80; |
| 95 | pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp); |
| 96 | pnp_exit_conf_state(dev); |
| 97 | } |
| 98 | |
| 99 | /* |
Michael Büchler | 6c5f47b | 2020-08-20 16:06:26 +0200 | [diff] [blame] | 100 | * |
| 101 | * LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge |
| 102 | * This can be needed for S3 resume. |
| 103 | * Documented in IT8728F V0.4.2 but also applies to IT8720F where it is marked |
| 104 | * as reserved. |
| 105 | * |
| 106 | * Delay PWRGD3 assertion after setting 3VSBSW#. |
| 107 | * 0: There will be no extra delay before PWRGD3 is set. |
| 108 | * 1: The delay after 3VSBSW# rising edge before PWRGD3 is set is increased. |
| 109 | * |
| 110 | * in romstage.c |
| 111 | * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) |
| 112 | * and pass: GPIO_DEV |
| 113 | */ |
| 114 | |
| 115 | void ite_delay_pwrgd3(pnp_devfn_t dev) |
| 116 | { |
| 117 | u8 tmp; |
| 118 | pnp_enter_conf_state(dev); |
| 119 | pnp_set_logical_device(dev); |
| 120 | tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC); |
| 121 | tmp |= 0x01; |
| 122 | pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp); |
| 123 | pnp_exit_conf_state(dev); |
| 124 | } |
| 125 | |
| 126 | /* |
Rudolf Marek | a7d14a1 | 2014-05-13 15:57:47 +0200 | [diff] [blame] | 127 | * in romstage.c |
| 128 | * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) |
| 129 | * and pass: GPIO_DEV |
| 130 | */ |
| 131 | |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 132 | void ite_kill_watchdog(pnp_devfn_t dev) |
Rudolf Marek | a7d14a1 | 2014-05-13 15:57:47 +0200 | [diff] [blame] | 133 | { |
| 134 | pnp_enter_conf_state(dev); |
| 135 | ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00); |
Michał Kopeć | a7a40a5 | 2022-07-26 13:10:36 +0200 | [diff] [blame] | 136 | ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_LSB, 0x00); |
| 137 | ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00); |
Rudolf Marek | a7d14a1 | 2014-05-13 15:57:47 +0200 | [diff] [blame] | 138 | pnp_exit_conf_state(dev); |
| 139 | } |
Joel Linn | fb51661 | 2024-03-29 14:08:35 +0100 | [diff] [blame^] | 140 | |
| 141 | /* |
| 142 | * Set AC resume to be up to the Southbridge |
| 143 | * pass EC_DEV |
| 144 | */ |
| 145 | void ite_ac_resume_southbridge(pnp_devfn_t dev) |
| 146 | { |
| 147 | u8 tmp; |
| 148 | pnp_enter_conf_state(dev); |
| 149 | pnp_set_logical_device(dev); |
| 150 | tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL2); |
| 151 | /* |
| 152 | * Set both |
| 153 | * 6: Gate Extra PWRON# Pulse |
| 154 | * 5: PSON# state when 3VSB switched to on |
| 155 | */ |
| 156 | tmp |= 0x60; |
| 157 | pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL2, tmp); |
| 158 | pnp_exit_conf_state(dev); |
| 159 | } |