Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
| 20 | #include <assert.h> |
| 21 | #include <console/console.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <intelblocks/lpc_lib.h> |
| 24 | #include <lib.h> |
| 25 | #include "lpc_def.h" |
| 26 | #include <soc/pci_devs.h> |
| 27 | |
| 28 | void lpc_enable_fixed_io_ranges(uint16_t io_enables) |
| 29 | { |
| 30 | uint16_t reg_io_enables; |
| 31 | |
| 32 | reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); |
| 33 | io_enables |= reg_io_enables; |
| 34 | pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); |
| 35 | } |
| 36 | |
| 37 | /* |
| 38 | * Find the first unused IO window. |
| 39 | * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ... |
| 40 | */ |
| 41 | static int find_unused_pmio_window(void) |
| 42 | { |
| 43 | int i; |
| 44 | uint32_t lgir; |
| 45 | |
| 46 | for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { |
| 47 | lgir = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i)); |
| 48 | |
| 49 | if (!(lgir & LPC_LGIR_EN)) |
| 50 | return i; |
| 51 | } |
| 52 | |
| 53 | return -1; |
| 54 | } |
| 55 | |
| 56 | void lpc_close_pmio_windows(void) |
| 57 | { |
| 58 | size_t i; |
| 59 | |
| 60 | for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) |
| 61 | pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), 0); |
| 62 | } |
| 63 | |
| 64 | void lpc_open_pmio_window(uint16_t base, uint16_t size) |
| 65 | { |
| 66 | int lgir_reg_num; |
| 67 | uint32_t lgir_reg_offset, lgir, window_size, alignment; |
| 68 | resource_t bridged_size, bridge_base; |
| 69 | |
| 70 | printk(BIOS_SPEW, "LPC: Trying to open IO window from %x size %x\n", |
| 71 | base, size); |
| 72 | |
| 73 | bridged_size = 0; |
| 74 | bridge_base = base; |
| 75 | |
| 76 | while (bridged_size < size) { |
| 77 | lgir_reg_num = find_unused_pmio_window(); |
| 78 | if (lgir_reg_num < 0) { |
| 79 | printk(BIOS_ERR, |
| 80 | "LPC: Cannot open IO window: %llx size %llx\n", |
| 81 | bridge_base, size - bridged_size); |
| 82 | printk(BIOS_ERR, "No more IO windows\n"); |
| 83 | return; |
| 84 | } |
| 85 | lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); |
| 86 | |
| 87 | /* Each IO range register can only open a 256-byte window. */ |
| 88 | window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE); |
| 89 | |
| 90 | /* Window size must be a power of two for the AMASK to work. */ |
| 91 | alignment = 1 << (log2_ceil(window_size)); |
| 92 | window_size = ALIGN_UP(window_size, alignment); |
| 93 | |
| 94 | /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18]. */ |
| 95 | lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN; |
| 96 | lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK; |
| 97 | |
| 98 | pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); |
| 99 | |
| 100 | printk(BIOS_DEBUG, |
| 101 | "LPC: Opened IO window LGIR%d: base %llx size %x\n", |
| 102 | lgir_reg_num, bridge_base, window_size); |
| 103 | |
| 104 | bridged_size += window_size; |
| 105 | bridge_base += window_size; |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | void lpc_open_mmio_window(uintptr_t base, size_t size) |
| 110 | { |
| 111 | uint32_t lgmr; |
| 112 | |
| 113 | lgmr = pci_read_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE); |
| 114 | |
| 115 | if (lgmr & LPC_LGMR_EN) { |
| 116 | printk(BIOS_ERR, |
| 117 | "LPC: Cannot open window to resource %lx size %zx\n", |
| 118 | base, size); |
| 119 | printk(BIOS_ERR, "LPC: MMIO window already in use\n"); |
| 120 | return; |
| 121 | } |
| 122 | |
| 123 | if (size > LPC_LGMR_WINDOW_SIZE) { |
| 124 | printk(BIOS_WARNING, |
| 125 | "LPC: Resource %lx size %zx larger than window(%x)\n", |
| 126 | base, size, LPC_LGMR_WINDOW_SIZE); |
| 127 | } |
| 128 | |
| 129 | lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN; |
| 130 | |
| 131 | pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); |
| 132 | } |
| 133 | |
| 134 | bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size) |
| 135 | { |
| 136 | resource_t res_end, range_end; |
| 137 | const struct lpc_mmio_range *range; |
| 138 | const struct lpc_mmio_range *lpc_fixed_mmio_ranges = |
| 139 | soc_get_fixed_mmio_ranges(); |
| 140 | |
| 141 | for (range = lpc_fixed_mmio_ranges; range->size; range++) { |
| 142 | range_end = range->base + range->size; |
| 143 | res_end = base + size; |
| 144 | |
| 145 | if ((base >= range->base) && (res_end <= range_end)) { |
| 146 | printk(BIOS_DEBUG, |
| 147 | "Resource %lx size %zx fits in fixed window" |
| 148 | " %lx size %zx\n", |
| 149 | base, size, range->base, range->size); |
| 150 | return true; |
| 151 | } |
| 152 | } |
| 153 | return false; |
| 154 | } |
| 155 | |
| 156 | /* |
| 157 | * Set FAST_SPIBAR BIOS Control register based on input bit field. |
| 158 | */ |
| 159 | static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit) |
| 160 | { |
| 161 | device_t dev = PCH_DEV_LPC; |
| 162 | uint8_t bc_cntl; |
| 163 | |
Jonathan Neuschäfer | 3a182f7 | 2017-09-23 17:09:36 +0200 | [diff] [blame] | 164 | assert(IS_POWER_OF_2(bios_cntl_bit)); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 165 | bc_cntl = pci_read_config8(dev, LPC_BIOS_CNTL); |
| 166 | bc_cntl |= bios_cntl_bit; |
| 167 | pci_write_config8(dev, LPC_BIOS_CNTL, bc_cntl); |
| 168 | |
| 169 | /* |
| 170 | * Ensure an additional read back after performing lock down |
| 171 | */ |
| 172 | pci_read_config8(PCH_DEV_LPC, LPC_BIOS_CNTL); |
| 173 | } |
| 174 | |
| 175 | /* |
| 176 | * Set LPC BIOS Control BILD bit. |
| 177 | */ |
| 178 | void lpc_set_bios_interface_lock_down(void) |
| 179 | { |
| 180 | lpc_set_bios_control_reg(LPC_BC_BILD); |
| 181 | } |
| 182 | |
| 183 | /* |
| 184 | * Set LPC BIOS Control LE bit. |
| 185 | */ |
| 186 | void lpc_set_lock_enable(void) |
| 187 | { |
| 188 | lpc_set_bios_control_reg(LPC_BC_LE); |
| 189 | } |
| 190 | |
| 191 | /* |
| 192 | * Set LPC BIOS Control EISS bit. |
| 193 | */ |
| 194 | void lpc_set_eiss(void) |
| 195 | { |
| 196 | lpc_set_bios_control_reg(LPC_BC_EISS); |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * Set LPC Serial IRQ mode. |
| 201 | */ |
| 202 | void lpc_set_serirq_mode(enum serirq_mode mode) |
| 203 | { |
| 204 | device_t dev = PCH_DEV_LPC; |
| 205 | uint8_t scnt; |
| 206 | |
| 207 | scnt = pci_read_config8(dev, LPC_SERIRQ_CTL); |
| 208 | scnt &= ~(LPC_SCNT_EN | LPC_SCNT_MODE); |
| 209 | |
| 210 | switch (mode) { |
| 211 | case SERIRQ_QUIET: |
| 212 | scnt |= LPC_SCNT_EN; |
| 213 | break; |
| 214 | case SERIRQ_CONTINUOUS: |
| 215 | scnt |= LPC_SCNT_EN | LPC_SCNT_MODE; |
| 216 | break; |
| 217 | case SERIRQ_OFF: |
| 218 | default: |
| 219 | break; |
| 220 | } |
| 221 | |
| 222 | pci_write_config8(dev, LPC_SERIRQ_CTL, scnt); |
| 223 | } |
| 224 | |
| 225 | |
| 226 | void lpc_io_setup_comm_a_b(void) |
| 227 | { |
| 228 | /* |
| 229 | * Setup I/O Decode Range Register for LPC |
| 230 | * ComA Range 3F8h-3FFh [2:0] |
| 231 | * ComB Range 2F8h-2FFh [6:4] |
| 232 | */ |
| 233 | pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, |
| 234 | LPC_IOD_COMA_RANGE | LPC_IOD_COMB_RANGE); |
| 235 | /* Enable ComA and ComB Port */ |
| 236 | lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN); |
| 237 | } |
Ravi Sarawadi | a9b5a39 | 2017-09-20 13:46:19 -0700 | [diff] [blame] | 238 | |
| 239 | static void lpc_set_gen_decode_range( |
| 240 | uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) |
| 241 | { |
| 242 | size_t i; |
| 243 | |
| 244 | /* Set in PCI generic decode range registers */ |
| 245 | for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) |
| 246 | pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), |
| 247 | gen_io_dec[i]); |
| 248 | } |
| 249 | |
| 250 | static void pch_lpc_interrupt_init(void) |
| 251 | { |
| 252 | const struct device *dev; |
| 253 | |
| 254 | dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); |
| 255 | if (!dev || !dev->chip_info) |
| 256 | return; |
| 257 | |
| 258 | soc_pch_pirq_init(dev); |
| 259 | } |
| 260 | |
| 261 | void pch_enable_lpc(void) |
| 262 | { |
| 263 | /* Lookup device tree in romstage */ |
| 264 | const struct device *dev; |
| 265 | uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]; |
| 266 | |
| 267 | dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); |
| 268 | if (!dev || !dev->chip_info) |
| 269 | return; |
| 270 | |
| 271 | soc_get_gen_io_dec_range(dev, gen_io_dec); |
| 272 | lpc_set_gen_decode_range(gen_io_dec); |
| 273 | soc_setup_dmi_pcr_io_dec(gen_io_dec); |
| 274 | if (ENV_RAMSTAGE) |
| 275 | pch_lpc_interrupt_init(); |
| 276 | } |
| 277 | |
| 278 | void lpc_enable_pci_clk_cntl(void) |
| 279 | { |
| 280 | pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN); |
| 281 | } |