Angel Pons | 381c4eb | 2020-04-03 01:22:06 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 2 | |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 3 | #include <AGESA.h> |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 4 | #include <PlatformMemoryConfiguration.h> |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 5 | |
Kyösti Mälkki | f27cb24 | 2017-03-04 07:51:21 +0200 | [diff] [blame] | 6 | #include <northbridge/amd/agesa/state_machine.h> |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 7 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 8 | static const PCIe_PORT_DESCRIPTOR PortList[] = { |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 9 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 10 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 11 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), |
| 12 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 13 | HotplugDisabled, |
| 14 | PcieGenMaxSupported, |
| 15 | PcieGenMaxSupported, |
| 16 | AspmDisabled, 0x01, 0) |
| 17 | }, |
| 18 | /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ |
| 19 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 20 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 21 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), |
| 22 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 23 | HotplugDisabled, |
| 24 | PcieGenMaxSupported, |
| 25 | PcieGenMaxSupported, |
| 26 | AspmDisabled, 0x02, 0) |
| 27 | }, |
| 28 | /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ |
| 29 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 30 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 31 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), |
| 32 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 33 | HotplugDisabled, |
| 34 | PcieGenMaxSupported, |
| 35 | PcieGenMaxSupported, |
| 36 | AspmDisabled, 0x03, 0) |
| 37 | }, |
| 38 | /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ |
| 39 | { |
| 40 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 41 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), |
| 42 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 43 | HotplugDisabled, |
| 44 | PcieGenMaxSupported, |
| 45 | PcieGenMaxSupported, |
| 46 | AspmDisabled, 0x04, 0) |
| 47 | }, |
| 48 | /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ |
| 49 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 50 | DESCRIPTOR_TERMINATE_LIST, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 51 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), |
| 52 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 53 | HotplugDisabled, |
| 54 | PcieGenMaxSupported, |
| 55 | PcieGenMaxSupported, |
| 56 | AspmDisabled, 0x05, 0) |
| 57 | } |
| 58 | }; |
| 59 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 60 | static const PCIe_DDI_DESCRIPTOR DdiList[] = { |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 61 | /* DP0 to HDMI0/DP */ |
| 62 | { |
| 63 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 64 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), |
| 65 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 66 | }, |
| 67 | /* DP1 to FCH */ |
| 68 | { |
Dave Frodin | 83405a1 | 2014-06-05 11:49:04 -0600 | [diff] [blame] | 69 | DESCRIPTOR_TERMINATE_LIST, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 70 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), |
| 71 | PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2) |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 72 | }, |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| 76 | .Flags = DESCRIPTOR_TERMINATE_LIST, |
| 77 | .SocketId = 0, |
| 78 | .PciePortList = PortList, |
| 79 | .DdiLinkList = DdiList |
| 80 | }; |
| 81 | |
Kyösti Mälkki | f27cb24 | 2017-03-04 07:51:21 +0200 | [diff] [blame] | 82 | void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 83 | { |
| 84 | FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 85 | FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); |
Kyösti Mälkki | f27cb24 | 2017-03-04 07:51:21 +0200 | [diff] [blame] | 86 | FchReset->Xhci1Enable = FALSE; |
| 87 | } |
| 88 | |
Kyösti Mälkki | f27cb24 | 2017-03-04 07:51:21 +0200 | [diff] [blame] | 89 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 90 | { |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 91 | InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
Kyösti Mälkki | e75deb6 | 2014-06-26 09:12:54 +0300 | [diff] [blame] | 92 | } |
| 93 | |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 94 | /*---------------------------------------------------------------------------------------- |
Paul Menzel | 8a017aa | 2020-05-29 02:48:42 +0200 | [diff] [blame] | 95 | * CUSTOMER OVERRIDES MEMORY TABLE |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 96 | *---------------------------------------------------------------------------------------- |
| 97 | */ |
| 98 | |
| 99 | /* |
| 100 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA |
| 101 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable |
| 102 | * is populated, AGESA will base its settings on the data from the table. Otherwise, it will |
| 103 | * use its default conservative settings. |
| 104 | */ |
Kyösti Mälkki | f27cb24 | 2017-03-04 07:51:21 +0200 | [diff] [blame] | 105 | static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 106 | #define SEED_A 0x12 |
| 107 | HW_RXEN_SEED( |
| 108 | ANY_SOCKET, CHANNEL_A, ALL_DIMMS, |
| 109 | SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, |
| 110 | SEED_A), |
| 111 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 112 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, ONE_DIMM), |
| 113 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM), |
| 114 | MOTHER_BOARD_LAYERS(LAYERS_6), |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 115 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 116 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), |
| 117 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ |
| 118 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), |
| 119 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 120 | |
| 121 | PSO_END |
| 122 | }; |
| 123 | |
Kyösti Mälkki | f27cb24 | 2017-03-04 07:51:21 +0200 | [diff] [blame] | 124 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) |
| 125 | { |
| 126 | InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; |
| 127 | } |
| 128 | |
| 129 | void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) |
| 130 | { |
| 131 | /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ |
| 132 | InitMid->GnbMidConfiguration.iGpuVgaMode = 0; |
| 133 | } |