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review.coreboot.org / coreboot / f9decbb0c720662d8e71fe221aef55b7ecf76196 / . / src / mainboard / bap / ode_e20XX / bootblock.c
blob: 0acabe06c647bbe98078419951bf20b33006f85c [file] [log] [blame]
Angel Pons0fcb1b82020-04-03 01:21:20 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +0300[diff] [blame]2
Michał Żygowskiaf258cc2019-12-01 17:42:04 +0100[diff] [blame]3#include <amdblocks/acpimmio.h>
Mike Banonbb45f382020-02-13 15:45:05 +0000[diff] [blame]4#include <bootblock_common.h>
Fabian Kunkel7558dba2015-05-25 17:08:17 +0200[diff] [blame]5#include <superio/fintek/common/fintek.h>
6#include <superio/fintek/f81866d/f81866d.h>
Kyösti Mälkki7a0aa9a2016-12-20 06:43:44 +0200[diff] [blame]7
Fabian Kunkel7558dba2015-05-25 17:08:17 +0200[diff] [blame]8#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +0300[diff] [blame]9
Mike Banonbb45f382020-02-13 15:45:05 +0000[diff] [blame]10void bootblock_mainboard_early_init(void)
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +0300[diff] [blame]11{
Kyösti Mälkki7a0aa9a2016-12-20 06:43:44 +0200[diff] [blame]12 /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
Mike Banonbb45f382020-02-13 15:45:05 +0000[diff] [blame]13 pm_write8(0xea, 0x1);
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +0300[diff] [blame]14
Kyösti Mälkki7a0aa9a2016-12-20 06:43:44 +0200[diff] [blame]15 fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
Kyösti Mälkki595ef3d2015-05-27 12:44:16 +0300[diff] [blame]16}