Angel Pons | 5f1bf2f | 2020-04-03 01:21:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 2 | |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 3 | #include <device/device.h> |
| 4 | #include <southbridge/amd/agesa/hudson/pci_devs.h> |
| 5 | #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> |
| 6 | #include <southbridge/amd/common/amd_pci_util.h> |
| 7 | #include <northbridge/amd/agesa/family16kb/pci_devs.h> |
| 8 | |
Kyösti Mälkki | e1e3289 | 2019-12-22 09:49:56 +0200 | [diff] [blame] | 9 | static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 10 | /* INTA# - INTH# */ |
| 11 | [0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, |
| 12 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 13 | [0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 14 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ |
| 15 | [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, |
| 16 | /* IMC INT0 - 5 */ |
| 17 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
Mike Banon | 834d8c2 | 2020-01-07 18:47:40 +0300 | [diff] [blame] | 18 | /* USB Devs 18/19/22 INTA-B */ |
| 19 | [0x30] = 0x05,0x04,0x05,0x04,0x05,0x04,0x1F,0x1F, |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 20 | /* RSVD, SATA */ |
| 21 | [0x40] = 0x1F, 0x07 |
| 22 | }; |
| 23 | |
Kyösti Mälkki | e1e3289 | 2019-12-22 09:49:56 +0200 | [diff] [blame] | 24 | static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 25 | /* INTA# - INTH# */ |
| 26 | [0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F, |
| 27 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 28 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 29 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ |
| 30 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F, |
| 31 | /* IMC INT0 - 5 */ |
| 32 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
Mike Banon | 834d8c2 | 2020-01-07 18:47:40 +0300 | [diff] [blame] | 33 | /* USB Devs 18/19/22 INTA-B */ |
| 34 | [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x1F,0x1F, |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 35 | /* RSVD, SATA */ |
| 36 | [0x40] = 0x1F, 0x13 |
| 37 | }; |
| 38 | |
| 39 | /* |
| 40 | * This table defines the index into the picr/intr_data |
| 41 | * tables for each device. Any enabled device and slot |
| 42 | * that uses hardware interrupts should have an entry |
| 43 | * in this table to define its index into the FCH |
| 44 | * PCI_INTR register 0xC00/0xC01. This index will define |
| 45 | * the interrupt that it should use. Putting PIRQ_A into |
| 46 | * the PIN A index for a device will tell that device to |
| 47 | * use PIC IRQ 10 if it uses PIN A for its hardware INT. |
| 48 | */ |
| 49 | static const struct pirq_struct mainboard_pirq_data[] = { |
| 50 | /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ |
| 51 | {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ |
| 52 | {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ |
| 53 | {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ |
| 54 | {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* Edge: 02.5 */ |
| 55 | {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ |
| 56 | {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ |
| 57 | {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ |
| 58 | {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ |
| 59 | {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ |
| 60 | {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ |
Mike Banon | 834d8c2 | 2020-01-07 18:47:40 +0300 | [diff] [blame] | 61 | {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ |
| 62 | {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 63 | {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ |
| 64 | }; |
| 65 | |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 66 | /* PIRQ Setup */ |
| 67 | static void pirq_setup(void) |
| 68 | { |
| 69 | pirq_data_ptr = mainboard_pirq_data; |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 70 | pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 71 | intr_data_ptr = mainboard_intr_data; |
| 72 | picr_data_ptr = mainboard_picr_data; |
| 73 | } |
| 74 | |
| 75 | /********************************************** |
| 76 | * enable the dedicated function in mainboard. |
| 77 | **********************************************/ |
Elyes HAOUAS | 02b05d1 | 2018-05-04 20:00:08 +0200 | [diff] [blame] | 78 | static void mainboard_enable(struct device *dev) |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 79 | { |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 80 | /* Initialize the PIRQ data structures for consumption */ |
| 81 | pirq_setup(); |
| 82 | } |
| 83 | |
| 84 | struct chip_operations mainboard_ops = { |
| 85 | .enable_dev = mainboard_enable, |
| 86 | }; |