Angel Pons | 5f1bf2f | 2020-04-03 01:21:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 2 | |
Mike Banon | 2bdc05d | 2019-12-19 11:16:07 +0300 | [diff] [blame] | 3 | #include <amdblocks/acpimmio.h> |
Elyes HAOUAS | 92f46aa | 2020-09-15 08:42:17 +0200 | [diff] [blame] | 4 | #include <arch/io.h> |
Mike Banon | 2bdc05d | 2019-12-19 11:16:07 +0300 | [diff] [blame] | 5 | #include <bootblock_common.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 6 | #include <device/pnp_ops.h> |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 7 | #include <superio/ite/common/ite.h> |
| 8 | #include <superio/ite/it8623e/it8623e.h> |
| 9 | |
Mike Banon | 16a70c3 | 2019-06-26 09:38:03 +0300 | [diff] [blame] | 10 | #if CONFIG_UART_FOR_CONSOLE == 0 |
| 11 | #define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP1) |
| 12 | #elif CONFIG_UART_FOR_CONSOLE == 1 |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 13 | #define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP2) |
Mike Banon | 16a70c3 | 2019-06-26 09:38:03 +0300 | [diff] [blame] | 14 | #else |
| 15 | #error "Invalid value for CONFIG_UART_FOR_CONSOLE" |
| 16 | #endif |
| 17 | |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 18 | #define GPIO_DEV PNP_DEV(0x2e, IT8623E_GPIO) |
| 19 | #define CLKIN_DEV PNP_DEV(0x2e, IT8623E_GPIO) |
| 20 | #define ENVC_DEV PNP_DEV(0x2e, IT8623E_EC) |
| 21 | |
| 22 | /* Sets up EC configuration as per vendor defaults */ |
| 23 | static void ite_evc_conf(pnp_devfn_t dev) |
| 24 | { |
| 25 | pnp_set_enable(dev, 0); |
| 26 | ite_reg_write(dev, 0x70, 0x00); |
| 27 | ite_reg_write(dev, 0xf0, 0x00); |
| 28 | ite_reg_write(dev, 0xf1, 0x00); |
| 29 | ite_reg_write(dev, 0xf2, 0x06); |
| 30 | ite_reg_write(dev, 0xf3, 0x00); |
| 31 | ite_reg_write(dev, 0xf4, 0x00); |
| 32 | ite_reg_write(dev, 0xf5, 0x36); |
| 33 | ite_reg_write(dev, 0xf6, 0x03); |
| 34 | ite_reg_write(dev, 0xf9, 0x48); |
| 35 | ite_reg_write(dev, 0xfa, 0x00); |
| 36 | ite_reg_write(dev, 0xfb, 0x10); |
| 37 | pnp_set_enable(dev, 1); |
| 38 | } |
| 39 | |
| 40 | /* |
| 41 | * Sets up GPIO configuration as per vendor defaults |
| 42 | * SIO defaults are unknown therefore all GPIO pins are configured |
| 43 | */ |
| 44 | static void ite_gpio_conf(pnp_devfn_t dev) |
| 45 | { |
| 46 | ite_reg_write(dev, 0x23, 0x08); |
| 47 | ite_reg_write(dev, 0x25, 0x10); |
| 48 | ite_reg_write(dev, 0x26, 0x00); |
| 49 | ite_reg_write(dev, 0x27, 0x80); |
| 50 | ite_reg_write(dev, 0x28, 0x45); |
| 51 | ite_reg_write(dev, 0x29, 0x00); |
| 52 | ite_reg_write(dev, 0x2a, 0x00); |
| 53 | ite_reg_write(dev, 0x2b, 0x48); |
| 54 | ite_reg_write(dev, 0x2c, 0x10); |
| 55 | ite_reg_write(dev, 0x2d, 0x80); |
| 56 | ite_reg_write(dev, 0x71, 0x00); |
| 57 | ite_reg_write(dev, 0x72, 0x00); |
| 58 | ite_reg_write(dev, 0x73, 0x38); |
| 59 | ite_reg_write(dev, 0x74, 0x00); |
| 60 | ite_reg_write(dev, 0xb0, 0x00); |
| 61 | ite_reg_write(dev, 0xb1, 0x00); |
| 62 | ite_reg_write(dev, 0xb2, 0x00); |
| 63 | ite_reg_write(dev, 0xb3, 0x00); |
| 64 | ite_reg_write(dev, 0xb4, 0x00); |
| 65 | ite_reg_write(dev, 0xb8, 0x00); |
| 66 | ite_reg_write(dev, 0xb9, 0x00); |
| 67 | ite_reg_write(dev, 0xba, 0x00); |
| 68 | ite_reg_write(dev, 0xbb, 0x00); |
| 69 | ite_reg_write(dev, 0xbc, 0x00); |
| 70 | ite_reg_write(dev, 0xbd, 0x00); |
| 71 | ite_reg_write(dev, 0xc0, 0x01); |
| 72 | ite_reg_write(dev, 0xc1, 0x00); |
| 73 | ite_reg_write(dev, 0xc2, 0x00); |
| 74 | ite_reg_write(dev, 0xc3, 0x00); |
| 75 | ite_reg_write(dev, 0xc4, 0x00); |
| 76 | ite_reg_write(dev, 0xc8, 0x01); |
| 77 | ite_reg_write(dev, 0xc9, 0x00); |
| 78 | ite_reg_write(dev, 0xca, 0x00); |
| 79 | ite_reg_write(dev, 0xcb, 0x00); |
| 80 | ite_reg_write(dev, 0xcc, 0x00); |
| 81 | ite_reg_write(dev, 0xcd, 0x20); |
| 82 | ite_reg_write(dev, 0xce, 0x00); |
| 83 | ite_reg_write(dev, 0xcf, 0x00); |
| 84 | ite_reg_write(dev, 0xe0, 0x00); |
| 85 | ite_reg_write(dev, 0xe1, 0x00); |
| 86 | ite_reg_write(dev, 0xe2, 0x00); |
| 87 | ite_reg_write(dev, 0xe3, 0x00); |
| 88 | ite_reg_write(dev, 0xe4, 0x00); |
| 89 | ite_reg_write(dev, 0xe9, 0x21); |
| 90 | ite_reg_write(dev, 0xf0, 0x00); |
| 91 | ite_reg_write(dev, 0xf1, 0x00); |
| 92 | ite_reg_write(dev, 0xf2, 0x00); |
| 93 | ite_reg_write(dev, 0xf3, 0x00); |
| 94 | ite_reg_write(dev, 0xf4, 0x00); |
| 95 | ite_reg_write(dev, 0xf5, 0x00); |
| 96 | ite_reg_write(dev, 0xf6, 0x00); |
| 97 | ite_reg_write(dev, 0xf7, 0x00); |
| 98 | ite_reg_write(dev, 0xf8, 0x00); |
| 99 | ite_reg_write(dev, 0xf9, 0x00); |
| 100 | ite_reg_write(dev, 0xfa, 0x00); |
| 101 | ite_reg_write(dev, 0xfb, 0x00); |
| 102 | } |
| 103 | |
Mike Banon | 2bdc05d | 2019-12-19 11:16:07 +0300 | [diff] [blame] | 104 | void bootblock_mainboard_early_init(void) |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 105 | { |
Arthur Heymans | a74504b | 2022-03-24 00:09:14 +0100 | [diff] [blame] | 106 | u32 i; |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 107 | |
| 108 | /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ |
Mike Banon | 2bdc05d | 2019-12-19 11:16:07 +0300 | [diff] [blame] | 109 | pm_write8(0xea, 0x1); |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 110 | |
| 111 | /* Configure ClkDrvStr1 settings */ |
Idwer Vollering | c2ce370 | 2020-01-05 01:44:25 +0100 | [diff] [blame] | 112 | misc_write32(0x24, 0x030800aa); |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 113 | |
| 114 | /* Configure MiscClkCntl1 settings */ |
Idwer Vollering | c2ce370 | 2020-01-05 01:44:25 +0100 | [diff] [blame] | 115 | misc_write32(0x40, 0x000c4050); |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 116 | |
Mike Banon | 2bdc05d | 2019-12-19 11:16:07 +0300 | [diff] [blame] | 117 | /* Configure SIO as made under vendor BIOS */ |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 118 | ite_gpio_conf(GPIO_DEV); |
| 119 | ite_evc_conf(ENVC_DEV); |
| 120 | |
Mike Banon | 2bdc05d | 2019-12-19 11:16:07 +0300 | [diff] [blame] | 121 | /* Enable serial output on it8623e */ |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 122 | ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); |
| 123 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 124 | ite_kill_watchdog(GPIO_DEV); |
| 125 | |
| 126 | /* |
| 127 | * On Larne, after LpcClkDrvSth is set, it needs some time to be stable, |
| 128 | * because of the buffer ICS551M |
| 129 | */ |
| 130 | for (i = 0; i < 200000; i++) |
Arthur Heymans | a74504b | 2022-03-24 00:09:14 +0100 | [diff] [blame] | 131 | inb(0xcd6); |
Gergely Kiss | 3dce9f0 | 2017-12-27 15:24:04 +0100 | [diff] [blame] | 132 | } |