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review.coreboot.org / coreboot / f9decbb0c720662d8e71fe221aef55b7ecf76196 / . / src / mainboard / amd / olivehill / irq_tables.c
blob: e5d576a34933d77540ba554f00d950827668fd44 [file] [log] [blame]
Angel Pons5c596802020-04-03 01:21:01 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]2
3#include <console/console.h>
Elyes Haouase378cdb2022-09-11 12:02:46 +0200[diff] [blame]4#include <commonlib/bsd/helpers.h>
Mike Banone1ebabe2020-02-14 16:12:45 +0000[diff] [blame]5#include <device/pci_def.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]6#include <string.h>
7#include <stdint.h>
8#include <arch/pirq_routing.h>
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]9
10static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
11 u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
12 u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
13 u8 slot, u8 rfu)
14{
15 pirq_info->bus = bus;
16 pirq_info->devfn = devfn;
17 pirq_info->irq[0].link = link0;
18 pirq_info->irq[0].bitmap = bitmap0;
19 pirq_info->irq[1].link = link1;
20 pirq_info->irq[1].bitmap = bitmap1;
21 pirq_info->irq[2].link = link2;
22 pirq_info->irq[2].bitmap = bitmap2;
23 pirq_info->irq[3].link = link3;
24 pirq_info->irq[3].bitmap = bitmap3;
25 pirq_info->slot = slot;
26 pirq_info->rfu = rfu;
27}
28
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]29unsigned long write_pirq_routing_table(unsigned long addr)
30{
31 struct irq_routing_table *pirq;
32 struct irq_info *pirq_info;
33 u32 slot_num;
34 u8 *v;
35
36 u8 sum = 0;
37 int i;
38
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]39 /* Align the table to be 16 byte aligned. */
Elyes Haouase378cdb2022-09-11 12:02:46 +0200[diff] [blame]40 addr = ALIGN_UP(addr, 16);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]41
Kyösti Mälkki9533d832014-06-26 05:30:54 +0300[diff] [blame]42 /* This table must be between 0xf0000 & 0x100000 */
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]43 printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
44
45 pirq = (void *)(addr);
Elyes Haouasa69311d2022-07-16 09:34:02 +0200[diff] [blame]46 v = (u8 *)(addr);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]47
48 pirq->signature = PIRQ_SIGNATURE;
49 pirq->version = PIRQ_VERSION;
50
Kyösti Mälkki0c797f12014-07-21 19:35:16 +0300[diff] [blame]51 pirq->rtr_bus = 0;
52 pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]53
54 pirq->exclusive_irqs = 0;
55
56 pirq->rtr_vendor = 0x1002;
57 pirq->rtr_device = 0x4384;
58
59 pirq->miniport_data = 0;
60
61 memset(pirq->rfu, 0, sizeof(pirq->rfu));
62
63 pirq_info = (void *)(&pirq->checksum + 1);
64 slot_num = 0;
65
Elyes Haouasb366bcb2022-09-11 13:19:16 +0200[diff] [blame]66 /* PCI bridge */
Kyösti Mälkki0c797f12014-07-21 19:35:16 +0300[diff] [blame]67 write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
Elyes Haouasb366bcb2022-09-11 13:19:16 +0200[diff] [blame]68 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]69 pirq_info++;
70
71 slot_num++;
72
73 pirq->size = 32 + 16 * slot_num;
74
75 for (i = 0; i < pirq->size; i++)
76 sum += v[i];
77
78 sum = pirq->checksum - sum;
79
Elyes Haouasb366bcb2022-09-11 13:19:16 +0200[diff] [blame]80 if (sum != pirq->checksum)
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]81 pirq->checksum = sum;
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]82
Elyes HAOUAS682b1662020-03-03 10:21:37 +0100[diff] [blame]83 printk(BIOS_INFO, "%s done.\n", __func__);
Siyuan Wang80cf7d52013-07-09 17:42:43 +0800[diff] [blame]84
85 return (unsigned long)pirq_info;
86}