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review.coreboot.org / coreboot / f95a11eff5217a396dc43288f0c547559b5d221a / . / src / soc / amd / glinda / chip.h
blob: d33261fa19001f9cc41c58fe979b34a67e639aaa [file] [log] [blame]
Martin Rothf95a11e2022-10-21 16:43:08 -0600[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3/* TODO: Update for Glinda */
4
5#ifndef GLINDA_CHIP_H
6#define GLINDA_CHIP_H
7
8#include <amdblocks/chip.h>
9#include <amdblocks/i2c.h>
10#include <gpio.h>
11#include <soc/i2c.h>
12#include <soc/southbridge.h>
13#include <drivers/i2c/designware/dw_i2c.h>
14#include <types.h>
15#include <vendorcode/amd/fsp/glinda/FspUsb.h>
16
17struct soc_amd_glinda_config {
18 struct soc_amd_common_config common_config;
19 u8 i2c_scl_reset;
20 struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
21 struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
22
23 /* Enable S0iX support */
24 bool s0ix_enable;
25
26 enum {
27 DOWNCORE_AUTO = 0,
28 DOWNCORE_1 = 1, /* Run with 1 physical core */
29 DOWNCORE_2 = 3, /* Run with 2 physical cores */
30 DOWNCORE_3 = 4, /* Run with 3 physical cores */
31 DOWNCORE_4 = 6, /* Run with 4 physical cores */
32 DOWNCORE_5 = 8, /* Run with 5 physical cores */
33 DOWNCORE_6 = 9, /* Run with 6 physical cores */
34 DOWNCORE_7 = 10, /* Run with 7 physical cores */
35 } downcore_mode;
36 bool disable_smt; /* disable second thread on all physical cores */
37
38 uint8_t stt_control;
39 uint8_t stt_pcb_sensor_count;
40 uint16_t stt_min_limit;
41 uint16_t stt_m1;
42 uint16_t stt_m2;
43 uint16_t stt_m3;
44 uint16_t stt_m4;
45 uint16_t stt_m5;
46 uint16_t stt_m6;
47 uint16_t stt_c_apu;
48 uint16_t stt_c_gpu;
49 uint16_t stt_c_hs2;
50 uint16_t stt_alpha_apu;
51 uint16_t stt_alpha_gpu;
52 uint16_t stt_alpha_hs2;
53 uint16_t stt_skin_temp_apu;
54 uint16_t stt_skin_temp_gpu;
55 uint16_t stt_skin_temp_hs2;
56 uint16_t stt_error_coeff;
57 uint16_t stt_error_rate_coefficient;
58
59 /* Default */
60 uint8_t stapm_boost;
61 uint32_t stapm_time_constant_s;
62 uint32_t apu_only_sppt_limit;
63 uint32_t sustained_power_limit_mW;
64 uint32_t fast_ppt_limit_mW;
65 uint32_t slow_ppt_limit_mW;
66 uint32_t slow_ppt_time_constant_s;
67 uint32_t thermctl_limit_degreeC;
68 uint32_t vrm_current_limit_mA;
69 uint32_t vrm_maximum_current_limit_mA;
70 uint32_t vrm_soc_current_limit_mA;
71 /* Throttle (e.g., Low/No Battery) */
72 uint32_t vrm_current_limit_throttle_mA;
73 uint32_t vrm_maximum_current_limit_throttle_mA;
74 uint32_t vrm_soc_current_limit_throttle_mA;
75
76 uint8_t smartshift_enable;
77
78 uint8_t system_configuration;
79
80 uint8_t cppc_ctrl;
81 uint8_t cppc_perf_limit_max_range;
82 uint8_t cppc_perf_limit_min_range;
83 uint8_t cppc_epp_max_range;
84 uint8_t cppc_epp_min_range;
85 uint8_t cppc_preferred_cores;
86
87 /* telemetry settings */
88 uint32_t telemetry_vddcrvddfull_scale_current_mA;
89 uint32_t telemetry_vddcrvddoffset;
90 uint32_t telemetry_vddcrsocfull_scale_current_mA;
91 uint32_t telemetry_vddcrsocoffset;
92
93 /* The array index is the general purpose PCIe clock output number. Values in here
94 aren't the values written to the register to have the default to be always on. */
95 enum {
96 GPP_CLK_ON, /* GPP clock always on; default */
97 GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
98 GPP_CLK_OFF, /* GPP clk off */
99 } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
100
101 /* performance policy for the PCIe links: power consumption vs. link speed */
102 enum {
103 DXIO_PSPP_DISABLED = 0,
104 DXIO_PSPP_PERFORMANCE,
105 DXIO_PSPP_BALANCED,
106 DXIO_PSPP_POWERSAVE,
107 } pspp_policy;
108
109 uint8_t usb_phy_custom;
110 struct usb_phy_config usb_phy;
111};
112
113#endif /* GLINDA_CHIP_H */