Angel Pons | 5c59680 | 2020-04-03 01:21:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Richard Spiegel | 31d04e6 | 2019-07-02 17:13:19 -0700 | [diff] [blame] | 2 | |
| 3 | #include <amdblocks/agesawrapper.h> |
| 4 | #include <amdblocks/BiosCallOuts.h> |
| 5 | #include <soc/southbridge.h> |
Richard Spiegel | 31d04e6 | 2019-07-02 17:13:19 -0700 | [diff] [blame] | 6 | #include "gpio.h" |
| 7 | |
| 8 | /* |
| 9 | * As a rule of thumb, GPIO pins used by coreboot should be initialized at |
| 10 | * bootblock while GPIO pins used only by the OS should be initialized at |
| 11 | * ramstage. |
| 12 | */ |
| 13 | static const struct soc_amd_gpio gpio_set_stage_reset[] = { |
Elyes HAOUAS | d254fc4 | 2020-02-22 11:38:05 +0100 | [diff] [blame] | 14 | /* GFX presence detect */ |
Richard Spiegel | 31d04e6 | 2019-07-02 17:13:19 -0700 | [diff] [blame] | 15 | PAD_GPI(GPIO_9, PULL_DOWN), |
| 16 | /* VDDP_VCTRL */ |
| 17 | PAD_GPO(GPIO_40, HIGH), |
| 18 | /* PC SPKR */ |
| 19 | PAD_NF(GPIO_91, SPKR, PULL_NONE), |
| 20 | }; |
| 21 | |
| 22 | static const struct soc_amd_gpio gpio_set_stage_ram[] = { |
Angel Pons | 77330e5 | 2021-02-19 11:01:33 +0100 | [diff] [blame] | 23 | #if CONFIG(HAVE_ACPI_RESUME) |
Richard Spiegel | 31d04e6 | 2019-07-02 17:13:19 -0700 | [diff] [blame] | 24 | /* PCIE_WAKE - default, do not program */ |
| 25 | |
| 26 | /* DEVSLP1 */ |
| 27 | PAD_NF(GPIO_70, DEVSLP1, PULL_UP), |
| 28 | /* WLAND */ |
Richard Spiegel | 31d04e6 | 2019-07-02 17:13:19 -0700 | [diff] [blame] | 29 | PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3), |
| 30 | #else |
Felix Held | f8e440c | 2021-03-24 00:17:35 +0100 | [diff] [blame^] | 31 | /* PCIE_WAKE, SCI */ |
| 32 | PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW), |
Richard Spiegel | 31d04e6 | 2019-07-02 17:13:19 -0700 | [diff] [blame] | 33 | /* DEVSLP1 - default as GPIO, do not program */ |
| 34 | |
| 35 | /* WLAND - default as GPIO, do not program */ |
| 36 | |
Angel Pons | 77330e5 | 2021-02-19 11:01:33 +0100 | [diff] [blame] | 37 | #endif /* HAVE_ACPI_RESUME */ |
Richard Spiegel | 31d04e6 | 2019-07-02 17:13:19 -0700 | [diff] [blame] | 38 | /* BLINK - reselect GPIO OUTPUT HIGH to force BLINK */ |
| 39 | PAD_GPO(GPIO_11, HIGH), |
| 40 | }; |
| 41 | |
| 42 | const struct soc_amd_gpio *early_gpio_table(size_t *size) |
| 43 | { |
| 44 | *size = ARRAY_SIZE(gpio_set_stage_reset); |
| 45 | return gpio_set_stage_reset; |
| 46 | } |
| 47 | |
| 48 | const struct soc_amd_gpio *gpio_table(size_t *size) |
| 49 | { |
| 50 | *size = ARRAY_SIZE(gpio_set_stage_ram); |
| 51 | return gpio_set_stage_ram; |
| 52 | } |