Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2 | |
Angel Pons | 3447db5 | 2020-09-14 18:09:46 +0200 | [diff] [blame] | 3 | #ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__ |
| 4 | #define __SANDYBRIDGE_REGISTERS_MCHBAR_H__ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 5 | |
| 6 | /* |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 7 | * ### IOSAV memory controller interface poking state machine notes ### |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 8 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 9 | * IOSAV brings batch processing to memory training algorithms. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 10 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 11 | * The hardware is capable of executing a sequence of DRAM commands, |
| 12 | * which can be composed of up to four sub-sequences. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 13 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 14 | * A sub-sequence (from now on, subseq) consists of executing the same |
| 15 | * DRAM command for a configurable number of times, with adjustable |
| 16 | * delay between the commands, as well as an address auto-increment |
| 17 | * value, which is added after a given number of command executions. |
| 18 | * |
| 19 | * There are four groups of registers in MCHBAR, one for each subseq. |
| 20 | * When firing up IOSAV, one needs to specify the number of subseqs it |
| 21 | * should use. |
| 22 | * |
| 23 | * The macros for these registers can take some integer parameters. |
| 24 | * Valid values are: |
| 25 | * channel: 0..1 or 3 to broadcast to all channels. |
| 26 | * index: 0..3 |
| 27 | * lane: 0..8 |
| 28 | * |
| 29 | * These ranges are inclusive: both upper and lower bounds are valid. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 30 | * |
| 31 | * |
| 32 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 33 | * ### Register descriptions ### |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 34 | * |
| 35 | * IOSAV_n_SP_CMD_ADDR_ch(channel, index) |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 36 | * Configures the row/column, bank and rank addresses. When a subseq |
| 37 | * begins to execute, the address fields define the address of the |
| 38 | * first command in the subseq. The address is updated after each |
| 39 | * command as configured in the "IOSAV_n_ADDR_UPDATE" registers, |
| 40 | * and the updated address is then written back into this register. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 41 | * |
| 42 | * Bitfields: |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 43 | * [15..0] Row / Column Address. Defines the ADDR pins when |
| 44 | * issuing a DRAM command. |
| 45 | * |
| 46 | * [18..16] The number of valid row bits is this value, plus 10. |
| 47 | * Note: Value 1 is not implemented. |
| 48 | * Value 7 is unsupported, and thus reserved. |
| 49 | * |
| 50 | * [22..20] Bank select. |
| 51 | * [25..24] Rank select. It is later referred to as "ranksel". |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 52 | * |
| 53 | * IOSAV_n_ADDR_UPDATE_ch(channel, index) |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 54 | * How the address updates after executing a command in the subseq. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 55 | * |
| 56 | * Bitfields: |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 57 | * [0] Increment row/column address by 1. |
| 58 | * [1] Increment row/column address by 8. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 59 | * [2] Increment bank select by 1. |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 60 | * [4..3] Increment rank select by 1, 2 or 3. |
| 61 | * [9..5] Known as "addr_wrap", it limits the address increments. |
| 62 | * Address bits will wrap around the [addr_wrap..0] range. |
| 63 | * |
| 64 | * [11..10] LFSR update: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 65 | * 00: Do not use the LFSR function. |
| 66 | * 01: Undefined, treat as Reserved. |
| 67 | * 10: Apply LFSR on the [addr_wrap..0] bit range. |
| 68 | * 11: Apply LFSR on the [addr_wrap..3] bit range. |
| 69 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 70 | * [15..12] Update rate. The number of command runs between address updates. For example: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 71 | * 0: Update every command run. |
| 72 | * 1: Update every second command run. That is, half of the command rate. |
| 73 | * N: Update after N command runs without updates. |
| 74 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 75 | * [17..16] LFSR behavior on the deselect cycles (when no subseq command is issued): |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 76 | * 0: No change w.r.t. the last issued command. |
| 77 | * 1: LFSR XORs with address & command (excluding CS), but does not update. |
| 78 | * 2: LFSR XORs with address & command (excluding CS), and updates. |
| 79 | * |
| 80 | * IOSAV_n_SP_CMD_CTRL_ch(channel, index) |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 81 | * Configures how the DRAM command lines will be driven in each |
| 82 | * command of the subseq. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 83 | * |
| 84 | * Bitfields: |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 85 | * [0] !RAS signal (as driven electrically). |
| 86 | * [1] !CAS signal (as driven electrically). |
| 87 | * [2] !WE signal (as driven electrically). |
| 88 | * |
| 89 | * [4] CKE, for DIMM 0 Rank 0. |
| 90 | * [5] CKE, for DIMM 0 Rank 1. |
| 91 | * [6] CKE, for DIMM 1 Rank 0. |
| 92 | * [7] CKE, for DIMM 1 Rank 1. |
| 93 | * [11..8] ODT, per DIMM & Rank (same encoding as CKE). |
| 94 | * [15..12] Chip select, per DIMM and Rank. It works as follows: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 95 | * |
| 96 | * entity CS_BLOCK is |
| 97 | * port ( |
Angel Pons | 394ac5b | 2020-03-23 00:35:14 +0100 | [diff] [blame] | 98 | * MODE : in std_logic; -- Mode select at [16] |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 99 | * RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 100 | * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [15..12] |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 101 | * CS_Q : out std_logic_vector(0 to 3) -- CS signals |
| 102 | * ); |
| 103 | * end entity CS_BLOCK; |
| 104 | * |
| 105 | * architecture RTL of CS_BLOCK is |
| 106 | * begin |
| 107 | * if MODE = '1' then |
| 108 | * CS_Q <= not RANKSEL and CS_CTL; |
| 109 | * else |
| 110 | * CS_Q <= CS_CTL; |
| 111 | * end if; |
| 112 | * end architecture RTL; |
| 113 | * |
Angel Pons | 394ac5b | 2020-03-23 00:35:14 +0100 | [diff] [blame] | 114 | * [16] Chip Select mode control. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 115 | * [17] Auto Precharge. Only valid when using 10 row bits! |
| 116 | * |
| 117 | * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 118 | * The parameters of the subseq: number of repetitions of the command, |
| 119 | * the delay between command executions, wait cycles after completing |
| 120 | * this subseq and before the next one, and the data direction of the |
| 121 | * command (read, write, neither, or both read and write). |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 122 | * |
| 123 | * Bitfields: |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 124 | * [8..0] Number of repetitions of the DRAM command in this subseq. |
| 125 | * [14..10] Number of DCLK cycles to wait between two successive DRAM commands. |
| 126 | * [24..16] Number of DCLK cycles to idle after this subseq and before the next subseq. |
| 127 | * [27..26] The direction of the data: |
| 128 | * 00: None (non-data command) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 129 | * 01: Read |
| 130 | * 10: Write |
| 131 | * 11: Read & Write |
| 132 | * |
| 133 | * IOSAV_n_ADDRESS_LFSR_ch(channel, index) |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 134 | * 23-bit LFSR state. It is written into the LFSR when the subseq is |
| 135 | * loaded, and then read back from the LFSR when the subseq is done. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 136 | * |
| 137 | * Bitfields: |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 138 | * [22..0] LFSR state. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 139 | * |
| 140 | * IOSAV_SEQ_CTL_ch(channel) |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 141 | * IOSAV full sequence settings: number of subseqs, iterations, stop |
| 142 | * on error, maintenance cycles... |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 143 | * |
| 144 | * Bitfields: |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 145 | * [7..0] Number of full sequence executions. When this field becomes non-zero, then the |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 146 | * sequence starts running immediately. This value is decremented after completing |
| 147 | * a full sequence iteration. When it is zero, the sequence is done. No decrement |
| 148 | * is done if this field is set to 0xff. This is the "infinite repeat" mode, and |
| 149 | * it is manually aborted by clearing this field. |
| 150 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 151 | * [16..8] Number of wait cycles after each sequence iteration. This wait's purpose is to |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 152 | * allow performing maintenance in infinite loops. When non-zero, RCOMP, refresh |
| 153 | * and ZQXS operations can take place. |
| 154 | * |
| 155 | * [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs. |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 156 | * [19..18] Number of subseqs. The programmed value is the index of the last valid subseq. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 157 | * [20] If set, keep refresh disabled until the next sequence execution. |
| 158 | * DANGER: Refresh must be re-enabled within the (9 * tREFI) period! |
| 159 | * |
| 160 | * [22] If set, sequence execution will not prevent refresh. This cannot be set when |
| 161 | * bit [20] is also set, or was set on the previous sequence. This bit exists so |
| 162 | * that the sequence machine can be used as a timer without affecting the memory. |
| 163 | * |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 164 | * [23] If set, an output pin is asserted on the first detected error. This output can |
| 165 | * be used as a trigger for an oscilloscope or a logic analyzer, which is pretty |
| 166 | * useful for debugging (if you have the equipment and know where this pin is). |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 167 | * |
| 168 | * IOSAV_DATA_CTL_ch(channel) |
| 169 | * Data-related controls in IOSAV mode. |
| 170 | * |
| 171 | * Bitfields: |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 172 | * [7..0] WDB (Write Data Buffer) pattern length: [7..0] = (length / 8) - 1; |
| 173 | * [15..8] WDB read pointer. Points at the data used for IOSAV write transactions. |
| 174 | * [23..16] Comparison pointer. Used to compare data from IOSAV read transactions. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 175 | * [24] If set, increment pointers only when micro-breakpoint is active. |
| 176 | * |
| 177 | * IOSAV_STATUS_ch(channel) |
Angel Pons | fb6606b | 2020-05-01 22:41:13 +0200 | [diff] [blame] | 178 | * Provides feedback on the state of the IOSAV sequence machine. |
| 179 | * Should be polled after submitting an IOSAV sequence for execution. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 180 | * |
| 181 | * Bitfields: |
| 182 | * [0] IDLE: IOSAV is sleeping. |
| 183 | * [1] BUSY: IOSAV is running a sequence. |
| 184 | * [2] DONE: IOSAV has completed a sequence. |
| 185 | * [3] ERROR: IOSAV detected an error and stopped on it, when using Stop-on-error. |
| 186 | * [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted. |
| 187 | * [5] RCOMP: RComp failure. Unused, consider Reserved. |
| 188 | * [6] Cleared with a new sequence, and set when done and refresh counter is drained. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 189 | */ |
| 190 | |
Angel Pons | 66b0c5e | 2020-08-11 20:21:27 +0200 | [diff] [blame] | 191 | /* |
| 192 | * ### ECC error injection registers ### |
| 193 | * |
| 194 | * ECC_INJECT_COUNT_ch(channel) |
| 195 | * Defines the count of write chunks (64-bit data packets) until the |
| 196 | * next ECC error injection. This only seems to apply if the ECC_inject |
| 197 | * field in the ECC_DFT register is 110 or 111. The count is of chunks |
| 198 | * in order to allow creating ECC errors on different 64-bit chunks. |
| 199 | * |
| 200 | * Note that this register is only 32-bit. |
| 201 | * |
| 202 | * ECC_DFT_ch(channel) |
| 203 | * Control ECC DFT features, such as ECC4ANA, error inject, etc. |
| 204 | * |
| 205 | * Bitfields: |
| 206 | * [7..0] 8-bit fill value for ECC4ANA function. |
| 207 | * [9..8] ECC4ANA trigger: |
| 208 | * 00: ECC4ANA is off, no trigger. |
| 209 | * 10: Trigger on single-bit or uncorrectable error. |
| 210 | * 11: Trigger on uncorrectable error. |
| 211 | * |
| 212 | * [10] ECC4ANA byte select: |
| 213 | * 0: Byte 0 |
| 214 | * 1: Byte 7 |
| 215 | * |
| 216 | * [13..11] ECC_inject: ECC error inject options: |
| 217 | * 000: No ECC error injection. |
| 218 | * 100: Inject non-recoverable ECC error on GODLAT indication. |
| 219 | * 101: Inject non-recoverable ECC error on ECC_INJ_ADDR_COMPARE reg match. |
| 220 | * 110: Reserved. |
| 221 | * 111: Inject non-recoverable ECC error on ECC error insertion counter. |
| 222 | * |
| 223 | * [14] ECC correction disable: when set, the MC reports every error as uncorrectable. |
| 224 | * [15] Mark incoming transactions for ECC4ANA based on ECC_INJ_ADDR_COMPARE reg match. |
| 225 | * |
| 226 | * SCHED_SECOND_CBIT |
| 227 | * More chicken bits! |
| 228 | * |
| 229 | * Bitfields: |
| 230 | * |
| 231 | * [11] Disable ECC4ANA Bug Fix. WARNING: This register is only for Ivy Bridge! |
| 232 | * |
| 233 | * MAD_DIMM_ch(channel) |
| 234 | * Channel characteristics: number of DIMMs, number of ranks, size, |
| 235 | * (enhanced) interleave options and ECC options. |
| 236 | * |
| 237 | * Bitfields: |
| 238 | * [7..0] DIMM A size in 256 MiB units. |
| 239 | * [15..8] DIMM B size in 256 MiB units. |
| 240 | * [16] Select which of the DIMMs is DIMM A, should be the larger DIMM. |
| 241 | * [17] DIMM A number of ranks. (0 => Single Rank, 1 => Dual Rank) |
| 242 | * [18] DIMM B number of ranks. |
| 243 | * [19] DIMM A DDR chip width. (0 => x8, 1 => x16) |
| 244 | * [20] DIMM B DDR chip width. |
| 245 | * [21] Enable Rank Interleave. |
| 246 | * [22] Enable Enhanced Rank Interleave. |
| 247 | * [25..24] ECC control: |
| 248 | * 00: No ECC. |
| 249 | * 01: ECC is active in IO, ECC logic is not active. Used with IOSAV training. |
| 250 | * 10: ECC is disabled in IO, but ECC logic is enabled. Used with ECC4ANA mode. |
| 251 | * 11: ECC active in both IO and ECC logic. |
| 252 | * |
| 253 | * ECC_INJ_ADDR_COMPARE, ECC_INJ_ADDR_MASK |
| 254 | * |
| 255 | * Address compare for ECC error inject. Error injection is issued when |
| 256 | * ECC_INJ_ADDR_COMPARE[31..0] = ADDR[37..6] & ECC_INJ_ADDR_MASK[31..0]. |
| 257 | * |
| 258 | * MC_LOCK |
| 259 | * |
| 260 | * Locking of MC registers. Each bit locks one group of registers. |
| 261 | * |
| 262 | * Bitfields: |
| 263 | * [0] Lock all the address map registers. |
| 264 | * [1] Lock all the MC configuration registers including MCIO. |
| 265 | * [2] Lock all IOSAV and Init registers. |
| 266 | * [3] Lock all power management registers. |
| 267 | * [7] Lock all DFT features. |
| 268 | */ |
| 269 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 270 | /* Indexed register helper macros */ |
| 271 | #define Gz(r, z) ((r) + ((z) << 8)) |
| 272 | #define Ly(r, y) ((r) + ((y) << 2)) |
| 273 | #define Cx(r, x) ((r) + ((x) << 10)) |
| 274 | #define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) |
| 275 | #define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) |
| 276 | |
| 277 | /* Byte lane training register base addresses */ |
| 278 | #define LANEBASE_B0 0x0000 |
| 279 | #define LANEBASE_B1 0x0200 |
| 280 | #define LANEBASE_B2 0x0400 |
| 281 | #define LANEBASE_B3 0x0600 |
| 282 | #define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ |
| 283 | #define LANEBASE_B4 0x1000 |
| 284 | #define LANEBASE_B5 0x1200 |
| 285 | #define LANEBASE_B6 0x1400 |
| 286 | #define LANEBASE_B7 0x1600 |
| 287 | |
| 288 | /* Byte lane register offsets */ |
| 289 | #define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ |
| 290 | #define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ |
| 291 | #define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ |
| 292 | #define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ |
| 293 | #define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ |
| 294 | |
| 295 | /* Register definitions */ |
| 296 | #define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ |
| 297 | #define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ |
| 298 | #define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch) /* PI coding for DDR CLK pins */ |
| 299 | #define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch) /* Logic delay of 1 QCLK in CLK slice */ |
| 300 | #define GDDLLFUSE_ch(ch) Gz(0x0c20, ch) /* Used for fuse download to the DLLs */ |
| 301 | #define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch) /* Debug MUX control */ |
| 302 | |
| 303 | #define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch) /* Debug MUX control */ |
| 304 | |
| 305 | #define CRCOMPOFST1_ch(ch) Gz(0x1810, ch) /* DQ, CTL and CLK Offset values */ |
| 306 | |
| 307 | #define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch) /* Data training mode control */ |
| 308 | #define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch) /* Training results according to PI */ |
| 309 | #define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch) |
| 310 | |
| 311 | #define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch) /* Indicates which rank is populated */ |
| 312 | #define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch) /* COMP values register */ |
| 313 | #define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch) /* COMP values register */ |
| 314 | #define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch) /* Command and control PI coding */ |
| 315 | |
| 316 | #define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ |
| 317 | #define GDCRDATACOMP 0x340c /* COMP values register */ |
| 318 | |
| 319 | #define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ |
| 320 | |
Angel Pons | 8e66124 | 2020-05-02 19:02:53 +0200 | [diff] [blame] | 321 | /* |
| 322 | * The register bank that would correspond to Channel 3 are actually "broadcast" registers. |
| 323 | * They can be used to write values to all channels. Use this macro instead of a literal '3'. |
| 324 | */ |
| 325 | #define BROADCAST_CH 3 |
| 326 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 327 | /* MC per-channel registers */ |
| 328 | #define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ |
| 329 | #define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ |
| 330 | #define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ |
| 331 | #define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ |
Angel Pons | 5fd50b6 | 2020-03-22 13:00:44 +0100 | [diff] [blame] | 332 | |
| 333 | /** WARNING: Only applies to Ivy Bridge! */ |
| 334 | #define TC_DTP_ch(ch) Cx(0x4014, ch) /** Timings: Debug parameters */ |
| 335 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 336 | #define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ |
| 337 | #define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ |
| 338 | #define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ |
| 339 | #define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch) /* IO Latency Configuration */ |
| 340 | #define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch) /* Scrambling seed 1 */ |
| 341 | #define SCRAMBLING_SEED_2_LO_ch(ch) Cx(0x4038, ch) /* Scrambling seed 2 low */ |
| 342 | #define SCRAMBLING_SEED_2_HI_ch(ch) Cx(0x403c, ch) /* Scrambling seed 2 high */ |
| 343 | |
| 344 | /* IOSAV Bytelane Bit-wise error */ |
| 345 | #define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y) |
| 346 | |
| 347 | /* IOSAV Bytelane Bit-wise compare mask */ |
| 348 | #define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y) |
| 349 | |
| 350 | /* |
| 351 | * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. |
| 352 | * Different counters for transactions that are issued on the ring agents (core or GT) and |
| 353 | * transactions issued in the SA. |
| 354 | */ |
| 355 | #define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch) |
| 356 | #define SC_PCIT_ch(ch) Cx(0x40ac, ch) /* Page-close idle timer setup - 8 bits */ |
| 357 | #define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch) /* Power-down (CKE-off) operation config */ |
| 358 | #define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch) /* ECC error injection count */ |
| 359 | #define ECC_DFT_ch(ch) Cx(0x40b8, ch) /* ECC DFT features (ECC4ANA, error inject) */ |
| 360 | #define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch) /* Extra WR delay to overcome WR-flyby issue */ |
| 361 | |
| 362 | #define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ |
| 363 | |
| 364 | /* IOSAV sub-sequence control registers */ |
| 365 | #define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ |
| 366 | #define IOSAV_n_ADDR_UPDATE_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ |
| 367 | #define IOSAV_n_SP_CMD_CTRL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ |
| 368 | #define IOSAV_n_SUBSEQ_CTRL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ |
| 369 | #define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ |
| 370 | |
| 371 | #define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ |
| 372 | #define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ |
| 373 | #define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch) /* Data control in IOSAV mode */ |
| 374 | #define IOSAV_STATUS_ch(ch) Cx(0x428c, ch) /* State of the IOSAV sequence machine */ |
| 375 | #define TC_ZQCAL_ch(ch) Cx(0x4290, ch) /* ZQCAL control register */ |
| 376 | #define TC_RFP_ch(ch) Cx(0x4294, ch) /* Refresh Parameters */ |
| 377 | #define TC_RFTP_ch(ch) Cx(0x4298, ch) /* Refresh Timing Parameters */ |
| 378 | #define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch) /* MR2 shadow - copy of DDR configuration */ |
| 379 | #define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch) /* IOSAV mode control */ |
| 380 | #define TC_SRFTP_ch(ch) Cx(0x42a4, ch) /* Self-refresh timing parameters */ |
| 381 | #define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch) /* Data vector count of the first error */ |
| 382 | #define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch) /* IOSAV data check masking */ |
| 383 | |
| 384 | #define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y) /* Per-byte 16-bit error count */ |
| 385 | #define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch) /* Global 16-bit error count */ |
| 386 | |
| 387 | /** WARNING: Only applies to Ivy Bridge! */ |
| 388 | #define IOSAV_BYTE_SERROR_ch(ch) Cx(0x4368, ch) /** Byte-Wise Sticky Error */ |
| 389 | #define IOSAV_BYTE_SERROR_C_ch(ch) Cx(0x436c, ch) /** Byte-Wise Sticky Error Clear */ |
| 390 | |
| 391 | #define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch) /* Thermal mode configuration */ |
| 392 | #define PM_CMD_PWR_ch(ch) Cx(0x4384, ch) /* Power contribution of commands */ |
| 393 | #define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch) /* Bandwidth throttling on overtemp */ |
| 394 | #define SC_WDBWM_ch(ch) Cx(0x438c, ch) /* Watermarks and starvation counter */ |
| 395 | |
| 396 | /* MC Channel Broadcast registers */ |
| 397 | #define TC_DBP 0x4c00 /* Timings: BIN */ |
| 398 | #define TC_RAP 0x4c04 /* Timings: Regular access */ |
| 399 | #define TC_RWP 0x4c08 /* Timings: Read / Write */ |
| 400 | #define TC_OTHP 0x4c0c /* Timings: Other parameters */ |
Angel Pons | 5fd50b6 | 2020-03-22 13:00:44 +0100 | [diff] [blame] | 401 | |
| 402 | /** WARNING: Only applies to Ivy Bridge! */ |
| 403 | #define TC_DTP 0x4c14 /** Timings: Debug parameters */ |
| 404 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 405 | #define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ |
| 406 | #define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ |
| 407 | #define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ |
| 408 | #define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ |
| 409 | #define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ |
| 410 | #define SCRAMBLING_SEED_2_LO 0x4c38 /* Scrambling seed 2 low */ |
| 411 | #define SCRAMBLING_SEED_2_HI 0x4c3c /* Scrambling seed 2 high */ |
| 412 | |
| 413 | #define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ |
| 414 | #define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ |
| 415 | |
| 416 | /* |
| 417 | * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. |
| 418 | * Different counters for transactions that are issued on the ring agents (core or GT) and |
| 419 | * transactions issued in the SA. |
| 420 | */ |
| 421 | #define SC_PR_CNT_CONFIG 0x4ca8 |
| 422 | #define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ |
| 423 | #define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ |
| 424 | #define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ |
| 425 | #define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ |
| 426 | #define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ |
| 427 | |
| 428 | /** Opportunistic reads configuration during write-major-mode (WMM) */ |
| 429 | #define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ |
| 430 | |
| 431 | #define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ |
| 432 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 433 | #define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ |
| 434 | #define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ |
| 435 | #define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ |
| 436 | #define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ |
| 437 | #define TC_ZQCAL 0x4e90 /* ZQCAL control register */ |
| 438 | #define TC_RFP 0x4e94 /* Refresh Parameters */ |
| 439 | #define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ |
| 440 | #define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ |
| 441 | #define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ |
| 442 | #define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ |
| 443 | |
| 444 | /** |
| 445 | * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this |
| 446 | * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. |
| 447 | */ |
| 448 | #define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ |
| 449 | |
| 450 | #define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ |
| 451 | #define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ |
| 452 | |
| 453 | #define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ |
| 454 | #define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ |
| 455 | |
| 456 | /** WARNING: Only applies to Ivy Bridge! */ |
| 457 | #define IOSAV_BYTE_SERROR 0x4f68 /** Byte-Wise Sticky Error */ |
| 458 | #define IOSAV_BYTE_SERROR_C 0x4f6c /** Byte-Wise Sticky Error Clear */ |
| 459 | |
| 460 | #define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ |
| 461 | #define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ |
| 462 | #define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ |
| 463 | #define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ |
| 464 | |
| 465 | /* No, there's no need to get mad about the Memory Address Decoder */ |
| 466 | #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ |
| 467 | #define MAD_DIMM(ch) Ly(0x5004, ch) /* Channel characteristics */ |
| 468 | #define MAD_DIMM_CH0 MAD_DIMM(0) /* Channel 0 is at 0x5004 */ |
| 469 | #define MAD_DIMM_CH1 MAD_DIMM(1) /* Channel 1 is at 0x5008 */ |
| 470 | #define MAD_DIMM_CH2 MAD_DIMM(2) /* Channel 2 is at 0x500c (unused on SNB) */ |
| 471 | |
| 472 | #define MAD_ZR 0x5014 /* Address Decode Zones */ |
| 473 | #define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ |
| 474 | #define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ |
| 475 | |
| 476 | #define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ |
| 477 | |
| 478 | #define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ |
| 479 | #define MRC_REVISION 0x5034 /* MRC Revision */ |
| 480 | #define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ |
| 481 | #define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ |
| 482 | |
Angel Pons | 66b0c5e | 2020-08-11 20:21:27 +0200 | [diff] [blame] | 483 | #define ECC_INJ_ADDR_COMPARE 0x5090 /* Address compare for ECC error inject */ |
| 484 | #define ECC_INJ_ADDR_MASK 0x5094 /* Address mask for ECC error inject */ |
| 485 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 486 | #define MC_LOCK 0x50fc /* Memory Controlller Lock register */ |
| 487 | |
| 488 | #define GFXVTBAR 0x5400 /* Base address for IGD */ |
| 489 | #define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ |
| 490 | |
| 491 | /* On Ivy Bridge, this is used to enable Power Aware Interrupt Routing */ |
| 492 | #define INTRDIRCTL 0x5418 /* Interrupt Redirection Control */ |
| 493 | |
| 494 | /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ |
| 495 | #define PAVP_MSG 0x5500 |
| 496 | |
| 497 | #define MEM_TRML_ESTIMATION_CONFIG 0x5880 |
| 498 | #define MEM_TRML_THRESHOLDS_CONFIG 0x5888 |
| 499 | #define MEM_TRML_INTERRUPT 0x58a8 |
| 500 | |
| 501 | /* Some power MSRs are also represented in MCHBAR */ |
| 502 | #define MCH_PKG_POWER_LIMIT_LO 0x59a0 /* Turbo Power Limit 1 parameters */ |
| 503 | #define MCH_PKG_POWER_LIMIT_HI 0x59a4 /* Turbo Power Limit 2 parameters */ |
| 504 | |
| 505 | #define SSKPD 0x5d10 /* 64-bit scratchpad register */ |
| 506 | #define SSKPD_HI 0x5d14 |
| 507 | #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ |
| 508 | |
| 509 | /* PCODE will sample SAPM-related registers at the end of Phase 4. */ |
| 510 | #define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ |
| 511 | #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ |
| 512 | #define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ |
| 513 | #define M_COMP 0x5f08 /* Memory COMP control */ |
| 514 | #define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ |
| 515 | |
| 516 | /* WARNING: Only applies to Sandy Bridge! */ |
| 517 | #define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ |
| 518 | |
| 519 | /** WARNING: Only applies to Ivy Bridge! */ |
| 520 | #define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ |
| 521 | #define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ |
| 522 | |
| 523 | /* Finalize registers. The names come from Haswell, as the finalize sequence is the same. */ |
| 524 | #define HDAUDRID 0x6008 |
| 525 | #define UMAGFXCTL 0x6020 |
| 526 | #define VDMBDFBARKVM 0x6030 |
| 527 | #define VDMBDFBARPAVP 0x6034 |
| 528 | #define VTDTRKLCK 0x63fc |
| 529 | #define REQLIM 0x6800 |
| 530 | #define DMIVCLIM 0x7000 |
| 531 | #define PEGCTL 0x7010 /* Bit 0 is PCIPWRGAT (clock gate all PEG controllers) */ |
| 532 | #define CRDTCTL3 0x740c /* Minimum completion credits for PCIe/DMI */ |
| 533 | #define CRDTCTL4 0x7410 /* Read Return Tracker credits */ |
| 534 | #define CRDTLCK 0x77fc |
| 535 | |
Angel Pons | 3447db5 | 2020-09-14 18:09:46 +0200 | [diff] [blame] | 536 | #endif /* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */ |