Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 4 | #include <device/device.h> |
| 5 | #include <device/dram/lpddr4.h> |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 6 | #include <memory_info.h> |
| 7 | #include <smbios.h> |
| 8 | #include <types.h> |
| 9 | |
| 10 | enum lpddr4_speed_grade { |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 11 | LPDDR4_1333, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 12 | LPDDR4_1600, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 13 | LPDDR4_1866, |
| 14 | LPDDR4_2133, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 15 | LPDDR4_2400, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 16 | LPDDR4_2666, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 17 | LPDDR4_3200, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 18 | LPDDR4_3733, |
| 19 | LPDDR4_4266, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 20 | }; |
| 21 | |
| 22 | struct lpddr4_speed_attr { |
| 23 | uint32_t min_clock_mhz; // inclusive |
| 24 | uint32_t max_clock_mhz; // inclusive |
| 25 | uint32_t reported_mts; |
| 26 | }; |
| 27 | |
| 28 | /** |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 29 | * LPDDR4 speed attributes derived from JEDEC 209-4C and industry norms |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 30 | * |
| 31 | * min_clock_mhz = Previous max_clock_mhz + 1 |
| 32 | * max_clock_mhz = 1000/min_tCk_avg(ns) |
| 33 | * reported_mts = Standard reported DDR4 speed in MT/s |
| 34 | * May be slightly less than the actual max MT/s |
| 35 | */ |
| 36 | static const struct lpddr4_speed_attr lpddr4_speeds[] = { |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 37 | [LPDDR4_1333] = { |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 38 | .min_clock_mhz = 10, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 39 | .max_clock_mhz = 667, |
| 40 | .reported_mts = 1333, |
| 41 | }, |
| 42 | [LPDDR4_1600] = { |
| 43 | .min_clock_mhz = 668, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 44 | .max_clock_mhz = 800, |
| 45 | .reported_mts = 1600 |
| 46 | }, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 47 | [LPDDR4_1866] = { |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 48 | .min_clock_mhz = 801, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 49 | .max_clock_mhz = 934, |
| 50 | .reported_mts = 1866, |
| 51 | }, |
| 52 | [LPDDR4_2133] = { |
| 53 | .min_clock_mhz = 935, |
| 54 | .max_clock_mhz = 1067, |
| 55 | .reported_mts = 2133 |
| 56 | }, |
| 57 | [LPDDR4_2400] = { |
| 58 | .min_clock_mhz = 1068, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 59 | .max_clock_mhz = 1200, |
| 60 | .reported_mts = 2400 |
| 61 | }, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 62 | [LPDDR4_2666] = { |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 63 | .min_clock_mhz = 1201, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 64 | .max_clock_mhz = 1333, |
| 65 | .reported_mts = 2666 |
| 66 | }, |
| 67 | [LPDDR4_3200] = { |
| 68 | .min_clock_mhz = 1334, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 69 | .max_clock_mhz = 1600, |
| 70 | .reported_mts = 3200 |
| 71 | }, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 72 | [LPDDR4_3733] = { |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 73 | .min_clock_mhz = 1601, |
Rob Barnes | 4c66daa | 2021-08-31 15:42:20 -0600 | [diff] [blame] | 74 | .max_clock_mhz = 1867, |
| 75 | .reported_mts = 3733 |
| 76 | }, |
| 77 | [LPDDR4_4266] = { |
| 78 | .min_clock_mhz = 1868, |
| 79 | .max_clock_mhz = 2134, |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 80 | .reported_mts = 4266 |
| 81 | }, |
| 82 | }; |
| 83 | |
| 84 | /** |
| 85 | * Converts LPDDR4 clock speed in MHz to the standard reported speed in MT/s |
| 86 | */ |
| 87 | uint16_t lpddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) |
| 88 | { |
| 89 | for (enum lpddr4_speed_grade speed = 0; speed < ARRAY_SIZE(lpddr4_speeds); speed++) { |
| 90 | const struct lpddr4_speed_attr *speed_attr = &lpddr4_speeds[speed]; |
| 91 | if (speed_mhz >= speed_attr->min_clock_mhz && |
| 92 | speed_mhz <= speed_attr->max_clock_mhz) { |
| 93 | return speed_attr->reported_mts; |
| 94 | } |
| 95 | } |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 96 | printk(BIOS_ERR, "LPDDR4 speed of %d MHz is out of range\n", speed_mhz); |
Rob Barnes | f892b85 | 2021-06-07 08:55:14 -0600 | [diff] [blame] | 97 | return 0; |
| 98 | } |