Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <arch/acpi.h> |
| 19 | #include <arch/acpigen.h> |
| 20 | #include <cbmem.h> |
| 21 | #include <chip.h> |
| 22 | #include <console/console.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 23 | #include <cpu/amd/mtrr.h> |
| 24 | #include <cpu/cpu.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <device/hypertransport.h> |
| 29 | #include <lib.h> |
| 30 | #include <agesawrapper.h> |
| 31 | #include <agesawrapper_call.h> |
| 32 | #include <soc/northbridge.h> |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 34 | #include <stdint.h> |
| 35 | #include <stdlib.h> |
| 36 | #include <string.h> |
| 37 | |
| 38 | /* |
| 39 | * AMD vendorcode files. Place at the end so coreboot defaults and maintained |
| 40 | * and not set by vendorcode |
| 41 | */ |
| 42 | #include <AGESA.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 43 | #include <FieldAccessors.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 44 | #include <Porting.h> |
| 45 | #include <Topology.h> |
| 46 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 47 | typedef struct dram_base_mask { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 48 | u32 base; /* [47:27] at [28:8] */ |
| 49 | u32 mask; /* [47:27] at [28:8] and enable at bit 0 */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 50 | } dram_base_mask_t; |
| 51 | |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 52 | static dram_base_mask_t get_dram_base_mask(void) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 53 | { |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 54 | device_t dev = dev_find_slot(0, ADDR_DEVFN); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 55 | dram_base_mask_t d; |
| 56 | u32 temp; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 57 | |
| 58 | /* [39:24] at [31:16] */ |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 59 | temp = pci_read_config32(dev, 0x44); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 60 | |
| 61 | /* mask out DramMask [26:24] too */ |
| 62 | d.mask = ((temp & 0xfff80000) >> (8 + 3)); |
| 63 | |
| 64 | /* [47:40] at [7:0] */ |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 65 | temp = pci_read_config32(dev, 0x144) & 0xff; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 66 | d.mask |= temp << 21; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 67 | |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 68 | temp = pci_read_config32(dev, 0x40); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 69 | d.mask |= (temp & 1); /* enable bit */ |
| 70 | d.base = ((temp & 0xfff80000) >> (8 + 3)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 71 | temp = pci_read_config32(dev, 0x140) & 0xff; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 72 | d.base |= temp << 21; |
| 73 | return d; |
| 74 | } |
| 75 | |
| 76 | static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, |
| 77 | u32 io_min, u32 io_max) |
| 78 | { |
| 79 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 80 | device_t addr_map = dev_find_slot(0, ADDR_DEVFN); |
| 81 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 82 | /* io range allocation. Limit */ |
| 83 | tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) |
| 84 | | ((io_max & 0xf0) << (12 - 4)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 85 | pci_write_config32(addr_map, reg + 4, tempreg); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 86 | tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 87 | pci_write_config32(addr_map, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 88 | } |
| 89 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 90 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, |
| 91 | u32 mmio_min, u32 mmio_max) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 92 | { |
| 93 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 94 | device_t addr_map = dev_find_slot(0, ADDR_DEVFN); |
| 95 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 96 | /* io range allocation. Limit */ |
| 97 | tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 98 | pci_write_config32(addr_map, reg + 4, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 99 | tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 100 | pci_write_config32(addr_map, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 101 | } |
| 102 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 103 | static void read_resources(device_t dev) |
| 104 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 105 | /* |
| 106 | * This MMCONF resource must be reserved in the PCI domain. |
| 107 | * It is not honored by the coreboot resource allocator if it is in |
| 108 | * the CPU_CLUSTER. |
| 109 | */ |
| 110 | mmconf_resource(dev, 0xc0010058); |
| 111 | } |
| 112 | |
| 113 | static void set_resource(device_t dev, struct resource *resource, u32 nodeid) |
| 114 | { |
| 115 | resource_t rbase, rend; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 116 | unsigned int reg, link_num; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 117 | char buf[50]; |
| 118 | |
| 119 | /* Make certain the resource has actually been set */ |
| 120 | if (!(resource->flags & IORESOURCE_ASSIGNED)) |
| 121 | return; |
| 122 | |
| 123 | /* If I have already stored this resource don't worry about it */ |
| 124 | if (resource->flags & IORESOURCE_STORED) |
| 125 | return; |
| 126 | |
| 127 | /* Only handle PCI memory and IO resources */ |
| 128 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 129 | return; |
| 130 | |
| 131 | /* Ensure I am actually looking at a resource of function 1 */ |
| 132 | if ((resource->index & 0xffff) < 0x1000) |
| 133 | return; |
| 134 | |
| 135 | /* Get the base address */ |
| 136 | rbase = resource->base; |
| 137 | |
| 138 | /* Get the limit (rounded up) */ |
| 139 | rend = resource_end(resource); |
| 140 | |
| 141 | /* Get the register and link */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 142 | reg = resource->index & 0xfff; /* 4k */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 143 | link_num = IOINDEX_LINK(resource->index); |
| 144 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 145 | if (resource->flags & IORESOURCE_IO) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 146 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 147 | else if (resource->flags & IORESOURCE_MEM) |
| 148 | set_mmio_addr_reg(nodeid, link_num, reg, |
| 149 | (resource->index >> 24), rbase >> 8, rend >> 8); |
| 150 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 151 | resource->flags |= IORESOURCE_STORED; |
| 152 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
| 153 | nodeid, link_num); |
| 154 | report_resource_stored(dev, resource, buf); |
| 155 | } |
| 156 | |
| 157 | /** |
| 158 | * I tried to reuse the resource allocation code in set_resource() |
| 159 | * but it is too difficult to deal with the resource allocation magic. |
| 160 | */ |
| 161 | |
| 162 | static void create_vga_resource(device_t dev) |
| 163 | { |
| 164 | struct bus *link; |
| 165 | |
| 166 | /* find out which link the VGA card is connected, |
| 167 | * we only deal with the 'first' vga card */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 168 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 169 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 170 | break; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 171 | |
| 172 | /* no VGA card installed */ |
| 173 | if (link == NULL) |
| 174 | return; |
| 175 | |
Marshall Dawson | e2697de | 2017-09-06 10:46:36 -0600 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 177 | /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ |
| 178 | pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | static void set_resources(device_t dev) |
| 182 | { |
| 183 | struct bus *bus; |
| 184 | struct resource *res; |
| 185 | |
| 186 | |
| 187 | /* do we need this? */ |
| 188 | create_vga_resource(dev); |
| 189 | |
| 190 | /* Set each resource we have found */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 191 | for (res = dev->resource_list ; res ; res = res->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 192 | set_resource(dev, res, 0); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 193 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 194 | for (bus = dev->link_list ; bus ; bus = bus->next) |
| 195 | if (bus->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 196 | assign_resources(bus); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | static void northbridge_init(struct device *dev) |
| 200 | { |
| 201 | } |
| 202 | |
| 203 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
| 204 | { |
| 205 | void *addr, *current; |
| 206 | |
| 207 | /* Skip the HEST header. */ |
| 208 | current = (void *)(hest + 1); |
| 209 | |
| 210 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 211 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 212 | current += acpi_create_hest_error_source(hest, current, 0, |
| 213 | (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 214 | |
| 215 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 216 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 217 | current += acpi_create_hest_error_source(hest, current, 1, |
| 218 | (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 219 | |
| 220 | return (unsigned long)current; |
| 221 | } |
| 222 | |
| 223 | static void northbridge_fill_ssdt_generator(device_t device) |
| 224 | { |
| 225 | msr_t msr; |
| 226 | char pscope[] = "\\_SB.PCI0"; |
| 227 | |
| 228 | acpigen_write_scope(pscope); |
| 229 | msr = rdmsr(TOP_MEM); |
| 230 | acpigen_write_name_dword("TOM1", msr.lo); |
| 231 | msr = rdmsr(TOP_MEM2); |
| 232 | /* |
| 233 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 234 | * here. |
| 235 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 236 | * slide 22ff. |
| 237 | * Shift value right by 20 bit to make it fit into 32bit, |
| 238 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 239 | */ |
| 240 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 241 | acpigen_pop_len(); |
| 242 | } |
| 243 | |
| 244 | static unsigned long agesa_write_acpi_tables(device_t device, |
| 245 | unsigned long current, |
| 246 | acpi_rsdp_t *rsdp) |
| 247 | { |
| 248 | acpi_srat_t *srat; |
| 249 | acpi_slit_t *slit; |
| 250 | acpi_header_t *ssdt; |
| 251 | acpi_header_t *alib; |
| 252 | acpi_header_t *ivrs; |
| 253 | acpi_hest_t *hest; |
| 254 | |
| 255 | /* HEST */ |
| 256 | current = ALIGN(current, 8); |
| 257 | hest = (acpi_hest_t *)current; |
| 258 | acpi_write_hest((void *)current, acpi_fill_hest); |
| 259 | acpi_add_table(rsdp, (void *)current); |
| 260 | current += ((acpi_header_t *)current)->length; |
| 261 | |
| 262 | current = ALIGN(current, 8); |
| 263 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 264 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 265 | if (ivrs != NULL) { |
| 266 | memcpy((void *)current, ivrs, ivrs->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 267 | ivrs = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 268 | current += ivrs->length; |
| 269 | acpi_add_table(rsdp, ivrs); |
| 270 | } else { |
| 271 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 272 | } |
| 273 | |
| 274 | /* SRAT */ |
| 275 | current = ALIGN(current, 8); |
| 276 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 277 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 278 | if (srat != NULL) { |
| 279 | memcpy((void *)current, srat, srat->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 280 | srat = (acpi_srat_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 281 | current += srat->header.length; |
| 282 | acpi_add_table(rsdp, srat); |
| 283 | } else { |
| 284 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 285 | } |
| 286 | |
| 287 | /* SLIT */ |
| 288 | current = ALIGN(current, 8); |
| 289 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 290 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 291 | if (slit != NULL) { |
| 292 | memcpy((void *)current, slit, slit->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 293 | slit = (acpi_slit_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 294 | current += slit->header.length; |
| 295 | acpi_add_table(rsdp, slit); |
| 296 | } else { |
| 297 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 298 | } |
| 299 | |
| 300 | /* ALIB */ |
| 301 | current = ALIGN(current, 16); |
| 302 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 303 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 304 | if (alib != NULL) { |
| 305 | memcpy((void *)current, alib, alib->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 306 | alib = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 307 | current += alib->length; |
| 308 | acpi_add_table(rsdp, (void *)alib); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 309 | } else { |
| 310 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." |
| 311 | " Skipping.\n"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 312 | } |
| 313 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 314 | current = ALIGN(current, 16); |
| 315 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 316 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 317 | if (ssdt != NULL) { |
| 318 | memcpy((void *)current, ssdt, ssdt->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 319 | ssdt = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 320 | current += ssdt->length; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 321 | } else { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 322 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 323 | } |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 324 | acpi_add_table(rsdp, ssdt); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 325 | |
| 326 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 327 | return current; |
| 328 | } |
| 329 | |
| 330 | static struct device_operations northbridge_operations = { |
| 331 | .read_resources = read_resources, |
| 332 | .set_resources = set_resources, |
| 333 | .enable_resources = pci_dev_enable_resources, |
| 334 | .init = northbridge_init, |
| 335 | .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, |
| 336 | .write_acpi_tables = agesa_write_acpi_tables, |
| 337 | .enable = 0, |
| 338 | .ops_pci = 0, |
| 339 | }; |
| 340 | |
| 341 | static const struct pci_driver family15_northbridge __pci_driver = { |
| 342 | .ops = &northbridge_operations, |
| 343 | .vendor = PCI_VENDOR_ID_AMD, |
| 344 | .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, |
| 345 | }; |
| 346 | |
| 347 | void fam15_finalize(void *chip_info) |
| 348 | { |
| 349 | device_t dev; |
| 350 | u32 value; |
| 351 | dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 352 | pci_write_config32(dev, 0xf8, 0); |
| 353 | pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 354 | |
| 355 | /* disable No Snoop */ |
| 356 | dev = dev_find_slot(0, PCI_DEVFN(1, 1)); |
| 357 | value = pci_read_config32(dev, 0x60); |
| 358 | value &= ~(1 << 11); |
| 359 | pci_write_config32(dev, 0x60, value); |
| 360 | } |
| 361 | |
| 362 | void domain_read_resources(device_t dev) |
| 363 | { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 364 | unsigned int reg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 365 | device_t addr_map = dev_find_slot(0, ADDR_DEVFN); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 366 | |
| 367 | /* Find the already assigned resource pairs */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 368 | for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 369 | u32 base, limit; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 370 | base = pci_read_config32(addr_map, reg); |
| 371 | limit = pci_read_config32(addr_map, reg + 4); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 372 | /* Is this register allocated? */ |
| 373 | if ((base & 3) != 0) { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 374 | unsigned int nodeid, reg_link; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 375 | device_t reg_dev = dev_find_slot(0, HT_DEVFN); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 376 | if (reg < 0xc0) /* mmio */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 377 | nodeid = (limit & 0xf) + (base & 0x30); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 378 | else /* io */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 379 | nodeid = (limit & 0xf) + ((base >> 4) & 0x30); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 380 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 381 | reg_link = (limit >> 4) & 7; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 382 | if (reg_dev) { |
| 383 | /* Reserve the resource */ |
| 384 | struct resource *res; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 385 | res = new_resource(reg_dev, |
| 386 | IOINDEX(0x1000 + reg, |
| 387 | reg_link)); |
| 388 | if (res) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 389 | res->flags = 1; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 390 | } |
| 391 | } |
| 392 | } |
| 393 | /* FIXME: do we need to check extend conf space? |
| 394 | I don't believe that much preset value */ |
| 395 | |
| 396 | pci_domain_read_resources(dev); |
| 397 | } |
| 398 | |
| 399 | void domain_enable_resources(device_t dev) |
| 400 | { |
| 401 | if (acpi_is_wakeup_s3()) |
| 402 | AGESAWRAPPER(fchs3laterestore); |
| 403 | |
| 404 | /* Must be called after PCI enumeration and resource allocation */ |
| 405 | if (!acpi_is_wakeup_s3()) |
| 406 | AGESAWRAPPER(amdinitmid); |
| 407 | |
| 408 | printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); |
| 409 | } |
| 410 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 411 | void domain_set_resources(device_t dev) |
| 412 | { |
| 413 | unsigned long mmio_basek; |
| 414 | u32 pci_tolm; |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 415 | u32 hole; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 416 | int idx; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 417 | struct bus *link; |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame^] | 418 | void *tseg_base; |
| 419 | size_t tseg_size; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 420 | |
| 421 | pci_tolm = 0xffffffffUL; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 422 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 423 | pci_tolm = find_pci_tolm(link); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 424 | |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 425 | /* Start with alignment supportable in variable MTRR */ |
| 426 | mmio_basek = ALIGN_DOWN(pci_tolm, 4 * KiB) / KiB; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 427 | |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 428 | /* |
| 429 | * AGESA may have programmed the memory hole and rounded down to a |
| 430 | * 128MB boundary. If we find it's valid, adjust mmio_basek downward |
| 431 | * to the hole bottom. D18F1xF0[DramHoleBase] is granular to 16MB. |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 432 | */ |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 433 | hole = pci_read_config32(dev_find_slot(0, ADDR_DEVFN), D18F1_DRAM_HOLE); |
| 434 | if (hole & DRAM_HOLE_VALID) |
| 435 | mmio_basek = min(mmio_basek, ALIGN_DOWN(hole, 16 * MiB) / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 436 | |
| 437 | idx = 0x10; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 438 | dram_base_mask_t d; |
| 439 | resource_t basek, limitk, sizek; /* 4 1T */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 440 | |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 441 | d = get_dram_base_mask(); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 442 | |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 443 | if ((d.mask & 1)) { /* if enabled... */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 444 | /* could overflow, we may lose 6 bit here */ |
| 445 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; |
| 446 | limitk = ((resource_t)(((d.mask & ~1) + 0x000ff) |
| 447 | & 0x1fffff00)) << 9; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 448 | |
| 449 | sizek = limitk - basek; |
| 450 | |
| 451 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 452 | if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) + |
| 453 | (16 * 16)))) { |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 454 | ram_resource(dev, idx, basek, |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 455 | ((8 * 64) + (8 * 16)) - basek); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 456 | idx += 0x10; |
| 457 | basek = (8 * 64) + (16 * 16); |
| 458 | sizek = limitk - ((8 * 64) + (16 * 16)); |
| 459 | |
| 460 | } |
| 461 | |
| 462 | /* split the region to accommodate pci memory space */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 463 | if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 464 | if (basek <= mmio_basek) { |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 465 | unsigned int pre_sizek; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 466 | pre_sizek = mmio_basek - basek; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 467 | if (pre_sizek > 0) { |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 468 | ram_resource(dev, idx, basek, |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 469 | pre_sizek); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 470 | idx += 0x10; |
| 471 | sizek -= pre_sizek; |
| 472 | } |
| 473 | basek = mmio_basek; |
| 474 | } |
| 475 | if ((basek + sizek) <= 4 * 1024 * 1024) { |
| 476 | sizek = 0; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 477 | } else { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 478 | uint64_t topmem2 = bsp_topmem2(); |
| 479 | basek = 4 * 1024 * 1024; |
| 480 | sizek = topmem2 / 1024 - basek; |
| 481 | } |
| 482 | } |
| 483 | |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 484 | ram_resource(dev, idx, basek, sizek); |
| 485 | printk(BIOS_DEBUG, "node 0: mmio_basek=%08lx, basek=%08llx," |
| 486 | " limitk=%08llx\n", mmio_basek, basek, limitk); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 487 | } |
| 488 | |
Marshall Dawson | 7ac2af3 | 2017-09-19 16:26:34 -0600 | [diff] [blame] | 489 | /* UMA is not set up yet, but infer the base & size to make cacheable */ |
| 490 | uint32_t uma_base = restore_top_of_low_cacheable(); |
| 491 | if (uma_base != bsp_topmem()) { |
| 492 | uint32_t uma_size = bsp_topmem() - uma_base; |
| 493 | printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", |
| 494 | __func__, uma_size, uma_base); |
| 495 | reserved_ram_resource(dev, 7, uma_base / KiB, uma_size / KiB); |
| 496 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 497 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 498 | for (link = dev->link_list ; link ; link = link->next) |
| 499 | if (link->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 500 | assign_resources(link); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 501 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 502 | /* |
| 503 | * Reserve everything between A segment and 1MB: |
| 504 | * |
| 505 | * 0xa0000 - 0xbffff: legacy VGA |
| 506 | * 0xc0000 - 0xfffff: RAM |
| 507 | */ |
| 508 | mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB); |
| 509 | reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB); |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame^] | 510 | |
| 511 | /* Reserve TSEG */ |
| 512 | smm_region_info(&tseg_base, &tseg_size); |
| 513 | idx += 0x10; |
| 514 | reserved_ram_resource(dev, idx, (unsigned long)tseg_base/KiB, |
| 515 | tseg_size/KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 516 | } |
| 517 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 518 | /********************************************************************* |
| 519 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 520 | *********************************************************************/ |
| 521 | u32 map_oprom_vendev(u32 vendev) |
| 522 | { |
| 523 | u32 new_vendev; |
| 524 | new_vendev = |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 525 | ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? |
| 526 | 0x100298e0 : vendev; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 527 | |
| 528 | if (vendev != new_vendev) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 529 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", |
| 530 | vendev, new_vendev); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 531 | |
| 532 | return new_vendev; |
| 533 | } |