Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mtspd3.h |
| 6 | * |
| 7 | * Technology SPD support for DDR3 |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Tech/DDR3) |
| 12 | * @e \$Revision: 35415 $ @e \$Date: 2010-07-22 06:10:32 +0800 (Thu, 22 Jul 2010) $ |
| 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _MTSPD3_H_ |
| 48 | #define _MTSPD3_H_ |
| 49 | |
| 50 | /*---------------------------------------------------------------------------- |
| 51 | * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) |
| 52 | * |
| 53 | *---------------------------------------------------------------------------- |
| 54 | */ |
| 55 | |
| 56 | /*----------------------------------------------------------------------------- |
| 57 | * DEFINITIONS AND MACROS |
| 58 | * |
| 59 | *----------------------------------------------------------------------------- |
| 60 | */ |
| 61 | |
| 62 | /*=============================================================================== |
| 63 | * Jedec DDR III |
| 64 | *=============================================================================== |
| 65 | */ |
| 66 | #define SPD_BYTE_USED 0 |
| 67 | #define SPD_TYPE 2 /* SPD byte read location */ |
| 68 | #define JED_DDR_SDRAM 7 /* Jedec defined bit field */ |
| 69 | #define JED_DDR2_SDRAM 8 /* Jedec defined bit field */ |
| 70 | #define JED_DDR3SDRAM 0xB /* Jedec defined bit field */ |
| 71 | |
| 72 | #define SPD_DIMM_TYPE 3 |
| 73 | #define SPD_ATTRIB 21 |
| 74 | #define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */ |
| 75 | #define JED_RDIMM 1 |
| 76 | #define JED_MINIRDIMM 5 |
| 77 | #define JED_UDIMM 2 |
| 78 | #define JED_SODIMM 3 |
| 79 | #define JED_LRDIMM 0xB |
| 80 | |
| 81 | #define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */ |
| 82 | #define SPD_DENSITY 4 /* bit 3:0 */ |
| 83 | #define SPD_ROW_SZ 5 /* bit 5:3 */ |
| 84 | #define SPD_COL_SZ 5 /* bit 2:0 */ |
| 85 | #define SPD_RANKS 7 /* bit 5:3 */ |
| 86 | #define SPD_DEV_WIDTH 7 /* bit 2:0 */ |
| 87 | #define SPD_ECCBITS 8 /* bit 4:3 */ |
| 88 | #define JED_ECC 8 |
| 89 | #define SPD_RAWCARD 62 /* bit 2:0 */ |
| 90 | #define SPD_ADDRMAP 63 /* bit 0 */ |
| 91 | |
| 92 | #define SPD_CTLWRD03 70 /* bit 7:4 */ |
| 93 | #define SPD_CTLWRD04 71 /* bit 3:0 */ |
| 94 | #define SPD_CTLWRD05 71 /* bit 7:4 */ |
| 95 | |
| 96 | #define SPD_FTB 9 |
| 97 | |
Mike Banon | f7b410d | 2020-04-17 14:56:42 +0300 | [diff] [blame^] | 98 | #if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame] | 99 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 100 | #define SPD_DIVIDENT 10 |
| 101 | #define SPD_DIVISOR 11 |
| 102 | |
| 103 | #define SPD_TCK 12 |
| 104 | #define SPD_CASLO 14 |
| 105 | #define SPD_CASHI 15 |
| 106 | #define SPD_TAA 16 |
| 107 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 108 | #define SPD_TWR 17 |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame] | 109 | #define SPD_TRCD 18 |
| 110 | #define SPD_TRRD 19 |
| 111 | #define SPD_TRP 20 |
| 112 | #define SPD_UPPER_TRC 21 /* bits 7:4 */ |
| 113 | #define SPD_UPPER_TRAS 21 /* bits 3:0 */ |
| 114 | #define SPD_TRAS 22 |
| 115 | #define SPD_TRC 23 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 116 | #define SPD_TWTR 26 |
| 117 | #define SPD_TRTP 27 |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame] | 118 | #define SPD_UPPER_TFAW 28 /* bits 3:0 */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 119 | #define SPD_TFAW 29 |
Mike Banon | 3ee9935 | 2020-04-17 14:35:20 +0300 | [diff] [blame] | 120 | |
| 121 | #endif |
| 122 | |
| 123 | #if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) |
| 124 | |
| 125 | #define SPD_DIVIDENT 180 |
| 126 | #define SPD_DIVISOR 181 |
| 127 | |
| 128 | #define SPD_TCK 186 |
| 129 | #define SPD_CASLO 188 |
| 130 | #define SPD_CASHI 189 |
| 131 | #define SPD_TAA 187 |
| 132 | |
| 133 | #define SPD_TWR 193 |
| 134 | #define SPD_TRCD 192 |
| 135 | #define SPD_TRRD 202 |
| 136 | #define SPD_TRP 191 |
| 137 | #define SPD_UPPER_TRC 194 /* bits 7:4 */ |
| 138 | #define SPD_UPPER_TRAS 194 /* bits 3:0 */ |
| 139 | #define SPD_TRAS 195 |
| 140 | #define SPD_TRC 196 |
| 141 | #define SPD_TWTR 205 |
| 142 | #define SPD_TRTP 201 |
| 143 | #define SPD_UPPER_TFAW 203 /* bits 3:0 */ |
| 144 | #define SPD_TFAW 204 |
| 145 | |
| 146 | #endif |
| 147 | |
| 148 | #if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) |
| 149 | |
| 150 | #define SPD_DIVIDENT 182 |
| 151 | #define SPD_DIVISOR 183 |
| 152 | |
| 153 | #define SPD_TCK 221 |
| 154 | #define SPD_CASLO 223 |
| 155 | #define SPD_CASHI 224 |
| 156 | #define SPD_TAA 222 |
| 157 | |
| 158 | #define SPD_TWR 228 |
| 159 | #define SPD_TRCD 227 |
| 160 | #define SPD_TRRD 237 |
| 161 | #define SPD_TRP 226 |
| 162 | #define SPD_UPPER_TRC 229 /* bits 7:4 */ |
| 163 | #define SPD_UPPER_TRAS 229 /* bits 3:0 */ |
| 164 | #define SPD_TRAS 230 |
| 165 | #define SPD_TRC 231 |
| 166 | #define SPD_TWTR 240 |
| 167 | #define SPD_TRTP 236 |
| 168 | #define SPD_UPPER_TFAW 238 /* bits 3:0 */ |
| 169 | #define SPD_TFAW 239 |
| 170 | |
| 171 | #endif |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 172 | |
| 173 | #define SPD_TCK_FTB 34 |
| 174 | #define SPD_TAA_FTB 35 |
| 175 | #define SPD_TRCD_FTB 36 |
| 176 | #define SPD_TRP_FTB 37 |
| 177 | #define SPD_TRC_FTB 38 |
| 178 | |
| 179 | /*----------------------------- |
| 180 | * Jedec DDR II related equates |
| 181 | *----------------------------- |
| 182 | */ |
| 183 | |
| 184 | #define CL_DEF 4 /* Default value for failsafe operation. 4=CL 6.0 T */ |
| 185 | #define T_DEF 4 /* Default value for failsafe operation. 4=2.5ns (cycle time) */ |
| 186 | |
| 187 | #define BIAS_TRTP_T 4 |
| 188 | #define BIAS_TRCD_T 5 |
| 189 | #define BIAS_TRAS_T 15 |
| 190 | #define BIAS_TRC_T 11 |
| 191 | #define BIAS_TRRD_T 4 |
| 192 | #define BIAS_TWR_T 4 |
| 193 | #define BIAS_TRP_T 5 |
| 194 | #define BIAS_TWTR_T 4 |
| 195 | #define BIAS_TFAW_T 14 |
| 196 | |
| 197 | #define MIN_TRTP_T 4 |
| 198 | #define MAX_TRTP_T 7 |
| 199 | #define MIN_TRCD_T 5 |
| 200 | #define MAX_TRCD_T 12 |
| 201 | #define MIN_TRAS_T 15 |
| 202 | #define MAX_TRAS_T 30 |
| 203 | #define MIN_TRC_T 11 |
| 204 | #define MAX_TRC_T 42 |
| 205 | #define MIN_TRRD_T 4 |
| 206 | #define MAX_TRRD_T 7 |
| 207 | #define MIN_TWR_T 5 |
| 208 | #define MAX_TWR_T 12 |
| 209 | #define MIN_TRP_T 5 |
| 210 | #define MAX_TRP_T 12 |
| 211 | #define MIN_TWTR_T 4 |
| 212 | #define MAX_TWTR_T 7 |
| 213 | #define MIN_TFAW_T 16 |
| 214 | #define MAX_TFAW_T 32 |
| 215 | |
| 216 | /*---------------------------------------------------------------------------- |
| 217 | * TYPEDEFS, STRUCTURES, ENUMS |
| 218 | * |
| 219 | *---------------------------------------------------------------------------- |
| 220 | */ |
| 221 | |
| 222 | /*---------------------------------------------------------------------------- |
| 223 | * FUNCTIONS PROTOTYPE |
| 224 | * |
| 225 | *---------------------------------------------------------------------------- |
| 226 | */ |
| 227 | |
| 228 | |
| 229 | #endif /* _MTSPD3_H_ */ |
| 230 | |
| 231 | |