Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | // Use simple device model for this file even in ramstage |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
| 19 | #include <arch/io.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 20 | #include <arch/cpu.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 21 | #include <cbmem.h> |
| 22 | #include "i945.h" |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 23 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 24 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <program_loading.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 27 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 28 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 29 | { |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 30 | uintptr_t tom; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 31 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 32 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 33 | /* IGD enabled, get top of Memory from BSM register */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 34 | tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); |
| 35 | else |
| 36 | tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 37 | |
| 38 | /* if TSEG enabled subtract size */ |
Elyes HAOUAS | 8324d87 | 2018-01-19 12:52:25 +0100 | [diff] [blame] | 39 | switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC) & 0x07) { |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 40 | case 0x01: |
| 41 | /* 1MB TSEG */ |
Kyösti Mälkki | fd2501b | 2014-05-31 16:36:29 +0300 | [diff] [blame] | 42 | tom -= 0x100000; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 43 | break; |
| 44 | case 0x03: |
| 45 | /* 2MB TSEG */ |
Kyösti Mälkki | fd2501b | 2014-05-31 16:36:29 +0300 | [diff] [blame] | 46 | tom -= 0x200000; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 47 | break; |
| 48 | case 0x05: |
| 49 | /* 8MB TSEG */ |
Kyösti Mälkki | fd2501b | 2014-05-31 16:36:29 +0300 | [diff] [blame] | 50 | tom -= 0x800000; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 51 | break; |
| 52 | default: |
| 53 | /* TSEG either disabled or invalid */ |
| 54 | break; |
| 55 | } |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 56 | return tom; |
| 57 | } |
| 58 | |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 59 | /* Depending of UMA and TSEG configuration, TSEG might start at any |
| 60 | * 1 MiB aligment. As this may cause very greedy MTRR setup, push |
| 61 | * CBMEM top downwards to 4 MiB boundary. |
| 62 | */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 63 | void *cbmem_top(void) |
| 64 | { |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 65 | uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); |
| 66 | return (void *) top_of_ram; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 67 | } |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 68 | |
| 69 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 70 | u32 decode_igd_memory_size(const u32 gms) |
| 71 | { |
| 72 | static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, |
| 73 | 48, 64 }; |
| 74 | |
| 75 | if (gms > ARRAY_SIZE(ggc2uma)) |
| 76 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
| 77 | |
| 78 | return ggc2uma[gms] << 10; |
| 79 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 80 | |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 81 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
| 82 | |
Arthur Heymans | 2dcc3a5 | 2018-06-03 10:39:16 +0200 | [diff] [blame] | 83 | /* platform_enter_postcar() determines the stack to use after |
| 84 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 85 | * and continues execution in postcar stage. */ |
| 86 | void platform_enter_postcar(void) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 87 | { |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 88 | struct postcar_frame pcf; |
| 89 | uintptr_t top_of_ram; |
| 90 | |
| 91 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 92 | die("Unable to initialize postcar frame.\n"); |
| 93 | |
| 94 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 95 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 96 | |
| 97 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 98 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 99 | |
| 100 | /* Cache two separate 4 MiB regions below the top of ram, this |
| 101 | * satisfies MTRR alignment requirements. If you modify this to |
| 102 | * cover TSEG, make sure UMA region is not set with WRBACK as it |
| 103 | * causes hard-to-recover boot failures. |
| 104 | */ |
| 105 | top_of_ram = (uintptr_t)cbmem_top(); |
| 106 | postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); |
| 107 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); |
| 108 | |
Arthur Heymans | 2dcc3a5 | 2018-06-03 10:39:16 +0200 | [diff] [blame] | 109 | run_postcar_phase(&pcf); |
| 110 | |
| 111 | /* We do not return here. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 112 | } |