Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | SMRAM Save State Map Definitions. |
| 3 | |
| 4 | SMRAM Save State Map definitions based on contents of the |
| 5 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual |
| 6 | Volume 3C, Section 34.4 SMRAM |
| 7 | Volume 3C, Section 34.5 SMI Handler Execution Environment |
| 8 | Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs |
| 9 | |
| 10 | Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR> |
| 11 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 12 | |
| 13 | **/ |
| 14 | |
| 15 | #ifndef __INTEL_SMRAM_SAVE_STATE_MAP_H__ |
| 16 | #define __INTEL_SMRAM_SAVE_STATE_MAP_H__ |
| 17 | |
| 18 | /// |
| 19 | /// Default SMBASE address |
| 20 | /// |
| 21 | #define SMM_DEFAULT_SMBASE 0x30000 |
| 22 | |
| 23 | /// |
| 24 | /// Offset of SMM handler from SMBASE |
| 25 | /// |
| 26 | #define SMM_HANDLER_OFFSET 0x8000 |
| 27 | |
| 28 | /// |
| 29 | /// Offset of SMRAM Save State Map from SMBASE |
| 30 | /// |
| 31 | #define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00 |
| 32 | |
| 33 | #pragma pack (1) |
| 34 | |
| 35 | /// |
| 36 | /// 32-bit SMRAM Save State Map |
| 37 | /// |
| 38 | typedef struct { |
| 39 | UINT8 Reserved[0x200]; // 7c00h |
| 40 | // Padded an extra 0x200 bytes so 32-bit and 64-bit |
| 41 | // SMRAM Save State Maps are the same size |
| 42 | UINT8 Reserved1[0xf8]; // 7e00h |
| 43 | UINT32 SMBASE; // 7ef8h |
| 44 | UINT32 SMMRevId; // 7efch |
| 45 | UINT16 IORestart; // 7f00h |
| 46 | UINT16 AutoHALTRestart; // 7f02h |
| 47 | UINT8 Reserved2[0x9C]; // 7f08h |
| 48 | UINT32 IOMemAddr; // 7fa0h |
| 49 | UINT32 IOMisc; // 7fa4h |
| 50 | UINT32 _ES; // 7fa8h |
| 51 | UINT32 _CS; // 7fach |
| 52 | UINT32 _SS; // 7fb0h |
| 53 | UINT32 _DS; // 7fb4h |
| 54 | UINT32 _FS; // 7fb8h |
| 55 | UINT32 _GS; // 7fbch |
| 56 | UINT32 Reserved3; // 7fc0h |
| 57 | UINT32 _TR; // 7fc4h |
| 58 | UINT32 _DR7; // 7fc8h |
| 59 | UINT32 _DR6; // 7fcch |
| 60 | UINT32 _EAX; // 7fd0h |
| 61 | UINT32 _ECX; // 7fd4h |
| 62 | UINT32 _EDX; // 7fd8h |
| 63 | UINT32 _EBX; // 7fdch |
| 64 | UINT32 _ESP; // 7fe0h |
| 65 | UINT32 _EBP; // 7fe4h |
| 66 | UINT32 _ESI; // 7fe8h |
| 67 | UINT32 _EDI; // 7fech |
| 68 | UINT32 _EIP; // 7ff0h |
| 69 | UINT32 _EFLAGS; // 7ff4h |
| 70 | UINT32 _CR3; // 7ff8h |
| 71 | UINT32 _CR0; // 7ffch |
| 72 | } SMRAM_SAVE_STATE_MAP32; |
| 73 | |
| 74 | /// |
| 75 | /// 64-bit SMRAM Save State Map |
| 76 | /// |
| 77 | typedef struct { |
| 78 | UINT8 Reserved1[0x1d0]; // 7c00h |
| 79 | UINT32 GdtBaseHiDword; // 7dd0h |
| 80 | UINT32 LdtBaseHiDword; // 7dd4h |
| 81 | UINT32 IdtBaseHiDword; // 7dd8h |
| 82 | UINT8 Reserved2[0xc]; // 7ddch |
| 83 | UINT64 IO_EIP; // 7de8h |
| 84 | UINT8 Reserved3[0x50]; // 7df0h |
| 85 | UINT32 _CR4; // 7e40h |
| 86 | UINT8 Reserved4[0x48]; // 7e44h |
| 87 | UINT32 GdtBaseLoDword; // 7e8ch |
| 88 | UINT32 Reserved5; // 7e90h |
| 89 | UINT32 IdtBaseLoDword; // 7e94h |
| 90 | UINT32 Reserved6; // 7e98h |
| 91 | UINT32 LdtBaseLoDword; // 7e9ch |
| 92 | UINT8 Reserved7[0x38]; // 7ea0h |
| 93 | UINT64 EptVmxControl; // 7ed8h |
| 94 | UINT32 EnEptVmxControl; // 7ee0h |
| 95 | UINT8 Reserved8[0x14]; // 7ee4h |
| 96 | UINT32 SMBASE; // 7ef8h |
| 97 | UINT32 SMMRevId; // 7efch |
| 98 | UINT16 IORestart; // 7f00h |
| 99 | UINT16 AutoHALTRestart; // 7f02h |
| 100 | UINT8 Reserved9[0x18]; // 7f04h |
| 101 | UINT64 _R15; // 7f1ch |
| 102 | UINT64 _R14; |
| 103 | UINT64 _R13; |
| 104 | UINT64 _R12; |
| 105 | UINT64 _R11; |
| 106 | UINT64 _R10; |
| 107 | UINT64 _R9; |
| 108 | UINT64 _R8; |
| 109 | UINT64 _RAX; // 7f5ch |
| 110 | UINT64 _RCX; |
| 111 | UINT64 _RDX; |
| 112 | UINT64 _RBX; |
| 113 | UINT64 _RSP; |
| 114 | UINT64 _RBP; |
| 115 | UINT64 _RSI; |
| 116 | UINT64 _RDI; |
| 117 | UINT64 IOMemAddr; // 7f9ch |
| 118 | UINT32 IOMisc; // 7fa4h |
| 119 | UINT32 _ES; // 7fa8h |
| 120 | UINT32 _CS; |
| 121 | UINT32 _SS; |
| 122 | UINT32 _DS; |
| 123 | UINT32 _FS; |
| 124 | UINT32 _GS; |
| 125 | UINT32 _LDTR; // 7fc0h |
| 126 | UINT32 _TR; |
| 127 | UINT64 _DR7; // 7fc8h |
| 128 | UINT64 _DR6; |
| 129 | UINT64 _RIP; // 7fd8h |
| 130 | UINT64 IA32_EFER; // 7fe0h |
| 131 | UINT64 _RFLAGS; // 7fe8h |
| 132 | UINT64 _CR3; // 7ff0h |
| 133 | UINT64 _CR0; // 7ff8h |
| 134 | } SMRAM_SAVE_STATE_MAP64; |
| 135 | |
| 136 | /// |
| 137 | /// Union of 32-bit and 64-bit SMRAM Save State Maps |
| 138 | /// |
| 139 | typedef union { |
| 140 | SMRAM_SAVE_STATE_MAP32 x86; |
| 141 | SMRAM_SAVE_STATE_MAP64 x64; |
| 142 | } SMRAM_SAVE_STATE_MAP; |
| 143 | |
| 144 | /// |
| 145 | /// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map |
| 146 | /// |
| 147 | #define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004 |
| 148 | |
| 149 | /// |
| 150 | /// SMRAM Save State Map IOMisc I/O Length Values |
| 151 | /// |
| 152 | #define SMM_IO_LENGTH_BYTE 0x01 |
| 153 | #define SMM_IO_LENGTH_WORD 0x02 |
| 154 | #define SMM_IO_LENGTH_DWORD 0x04 |
| 155 | |
| 156 | /// |
| 157 | /// SMRAM Save State Map IOMisc I/O Instruction Type Values |
| 158 | /// |
| 159 | #define SMM_IO_TYPE_IN_IMMEDIATE 0x9 |
| 160 | #define SMM_IO_TYPE_IN_DX 0x1 |
| 161 | #define SMM_IO_TYPE_OUT_IMMEDIATE 0x8 |
| 162 | #define SMM_IO_TYPE_OUT_DX 0x0 |
| 163 | #define SMM_IO_TYPE_INS 0x3 |
| 164 | #define SMM_IO_TYPE_OUTS 0x2 |
| 165 | #define SMM_IO_TYPE_REP_INS 0x7 |
| 166 | #define SMM_IO_TYPE_REP_OUTS 0x6 |
| 167 | |
| 168 | /// |
| 169 | /// SMRAM Save State Map IOMisc structure |
| 170 | /// |
| 171 | typedef union { |
| 172 | struct { |
| 173 | UINT32 SmiFlag:1; |
| 174 | UINT32 Length:3; |
| 175 | UINT32 Type:4; |
| 176 | UINT32 Reserved1:8; |
| 177 | UINT32 Port:16; |
| 178 | } Bits; |
| 179 | UINT32 Uint32; |
| 180 | } SMRAM_SAVE_STATE_IOMISC; |
| 181 | |
| 182 | #pragma pack () |
| 183 | |
| 184 | #endif |