Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __SKYLAKE_MSR_H__ |
| 19 | #define __SKYLAKE_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is Intel processors based on the Skylake microarchitecture? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x06 && \ |
| 34 | ( \ |
| 35 | DisplayModel == 0x4E || \ |
| 36 | DisplayModel == 0x5E || \ |
| 37 | DisplayModel == 0x55 || \ |
| 38 | DisplayModel == 0x8E || \ |
| 39 | DisplayModel == 0x9E || \ |
| 40 | DisplayModel == 0x66 \ |
| 41 | ) \ |
| 42 | ) |
| 43 | |
| 44 | /** |
| 45 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, |
| 46 | RW if MSR_PLATFORM_INFO.[28] = 1. |
| 47 | |
| 48 | @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD) |
| 49 | @param EAX Lower 32-bits of MSR value. |
| 50 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. |
| 51 | @param EDX Upper 32-bits of MSR value. |
| 52 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. |
| 53 | |
| 54 | <b>Example usage</b> |
| 55 | @code |
| 56 | MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr; |
| 57 | |
| 58 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT); |
| 59 | @endcode |
| 60 | @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. |
| 61 | **/ |
| 62 | #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD |
| 63 | |
| 64 | /** |
| 65 | MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT |
| 66 | **/ |
| 67 | typedef union { |
| 68 | /// |
| 69 | /// Individual bit fields |
| 70 | /// |
| 71 | struct { |
| 72 | /// |
| 73 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio |
| 74 | /// limit of 1 core active. |
| 75 | /// |
| 76 | UINT32 Maximum1C:8; |
| 77 | /// |
| 78 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio |
| 79 | /// limit of 2 core active. |
| 80 | /// |
| 81 | UINT32 Maximum2C:8; |
| 82 | /// |
| 83 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio |
| 84 | /// limit of 3 core active. |
| 85 | /// |
| 86 | UINT32 Maximum3C:8; |
| 87 | /// |
| 88 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio |
| 89 | /// limit of 4 core active. |
| 90 | /// |
| 91 | UINT32 Maximum4C:8; |
| 92 | UINT32 Reserved:32; |
| 93 | } Bits; |
| 94 | /// |
| 95 | /// All bit fields as a 32-bit value |
| 96 | /// |
| 97 | UINT32 Uint32; |
| 98 | /// |
| 99 | /// All bit fields as a 64-bit value |
| 100 | /// |
| 101 | UINT64 Uint64; |
| 102 | } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER; |
| 103 | |
| 104 | |
| 105 | /** |
| 106 | Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) |
| 107 | that points to the MSR containing the most recent branch record. |
| 108 | |
| 109 | @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9) |
| 110 | @param EAX Lower 32-bits of MSR value. |
| 111 | @param EDX Upper 32-bits of MSR value. |
| 112 | |
| 113 | <b>Example usage</b> |
| 114 | @code |
| 115 | UINT64 Msr; |
| 116 | |
| 117 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS); |
| 118 | AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr); |
| 119 | @endcode |
| 120 | @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. |
| 121 | **/ |
| 122 | #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9 |
| 123 | |
| 124 | |
| 125 | /** |
| 126 | Core. Power Control Register See http://biosbits.org. |
| 127 | |
| 128 | @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC) |
| 129 | @param EAX Lower 32-bits of MSR value. |
| 130 | Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. |
| 131 | @param EDX Upper 32-bits of MSR value. |
| 132 | Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. |
| 133 | |
| 134 | <b>Example usage</b> |
| 135 | @code |
| 136 | MSR_SKYLAKE_POWER_CTL_REGISTER Msr; |
| 137 | |
| 138 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL); |
| 139 | AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64); |
| 140 | @endcode |
| 141 | **/ |
| 142 | #define MSR_SKYLAKE_POWER_CTL 0x000001FC |
| 143 | |
| 144 | /** |
| 145 | MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL |
| 146 | **/ |
| 147 | typedef union { |
| 148 | /// |
| 149 | /// Individual bit fields |
| 150 | /// |
| 151 | struct { |
| 152 | UINT32 Reserved1:1; |
| 153 | /// |
| 154 | /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU |
| 155 | /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating |
| 156 | /// point when all execution cores enter MWAIT (C1). |
| 157 | /// |
| 158 | UINT32 C1EEnable:1; |
| 159 | UINT32 Reserved2:17; |
| 160 | /// |
| 161 | /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit |
| 162 | /// disables the Race to Halt optimization and avoids this optimization |
| 163 | /// limitation to execute below the most efficient frequency ratio. |
| 164 | /// Default value is 0 for processors that support Race to Halt |
| 165 | /// optimization. Default value is 1 for processors that do not support |
| 166 | /// Race to Halt optimization. |
| 167 | /// |
| 168 | UINT32 Fix_Me_1:1; |
| 169 | /// |
| 170 | /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit |
| 171 | /// disables the P-States energy efficiency optimization. Default value is |
| 172 | /// 0. Disable/enable the energy efficiency optimization in P-State legacy |
| 173 | /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the |
| 174 | /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP |
| 175 | /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS |
| 176 | /// desired or OS maximize to the OS minimize performance setting. |
| 177 | /// |
| 178 | UINT32 DisableEnergyEfficiencyOptimization:1; |
| 179 | UINT32 Reserved3:11; |
| 180 | UINT32 Reserved4:32; |
| 181 | } Bits; |
| 182 | /// |
| 183 | /// All bit fields as a 32-bit value |
| 184 | /// |
| 185 | UINT32 Uint32; |
| 186 | /// |
| 187 | /// All bit fields as a 64-bit value |
| 188 | /// |
| 189 | UINT64 Uint64; |
| 190 | } MSR_SKYLAKE_POWER_CTL_REGISTER; |
| 191 | |
| 192 | |
| 193 | /** |
| 194 | Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update |
| 195 | CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in |
| 196 | the package. Lower 64 bits of an 128-bit external entropy value for key |
| 197 | derivation of an enclave. |
| 198 | |
| 199 | @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300) |
| 200 | @param EAX Lower 32-bits of MSR value. |
| 201 | @param EDX Upper 32-bits of MSR value. |
| 202 | |
| 203 | <b>Example usage</b> |
| 204 | @code |
| 205 | UINT64 Msr; |
| 206 | |
| 207 | Msr = 0; |
| 208 | AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr); |
| 209 | @endcode |
| 210 | @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM. |
| 211 | **/ |
| 212 | #define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300 |
| 213 | |
| 214 | // |
| 215 | // Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM. |
| 216 | // |
| 217 | #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 |
| 218 | /** |
| 219 | Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update |
| 220 | CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in |
| 221 | the package. Upper 64 bits of an 128-bit external entropy value for key |
| 222 | derivation of an enclave. |
| 223 | |
| 224 | @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301) |
| 225 | @param EAX Lower 32-bits of MSR value. |
| 226 | @param EDX Upper 32-bits of MSR value. |
| 227 | |
| 228 | <b>Example usage</b> |
| 229 | @code |
| 230 | UINT64 Msr; |
| 231 | |
| 232 | Msr = 0; |
| 233 | AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr); |
| 234 | @endcode |
| 235 | @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM. |
| 236 | **/ |
| 237 | #define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301 |
| 238 | |
| 239 | // |
| 240 | // Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM. |
| 241 | // |
| 242 | #define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1 |
| 243 | |
| 244 | |
| 245 | /** |
| 246 | See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring |
| 247 | Version 4.". |
| 248 | |
| 249 | @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E) |
| 250 | @param EAX Lower 32-bits of MSR value. |
| 251 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. |
| 252 | @param EDX Upper 32-bits of MSR value. |
| 253 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. |
| 254 | |
| 255 | <b>Example usage</b> |
| 256 | @code |
| 257 | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; |
| 258 | |
| 259 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS); |
| 260 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); |
| 261 | @endcode |
| 262 | @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. |
| 263 | **/ |
| 264 | #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E |
| 265 | |
| 266 | /** |
| 267 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS |
| 268 | **/ |
| 269 | typedef union { |
| 270 | /// |
| 271 | /// Individual bit fields |
| 272 | /// |
| 273 | struct { |
| 274 | /// |
| 275 | /// [Bit 0] Thread. Ovf_PMC0. |
| 276 | /// |
| 277 | UINT32 Ovf_PMC0:1; |
| 278 | /// |
| 279 | /// [Bit 1] Thread. Ovf_PMC1. |
| 280 | /// |
| 281 | UINT32 Ovf_PMC1:1; |
| 282 | /// |
| 283 | /// [Bit 2] Thread. Ovf_PMC2. |
| 284 | /// |
| 285 | UINT32 Ovf_PMC2:1; |
| 286 | /// |
| 287 | /// [Bit 3] Thread. Ovf_PMC3. |
| 288 | /// |
| 289 | UINT32 Ovf_PMC3:1; |
| 290 | /// |
| 291 | /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). |
| 292 | /// |
| 293 | UINT32 Ovf_PMC4:1; |
| 294 | /// |
| 295 | /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). |
| 296 | /// |
| 297 | UINT32 Ovf_PMC5:1; |
| 298 | /// |
| 299 | /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). |
| 300 | /// |
| 301 | UINT32 Ovf_PMC6:1; |
| 302 | /// |
| 303 | /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). |
| 304 | /// |
| 305 | UINT32 Ovf_PMC7:1; |
| 306 | UINT32 Reserved1:24; |
| 307 | /// |
| 308 | /// [Bit 32] Thread. Ovf_FixedCtr0. |
| 309 | /// |
| 310 | UINT32 Ovf_FixedCtr0:1; |
| 311 | /// |
| 312 | /// [Bit 33] Thread. Ovf_FixedCtr1. |
| 313 | /// |
| 314 | UINT32 Ovf_FixedCtr1:1; |
| 315 | /// |
| 316 | /// [Bit 34] Thread. Ovf_FixedCtr2. |
| 317 | /// |
| 318 | UINT32 Ovf_FixedCtr2:1; |
| 319 | UINT32 Reserved2:20; |
| 320 | /// |
| 321 | /// [Bit 55] Thread. Trace_ToPA_PMI. |
| 322 | /// |
| 323 | UINT32 Trace_ToPA_PMI:1; |
| 324 | UINT32 Reserved3:2; |
| 325 | /// |
| 326 | /// [Bit 58] Thread. LBR_Frz. |
| 327 | /// |
| 328 | UINT32 LBR_Frz:1; |
| 329 | /// |
| 330 | /// [Bit 59] Thread. CTR_Frz. |
| 331 | /// |
| 332 | UINT32 CTR_Frz:1; |
| 333 | /// |
| 334 | /// [Bit 60] Thread. ASCI. |
| 335 | /// |
| 336 | UINT32 ASCI:1; |
| 337 | /// |
| 338 | /// [Bit 61] Thread. Ovf_Uncore. |
| 339 | /// |
| 340 | UINT32 Ovf_Uncore:1; |
| 341 | /// |
| 342 | /// [Bit 62] Thread. Ovf_BufDSSAVE. |
| 343 | /// |
| 344 | UINT32 Ovf_BufDSSAVE:1; |
| 345 | /// |
| 346 | /// [Bit 63] Thread. CondChgd. |
| 347 | /// |
| 348 | UINT32 CondChgd:1; |
| 349 | } Bits; |
| 350 | /// |
| 351 | /// All bit fields as a 64-bit value |
| 352 | /// |
| 353 | UINT64 Uint64; |
| 354 | } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER; |
| 355 | |
| 356 | |
| 357 | /** |
| 358 | See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring |
| 359 | Version 4.". |
| 360 | |
| 361 | @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) |
| 362 | @param EAX Lower 32-bits of MSR value. |
| 363 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. |
| 364 | @param EDX Upper 32-bits of MSR value. |
| 365 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. |
| 366 | |
| 367 | <b>Example usage</b> |
| 368 | @code |
| 369 | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; |
| 370 | |
| 371 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET); |
| 372 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); |
| 373 | @endcode |
| 374 | @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. |
| 375 | **/ |
| 376 | #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 |
| 377 | |
| 378 | /** |
| 379 | MSR information returned for MSR index |
| 380 | #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET |
| 381 | **/ |
| 382 | typedef union { |
| 383 | /// |
| 384 | /// Individual bit fields |
| 385 | /// |
| 386 | struct { |
| 387 | /// |
| 388 | /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0. |
| 389 | /// |
| 390 | UINT32 Ovf_PMC0:1; |
| 391 | /// |
| 392 | /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1. |
| 393 | /// |
| 394 | UINT32 Ovf_PMC1:1; |
| 395 | /// |
| 396 | /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2. |
| 397 | /// |
| 398 | UINT32 Ovf_PMC2:1; |
| 399 | /// |
| 400 | /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3. |
| 401 | /// |
| 402 | UINT32 Ovf_PMC3:1; |
| 403 | /// |
| 404 | /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). |
| 405 | /// |
| 406 | UINT32 Ovf_PMC4:1; |
| 407 | /// |
| 408 | /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). |
| 409 | /// |
| 410 | UINT32 Ovf_PMC5:1; |
| 411 | /// |
| 412 | /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). |
| 413 | /// |
| 414 | UINT32 Ovf_PMC6:1; |
| 415 | /// |
| 416 | /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). |
| 417 | /// |
| 418 | UINT32 Ovf_PMC7:1; |
| 419 | UINT32 Reserved1:24; |
| 420 | /// |
| 421 | /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0. |
| 422 | /// |
| 423 | UINT32 Ovf_FixedCtr0:1; |
| 424 | /// |
| 425 | /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1. |
| 426 | /// |
| 427 | UINT32 Ovf_FixedCtr1:1; |
| 428 | /// |
| 429 | /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2. |
| 430 | /// |
| 431 | UINT32 Ovf_FixedCtr2:1; |
| 432 | UINT32 Reserved2:20; |
| 433 | /// |
| 434 | /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI. |
| 435 | /// |
| 436 | UINT32 Trace_ToPA_PMI:1; |
| 437 | UINT32 Reserved3:2; |
| 438 | /// |
| 439 | /// [Bit 58] Thread. Set 1 to clear LBR_Frz. |
| 440 | /// |
| 441 | UINT32 LBR_Frz:1; |
| 442 | /// |
| 443 | /// [Bit 59] Thread. Set 1 to clear CTR_Frz. |
| 444 | /// |
| 445 | UINT32 CTR_Frz:1; |
| 446 | /// |
| 447 | /// [Bit 60] Thread. Set 1 to clear ASCI. |
| 448 | /// |
| 449 | UINT32 ASCI:1; |
| 450 | /// |
| 451 | /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore. |
| 452 | /// |
| 453 | UINT32 Ovf_Uncore:1; |
| 454 | /// |
| 455 | /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE. |
| 456 | /// |
| 457 | UINT32 Ovf_BufDSSAVE:1; |
| 458 | /// |
| 459 | /// [Bit 63] Thread. Set 1 to clear CondChgd. |
| 460 | /// |
| 461 | UINT32 CondChgd:1; |
| 462 | } Bits; |
| 463 | /// |
| 464 | /// All bit fields as a 64-bit value |
| 465 | /// |
| 466 | UINT64 Uint64; |
| 467 | } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; |
| 468 | |
| 469 | |
| 470 | /** |
| 471 | See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring |
| 472 | Version 4.". |
| 473 | |
| 474 | @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) |
| 475 | @param EAX Lower 32-bits of MSR value. |
| 476 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. |
| 477 | @param EDX Upper 32-bits of MSR value. |
| 478 | Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. |
| 479 | |
| 480 | <b>Example usage</b> |
| 481 | @code |
| 482 | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; |
| 483 | |
| 484 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET); |
| 485 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); |
| 486 | @endcode |
| 487 | @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. |
| 488 | **/ |
| 489 | #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 |
| 490 | |
| 491 | /** |
| 492 | MSR information returned for MSR index |
| 493 | #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET |
| 494 | **/ |
| 495 | typedef union { |
| 496 | /// |
| 497 | /// Individual bit fields |
| 498 | /// |
| 499 | struct { |
| 500 | /// |
| 501 | /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1. |
| 502 | /// |
| 503 | UINT32 Ovf_PMC0:1; |
| 504 | /// |
| 505 | /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1. |
| 506 | /// |
| 507 | UINT32 Ovf_PMC1:1; |
| 508 | /// |
| 509 | /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1. |
| 510 | /// |
| 511 | UINT32 Ovf_PMC2:1; |
| 512 | /// |
| 513 | /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1. |
| 514 | /// |
| 515 | UINT32 Ovf_PMC3:1; |
| 516 | /// |
| 517 | /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4). |
| 518 | /// |
| 519 | UINT32 Ovf_PMC4:1; |
| 520 | /// |
| 521 | /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5). |
| 522 | /// |
| 523 | UINT32 Ovf_PMC5:1; |
| 524 | /// |
| 525 | /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6). |
| 526 | /// |
| 527 | UINT32 Ovf_PMC6:1; |
| 528 | /// |
| 529 | /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7). |
| 530 | /// |
| 531 | UINT32 Ovf_PMC7:1; |
| 532 | UINT32 Reserved1:24; |
| 533 | /// |
| 534 | /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1. |
| 535 | /// |
| 536 | UINT32 Ovf_FixedCtr0:1; |
| 537 | /// |
| 538 | /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1. |
| 539 | /// |
| 540 | UINT32 Ovf_FixedCtr1:1; |
| 541 | /// |
| 542 | /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1. |
| 543 | /// |
| 544 | UINT32 Ovf_FixedCtr2:1; |
| 545 | UINT32 Reserved2:20; |
| 546 | /// |
| 547 | /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1. |
| 548 | /// |
| 549 | UINT32 Trace_ToPA_PMI:1; |
| 550 | UINT32 Reserved3:2; |
| 551 | /// |
| 552 | /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1. |
| 553 | /// |
| 554 | UINT32 LBR_Frz:1; |
| 555 | /// |
| 556 | /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1. |
| 557 | /// |
| 558 | UINT32 CTR_Frz:1; |
| 559 | /// |
| 560 | /// [Bit 60] Thread. Set 1 to cause ASCI = 1. |
| 561 | /// |
| 562 | UINT32 ASCI:1; |
| 563 | /// |
| 564 | /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore. |
| 565 | /// |
| 566 | UINT32 Ovf_Uncore:1; |
| 567 | /// |
| 568 | /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE. |
| 569 | /// |
| 570 | UINT32 Ovf_BufDSSAVE:1; |
| 571 | UINT32 Reserved4:1; |
| 572 | } Bits; |
| 573 | /// |
| 574 | /// All bit fields as a 64-bit value |
| 575 | /// |
| 576 | UINT64 Uint64; |
| 577 | } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; |
| 578 | |
| 579 | |
| 580 | /** |
| 581 | Thread. FrontEnd Precise Event Condition Select (R/W). |
| 582 | |
| 583 | @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7) |
| 584 | @param EAX Lower 32-bits of MSR value. |
| 585 | Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. |
| 586 | @param EDX Upper 32-bits of MSR value. |
| 587 | Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. |
| 588 | |
| 589 | <b>Example usage</b> |
| 590 | @code |
| 591 | MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr; |
| 592 | |
| 593 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND); |
| 594 | AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64); |
| 595 | @endcode |
| 596 | @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM. |
| 597 | **/ |
| 598 | #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7 |
| 599 | |
| 600 | /** |
| 601 | MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND |
| 602 | **/ |
| 603 | typedef union { |
| 604 | /// |
| 605 | /// Individual bit fields |
| 606 | /// |
| 607 | struct { |
| 608 | /// |
| 609 | /// [Bits 2:0] Event Code Select. |
| 610 | /// |
| 611 | UINT32 EventCodeSelect:3; |
| 612 | UINT32 Reserved1:1; |
| 613 | /// |
| 614 | /// [Bit 4] Event Code Select High. |
| 615 | /// |
| 616 | UINT32 EventCodeSelectHigh:1; |
| 617 | UINT32 Reserved2:3; |
| 618 | /// |
| 619 | /// [Bits 19:8] IDQ_Bubble_Length Specifier. |
| 620 | /// |
| 621 | UINT32 IDQ_Bubble_Length:12; |
| 622 | /// |
| 623 | /// [Bits 22:20] IDQ_Bubble_Width Specifier. |
| 624 | /// |
| 625 | UINT32 IDQ_Bubble_Width:3; |
| 626 | UINT32 Reserved3:9; |
| 627 | UINT32 Reserved4:32; |
| 628 | } Bits; |
| 629 | /// |
| 630 | /// All bit fields as a 32-bit value |
| 631 | /// |
| 632 | UINT32 Uint32; |
| 633 | /// |
| 634 | /// All bit fields as a 64-bit value |
| 635 | /// |
| 636 | UINT64 Uint64; |
| 637 | } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER; |
| 638 | |
| 639 | |
| 640 | /** |
| 641 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL |
| 642 | Domains.". |
| 643 | |
| 644 | @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) |
| 645 | @param EAX Lower 32-bits of MSR value. |
| 646 | @param EDX Upper 32-bits of MSR value. |
| 647 | |
| 648 | <b>Example usage</b> |
| 649 | @code |
| 650 | UINT64 Msr; |
| 651 | |
| 652 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS); |
| 653 | @endcode |
| 654 | @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. |
| 655 | **/ |
| 656 | #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639 |
| 657 | |
| 658 | |
| 659 | /** |
| 660 | Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both |
| 661 | platform vendor hardware implementation and BIOS enablement support it. This |
| 662 | MSR will read 0 if not valid. |
| 663 | |
| 664 | @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D) |
| 665 | @param EAX Lower 32-bits of MSR value. |
| 666 | Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. |
| 667 | @param EDX Upper 32-bits of MSR value. |
| 668 | Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. |
| 669 | |
| 670 | <b>Example usage</b> |
| 671 | @code |
| 672 | MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr; |
| 673 | |
| 674 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER); |
| 675 | @endcode |
| 676 | @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM. |
| 677 | **/ |
| 678 | #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D |
| 679 | |
| 680 | /** |
| 681 | MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER |
| 682 | **/ |
| 683 | typedef union { |
| 684 | /// |
| 685 | /// Individual bit fields |
| 686 | /// |
| 687 | struct { |
| 688 | /// |
| 689 | /// [Bits 31:0] Total energy consumed by all devices in the platform that |
| 690 | /// receive power from integrated power delivery mechanism, Included |
| 691 | /// platform devices are processor cores, SOC, memory, add-on or |
| 692 | /// peripheral devices that get powered directly from the platform power |
| 693 | /// delivery means. The energy units are specified in the |
| 694 | /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit. |
| 695 | /// |
| 696 | UINT32 TotalEnergy:32; |
| 697 | UINT32 Reserved:32; |
| 698 | } Bits; |
| 699 | /// |
| 700 | /// All bit fields as a 32-bit value |
| 701 | /// |
| 702 | UINT32 Uint32; |
| 703 | /// |
| 704 | /// All bit fields as a 64-bit value |
| 705 | /// |
| 706 | UINT64 Uint64; |
| 707 | } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER; |
| 708 | |
| 709 | |
| 710 | /** |
| 711 | Thread. Productive Performance Count. (R/O). Hardware's view of workload |
| 712 | scalability. See Section 14.4.5.1. |
| 713 | |
| 714 | @param ECX MSR_SKYLAKE_PPERF (0x0000064E) |
| 715 | @param EAX Lower 32-bits of MSR value. |
| 716 | @param EDX Upper 32-bits of MSR value. |
| 717 | |
| 718 | <b>Example usage</b> |
| 719 | @code |
| 720 | UINT64 Msr; |
| 721 | |
| 722 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF); |
| 723 | @endcode |
| 724 | @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM. |
| 725 | **/ |
| 726 | #define MSR_SKYLAKE_PPERF 0x0000064E |
| 727 | |
| 728 | |
| 729 | /** |
| 730 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency |
| 731 | refers to processor core frequency). |
| 732 | |
| 733 | @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F) |
| 734 | @param EAX Lower 32-bits of MSR value. |
| 735 | Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. |
| 736 | @param EDX Upper 32-bits of MSR value. |
| 737 | Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. |
| 738 | |
| 739 | <b>Example usage</b> |
| 740 | @code |
| 741 | MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr; |
| 742 | |
| 743 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS); |
| 744 | AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64); |
| 745 | @endcode |
| 746 | @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. |
| 747 | **/ |
| 748 | #define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F |
| 749 | |
| 750 | /** |
| 751 | MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS |
| 752 | **/ |
| 753 | typedef union { |
| 754 | /// |
| 755 | /// Individual bit fields |
| 756 | /// |
| 757 | struct { |
| 758 | /// |
| 759 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the |
| 760 | /// operating system request due to assertion of external PROCHOT. |
| 761 | /// |
| 762 | UINT32 PROCHOT_Status:1; |
| 763 | /// |
| 764 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the |
| 765 | /// operating system request due to a thermal event. |
| 766 | /// |
| 767 | UINT32 ThermalStatus:1; |
| 768 | UINT32 Reserved1:2; |
| 769 | /// |
| 770 | /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is |
| 771 | /// reduced below the operating system request due to residency state |
| 772 | /// regulation limit. |
| 773 | /// |
| 774 | UINT32 ResidencyStateRegulationStatus:1; |
| 775 | /// |
| 776 | /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency |
| 777 | /// is reduced below the operating system request due to Running Average |
| 778 | /// Thermal Limit (RATL). |
| 779 | /// |
| 780 | UINT32 RunningAverageThermalLimitStatus:1; |
| 781 | /// |
| 782 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced |
| 783 | /// below the operating system request due to a thermal alert from a |
| 784 | /// processor Voltage Regulator (VR). |
| 785 | /// |
| 786 | UINT32 VRThermAlertStatus:1; |
| 787 | /// |
| 788 | /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is |
| 789 | /// reduced below the operating system request due to VR thermal design |
| 790 | /// current limit. |
| 791 | /// |
| 792 | UINT32 VRThermDesignCurrentStatus:1; |
| 793 | /// |
| 794 | /// [Bit 8] Other Status (R0) When set, frequency is reduced below the |
| 795 | /// operating system request due to electrical or other constraints. |
| 796 | /// |
| 797 | UINT32 OtherStatus:1; |
| 798 | UINT32 Reserved2:1; |
| 799 | /// |
| 800 | /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When |
| 801 | /// set, frequency is reduced below the operating system request due to |
| 802 | /// package/platform-level power limiting PL1. |
| 803 | /// |
| 804 | UINT32 PL1Status:1; |
| 805 | /// |
| 806 | /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When |
| 807 | /// set, frequency is reduced below the operating system request due to |
| 808 | /// package/platform-level power limiting PL2/PL3. |
| 809 | /// |
| 810 | UINT32 PL2Status:1; |
| 811 | /// |
| 812 | /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced |
| 813 | /// below the operating system request due to multi-core turbo limits. |
| 814 | /// |
| 815 | UINT32 MaxTurboLimitStatus:1; |
| 816 | /// |
| 817 | /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency |
| 818 | /// is reduced below the operating system request due to Turbo transition |
| 819 | /// attenuation. This prevents performance degradation due to frequent |
| 820 | /// operating ratio changes. |
| 821 | /// |
| 822 | UINT32 TurboTransitionAttenuationStatus:1; |
| 823 | UINT32 Reserved3:2; |
| 824 | /// |
| 825 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit |
| 826 | /// has asserted since the log bit was last cleared. This log bit will |
| 827 | /// remain set until cleared by software writing 0. |
| 828 | /// |
| 829 | UINT32 PROCHOT_Log:1; |
| 830 | /// |
| 831 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit |
| 832 | /// has asserted since the log bit was last cleared. This log bit will |
| 833 | /// remain set until cleared by software writing 0. |
| 834 | /// |
| 835 | UINT32 ThermalLog:1; |
| 836 | UINT32 Reserved4:2; |
| 837 | /// |
| 838 | /// [Bit 20] Residency State Regulation Log When set, indicates that the |
| 839 | /// Residency State Regulation Status bit has asserted since the log bit |
| 840 | /// was last cleared. This log bit will remain set until cleared by |
| 841 | /// software writing 0. |
| 842 | /// |
| 843 | UINT32 ResidencyStateRegulationLog:1; |
| 844 | /// |
| 845 | /// [Bit 21] Running Average Thermal Limit Log When set, indicates that |
| 846 | /// the RATL Status bit has asserted since the log bit was last cleared. |
| 847 | /// This log bit will remain set until cleared by software writing 0. |
| 848 | /// |
| 849 | UINT32 RunningAverageThermalLimitLog:1; |
| 850 | /// |
| 851 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm |
| 852 | /// Alert Status bit has asserted since the log bit was last cleared. This |
| 853 | /// log bit will remain set until cleared by software writing 0. |
| 854 | /// |
| 855 | UINT32 VRThermAlertLog:1; |
| 856 | /// |
| 857 | /// [Bit 23] VR Thermal Design Current Log When set, indicates that the |
| 858 | /// VR TDC Status bit has asserted since the log bit was last cleared. |
| 859 | /// This log bit will remain set until cleared by software writing 0. |
| 860 | /// |
| 861 | UINT32 VRThermalDesignCurrentLog:1; |
| 862 | /// |
| 863 | /// [Bit 24] Other Log When set, indicates that the Other Status bit has |
| 864 | /// asserted since the log bit was last cleared. This log bit will remain |
| 865 | /// set until cleared by software writing 0. |
| 866 | /// |
| 867 | UINT32 OtherLog:1; |
| 868 | UINT32 Reserved5:1; |
| 869 | /// |
| 870 | /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, |
| 871 | /// indicates that the Package or Platform Level PL1 Power Limiting Status |
| 872 | /// bit has asserted since the log bit was last cleared. This log bit will |
| 873 | /// remain set until cleared by software writing 0. |
| 874 | /// |
| 875 | UINT32 PL1Log:1; |
| 876 | /// |
| 877 | /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, |
| 878 | /// indicates that the Package or Platform Level PL2/PL3 Power Limiting |
| 879 | /// Status bit has asserted since the log bit was last cleared. This log |
| 880 | /// bit will remain set until cleared by software writing 0. |
| 881 | /// |
| 882 | UINT32 PL2Log:1; |
| 883 | /// |
| 884 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo |
| 885 | /// Limit Status bit has asserted since the log bit was last cleared. This |
| 886 | /// log bit will remain set until cleared by software writing 0. |
| 887 | /// |
| 888 | UINT32 MaxTurboLimitLog:1; |
| 889 | /// |
| 890 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the |
| 891 | /// Turbo Transition Attenuation Status bit has asserted since the log bit |
| 892 | /// was last cleared. This log bit will remain set until cleared by |
| 893 | /// software writing 0. |
| 894 | /// |
| 895 | UINT32 TurboTransitionAttenuationLog:1; |
| 896 | UINT32 Reserved6:2; |
| 897 | UINT32 Reserved7:32; |
| 898 | } Bits; |
| 899 | /// |
| 900 | /// All bit fields as a 32-bit value |
| 901 | /// |
| 902 | UINT32 Uint32; |
| 903 | /// |
| 904 | /// All bit fields as a 64-bit value |
| 905 | /// |
| 906 | UINT64 Uint64; |
| 907 | } MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER; |
| 908 | |
| 909 | |
| 910 | /** |
| 911 | Package. HDC Configuration (R/W).. |
| 912 | |
| 913 | @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652) |
| 914 | @param EAX Lower 32-bits of MSR value. |
| 915 | Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. |
| 916 | @param EDX Upper 32-bits of MSR value. |
| 917 | Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. |
| 918 | |
| 919 | <b>Example usage</b> |
| 920 | @code |
| 921 | MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr; |
| 922 | |
| 923 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG); |
| 924 | AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64); |
| 925 | @endcode |
| 926 | @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM. |
| 927 | **/ |
| 928 | #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652 |
| 929 | |
| 930 | /** |
| 931 | MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG |
| 932 | **/ |
| 933 | typedef union { |
| 934 | /// |
| 935 | /// Individual bit fields |
| 936 | /// |
| 937 | struct { |
| 938 | /// |
| 939 | /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for |
| 940 | /// MSR_PKG_HDC_DEEP_RESIDENCY. |
| 941 | /// |
| 942 | UINT32 PKG_Cx_Monitor:3; |
| 943 | UINT32 Reserved1:29; |
| 944 | UINT32 Reserved2:32; |
| 945 | } Bits; |
| 946 | /// |
| 947 | /// All bit fields as a 32-bit value |
| 948 | /// |
| 949 | UINT32 Uint32; |
| 950 | /// |
| 951 | /// All bit fields as a 64-bit value |
| 952 | /// |
| 953 | UINT64 Uint64; |
| 954 | } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER; |
| 955 | |
| 956 | |
| 957 | /** |
| 958 | Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt. |
| 959 | |
| 960 | @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653) |
| 961 | @param EAX Lower 32-bits of MSR value. |
| 962 | @param EDX Upper 32-bits of MSR value. |
| 963 | |
| 964 | <b>Example usage</b> |
| 965 | @code |
| 966 | UINT64 Msr; |
| 967 | |
| 968 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY); |
| 969 | @endcode |
| 970 | @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM. |
| 971 | **/ |
| 972 | #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653 |
| 973 | |
| 974 | |
| 975 | /** |
| 976 | Package. Accumulate the cycles the package was in C2 state and at least one |
| 977 | logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt. |
| 978 | |
| 979 | @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655) |
| 980 | @param EAX Lower 32-bits of MSR value. |
| 981 | @param EDX Upper 32-bits of MSR value. |
| 982 | |
| 983 | <b>Example usage</b> |
| 984 | @code |
| 985 | UINT64 Msr; |
| 986 | |
| 987 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY); |
| 988 | @endcode |
| 989 | @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM. |
| 990 | **/ |
| 991 | #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655 |
| 992 | |
| 993 | |
| 994 | /** |
| 995 | Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt. |
| 996 | |
| 997 | @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656) |
| 998 | @param EAX Lower 32-bits of MSR value. |
| 999 | @param EDX Upper 32-bits of MSR value. |
| 1000 | |
| 1001 | <b>Example usage</b> |
| 1002 | @code |
| 1003 | UINT64 Msr; |
| 1004 | |
| 1005 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY); |
| 1006 | @endcode |
| 1007 | @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM. |
| 1008 | **/ |
| 1009 | #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656 |
| 1010 | |
| 1011 | |
| 1012 | /** |
| 1013 | Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate |
| 1014 | as the TSC. The increment each cycle is weighted by the number of processor |
| 1015 | cores in the package that reside in C0. If N cores are simultaneously in C0, |
| 1016 | then each cycle the counter increments by N. |
| 1017 | |
| 1018 | @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658) |
| 1019 | @param EAX Lower 32-bits of MSR value. |
| 1020 | @param EDX Upper 32-bits of MSR value. |
| 1021 | |
| 1022 | <b>Example usage</b> |
| 1023 | @code |
| 1024 | UINT64 Msr; |
| 1025 | |
| 1026 | Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0); |
| 1027 | @endcode |
| 1028 | @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM. |
| 1029 | **/ |
| 1030 | #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658 |
| 1031 | |
| 1032 | |
| 1033 | /** |
| 1034 | Package. Any Core C0 Residency. (R/O). Increment at the same rate as the |
| 1035 | TSC. The increment each cycle is one if any processor core in the package is |
| 1036 | in C0. |
| 1037 | |
| 1038 | @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659) |
| 1039 | @param EAX Lower 32-bits of MSR value. |
| 1040 | @param EDX Upper 32-bits of MSR value. |
| 1041 | |
| 1042 | <b>Example usage</b> |
| 1043 | @code |
| 1044 | UINT64 Msr; |
| 1045 | |
| 1046 | Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0); |
| 1047 | @endcode |
| 1048 | @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM. |
| 1049 | **/ |
| 1050 | #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659 |
| 1051 | |
| 1052 | |
| 1053 | /** |
| 1054 | Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate |
| 1055 | as the TSC. The increment each cycle is one if any processor graphic |
| 1056 | device's compute engines are in C0. |
| 1057 | |
| 1058 | @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A) |
| 1059 | @param EAX Lower 32-bits of MSR value. |
| 1060 | @param EDX Upper 32-bits of MSR value. |
| 1061 | |
| 1062 | <b>Example usage</b> |
| 1063 | @code |
| 1064 | UINT64 Msr; |
| 1065 | |
| 1066 | Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0); |
| 1067 | @endcode |
| 1068 | @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM. |
| 1069 | **/ |
| 1070 | #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A |
| 1071 | |
| 1072 | |
| 1073 | /** |
| 1074 | Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment |
| 1075 | at the same rate as the TSC. The increment each cycle is one if at least one |
| 1076 | compute engine of the processor graphics is in C0 and at least one processor |
| 1077 | core in the package is also in C0. |
| 1078 | |
| 1079 | @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B) |
| 1080 | @param EAX Lower 32-bits of MSR value. |
| 1081 | @param EDX Upper 32-bits of MSR value. |
| 1082 | |
| 1083 | <b>Example usage</b> |
| 1084 | @code |
| 1085 | UINT64 Msr; |
| 1086 | |
| 1087 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0); |
| 1088 | @endcode |
| 1089 | @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM. |
| 1090 | **/ |
| 1091 | #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B |
| 1092 | |
| 1093 | |
| 1094 | /** |
| 1095 | Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to |
| 1096 | limit power consumption of the platform devices to the specified values. The |
| 1097 | Long Duration power consumption is specified via Platform_Power_Limit_1 and |
| 1098 | Platform_Power_Limit_1_Time. The Short Duration power consumption limit is |
| 1099 | specified via the Platform_Power_Limit_2 with duration chosen by the |
| 1100 | processor. The processor implements an exponential-weighted algorithm in the |
| 1101 | placement of the time windows. |
| 1102 | |
| 1103 | @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C) |
| 1104 | @param EAX Lower 32-bits of MSR value. |
| 1105 | Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. |
| 1106 | @param EDX Upper 32-bits of MSR value. |
| 1107 | Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. |
| 1108 | |
| 1109 | <b>Example usage</b> |
| 1110 | @code |
| 1111 | MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr; |
| 1112 | |
| 1113 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT); |
| 1114 | AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64); |
| 1115 | @endcode |
| 1116 | @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM. |
| 1117 | **/ |
| 1118 | #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C |
| 1119 | |
| 1120 | /** |
| 1121 | MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT |
| 1122 | **/ |
| 1123 | typedef union { |
| 1124 | /// |
| 1125 | /// Individual bit fields |
| 1126 | /// |
| 1127 | struct { |
| 1128 | /// |
| 1129 | /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which |
| 1130 | /// the platform must not exceed over a time window as specified by |
| 1131 | /// Power_Limit_1_TIME field. The default value is the Thermal Design |
| 1132 | /// Power (TDP) and varies with product skus. The unit is specified in |
| 1133 | /// MSR_RAPLPOWER_UNIT. |
| 1134 | /// |
| 1135 | UINT32 PlatformPowerLimit1:15; |
| 1136 | /// |
| 1137 | /// [Bit 15] Enable Platform Power Limit #1. When set, enables the |
| 1138 | /// processor to apply control policy such that the platform power does |
| 1139 | /// not exceed Platform Power limit #1 over the time window specified by |
| 1140 | /// Power Limit #1 Time Window. |
| 1141 | /// |
| 1142 | UINT32 EnablePlatformPowerLimit1:1; |
| 1143 | /// |
| 1144 | /// [Bit 16] Platform Clamping Limitation #1. When set, allows the |
| 1145 | /// processor to go below the OS requested P states in order to maintain |
| 1146 | /// the power below specified Platform Power Limit #1 value. This bit is |
| 1147 | /// writeable only when CPUID (EAX=6):EAX[4] is set. |
| 1148 | /// |
| 1149 | UINT32 PlatformClampingLimitation1:1; |
| 1150 | /// |
| 1151 | /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the |
| 1152 | /// duration of the time window over which Platform Power Limit 1 value |
| 1153 | /// should be maintained for sustained long duration. This field is made |
| 1154 | /// up of two numbers from the following equation: Time Window = (float) |
| 1155 | /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. = |
| 1156 | /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is |
| 1157 | /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH, |
| 1158 | /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit]. |
| 1159 | /// |
| 1160 | UINT32 Time:7; |
| 1161 | UINT32 Reserved1:8; |
| 1162 | /// |
| 1163 | /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which |
| 1164 | /// the platform must not exceed over the Short Duration time window |
| 1165 | /// chosen by the processor. The recommended default value is 1.25 times |
| 1166 | /// the Long Duration Power Limit (i.e. Platform Power Limit # 1). |
| 1167 | /// |
| 1168 | UINT32 PlatformPowerLimit2:15; |
| 1169 | /// |
| 1170 | /// [Bit 47] Enable Platform Power Limit #2. When set, enables the |
| 1171 | /// processor to apply control policy such that the platform power does |
| 1172 | /// not exceed Platform Power limit #2 over the Short Duration time window. |
| 1173 | /// |
| 1174 | UINT32 EnablePlatformPowerLimit2:1; |
| 1175 | /// |
| 1176 | /// [Bit 48] Platform Clamping Limitation #2. When set, allows the |
| 1177 | /// processor to go below the OS requested P states in order to maintain |
| 1178 | /// the power below specified Platform Power Limit #2 value. |
| 1179 | /// |
| 1180 | UINT32 PlatformClampingLimitation2:1; |
| 1181 | UINT32 Reserved2:14; |
| 1182 | /// |
| 1183 | /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR |
| 1184 | /// until system RESET. |
| 1185 | /// |
| 1186 | UINT32 Lock:1; |
| 1187 | } Bits; |
| 1188 | /// |
| 1189 | /// All bit fields as a 64-bit value |
| 1190 | /// |
| 1191 | UINT64 Uint64; |
| 1192 | } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER; |
| 1193 | |
| 1194 | |
| 1195 | /** |
| 1196 | Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last |
| 1197 | branch record registers on the last branch record stack. This part of the |
| 1198 | stack contains pointers to the source instruction. See also: - Last Branch |
| 1199 | Record Stack TOS at 1C9H - Section 17.10. |
| 1200 | |
| 1201 | @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP |
| 1202 | @param EAX Lower 32-bits of MSR value. |
| 1203 | @param EDX Upper 32-bits of MSR value. |
| 1204 | |
| 1205 | <b>Example usage</b> |
| 1206 | @code |
| 1207 | UINT64 Msr; |
| 1208 | |
| 1209 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP); |
| 1210 | AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr); |
| 1211 | @endcode |
| 1212 | @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM. |
| 1213 | MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM. |
| 1214 | MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM. |
| 1215 | MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM. |
| 1216 | MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM. |
| 1217 | MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM. |
| 1218 | MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM. |
| 1219 | MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM. |
| 1220 | MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM. |
| 1221 | MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM. |
| 1222 | MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM. |
| 1223 | MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM. |
| 1224 | MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM. |
| 1225 | MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM. |
| 1226 | MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM. |
| 1227 | MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM. |
| 1228 | @{ |
| 1229 | **/ |
| 1230 | #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690 |
| 1231 | #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691 |
| 1232 | #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692 |
| 1233 | #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693 |
| 1234 | #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694 |
| 1235 | #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695 |
| 1236 | #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696 |
| 1237 | #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697 |
| 1238 | #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698 |
| 1239 | #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699 |
| 1240 | #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A |
| 1241 | #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B |
| 1242 | #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C |
| 1243 | #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D |
| 1244 | #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E |
| 1245 | #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F |
| 1246 | /// @} |
| 1247 | |
| 1248 | |
| 1249 | /** |
| 1250 | Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) |
| 1251 | (frequency refers to processor graphics frequency). |
| 1252 | |
| 1253 | @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0) |
| 1254 | @param EAX Lower 32-bits of MSR value. |
| 1255 | Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. |
| 1256 | @param EDX Upper 32-bits of MSR value. |
| 1257 | Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. |
| 1258 | |
| 1259 | <b>Example usage</b> |
| 1260 | @code |
| 1261 | MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr; |
| 1262 | |
| 1263 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS); |
| 1264 | AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64); |
| 1265 | @endcode |
| 1266 | @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM. |
| 1267 | **/ |
| 1268 | #define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0 |
| 1269 | |
| 1270 | /** |
| 1271 | MSR information returned for MSR index |
| 1272 | #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS |
| 1273 | **/ |
| 1274 | typedef union { |
| 1275 | /// |
| 1276 | /// Individual bit fields |
| 1277 | /// |
| 1278 | struct { |
| 1279 | /// |
| 1280 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to |
| 1281 | /// assertion of external PROCHOT. |
| 1282 | /// |
| 1283 | UINT32 PROCHOT_Status:1; |
| 1284 | /// |
| 1285 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a |
| 1286 | /// thermal event. |
| 1287 | /// |
| 1288 | UINT32 ThermalStatus:1; |
| 1289 | UINT32 Reserved1:3; |
| 1290 | /// |
| 1291 | /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency |
| 1292 | /// is reduced due to running average thermal limit. |
| 1293 | /// |
| 1294 | UINT32 RunningAverageThermalLimitStatus:1; |
| 1295 | /// |
| 1296 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due |
| 1297 | /// to a thermal alert from a processor Voltage Regulator. |
| 1298 | /// |
| 1299 | UINT32 VRThermAlertStatus:1; |
| 1300 | /// |
| 1301 | /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is |
| 1302 | /// reduced due to VR TDC limit. |
| 1303 | /// |
| 1304 | UINT32 VRThermalDesignCurrentStatus:1; |
| 1305 | /// |
| 1306 | /// [Bit 8] Other Status (R0) When set, frequency is reduced due to |
| 1307 | /// electrical or other constraints. |
| 1308 | /// |
| 1309 | UINT32 OtherStatus:1; |
| 1310 | UINT32 Reserved2:1; |
| 1311 | /// |
| 1312 | /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When |
| 1313 | /// set, frequency is reduced due to package/platform-level power limiting |
| 1314 | /// PL1. |
| 1315 | /// |
| 1316 | UINT32 PL1Status:1; |
| 1317 | /// |
| 1318 | /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When |
| 1319 | /// set, frequency is reduced due to package/platform-level power limiting |
| 1320 | /// PL2/PL3. |
| 1321 | /// |
| 1322 | UINT32 PL2Status:1; |
| 1323 | /// |
| 1324 | /// [Bit 12] Inefficient Operation Status (R0) When set, processor |
| 1325 | /// graphics frequency is operating below target frequency. |
| 1326 | /// |
| 1327 | UINT32 InefficientOperationStatus:1; |
| 1328 | UINT32 Reserved3:3; |
| 1329 | /// |
| 1330 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit |
| 1331 | /// has asserted since the log bit was last cleared. This log bit will |
| 1332 | /// remain set until cleared by software writing 0. |
| 1333 | /// |
| 1334 | UINT32 PROCHOT_Log:1; |
| 1335 | /// |
| 1336 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit |
| 1337 | /// has asserted since the log bit was last cleared. This log bit will |
| 1338 | /// remain set until cleared by software writing 0. |
| 1339 | /// |
| 1340 | UINT32 ThermalLog:1; |
| 1341 | UINT32 Reserved4:3; |
| 1342 | /// |
| 1343 | /// [Bit 21] Running Average Thermal Limit Log When set, indicates that |
| 1344 | /// the RATL Status bit has asserted since the log bit was last cleared. |
| 1345 | /// This log bit will remain set until cleared by software writing 0. |
| 1346 | /// |
| 1347 | UINT32 RunningAverageThermalLimitLog:1; |
| 1348 | /// |
| 1349 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm |
| 1350 | /// Alert Status bit has asserted since the log bit was last cleared. This |
| 1351 | /// log bit will remain set until cleared by software writing 0. |
| 1352 | /// |
| 1353 | UINT32 VRThermAlertLog:1; |
| 1354 | /// |
| 1355 | /// [Bit 23] VR Thermal Design Current Log When set, indicates that the |
| 1356 | /// VR Therm Alert Status bit has asserted since the log bit was last |
| 1357 | /// cleared. This log bit will remain set until cleared by software |
| 1358 | /// writing 0. |
| 1359 | /// |
| 1360 | UINT32 VRThermalDesignCurrentLog:1; |
| 1361 | /// |
| 1362 | /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has |
| 1363 | /// asserted since the log bit was last cleared. This log bit will remain |
| 1364 | /// set until cleared by software writing 0. |
| 1365 | /// |
| 1366 | UINT32 OtherLog:1; |
| 1367 | UINT32 Reserved5:1; |
| 1368 | /// |
| 1369 | /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, |
| 1370 | /// indicates that the Package/Platform Level PL1 Power Limiting Status |
| 1371 | /// bit has asserted since the log bit was last cleared. This log bit will |
| 1372 | /// remain set until cleared by software writing 0. |
| 1373 | /// |
| 1374 | UINT32 PL1Log:1; |
| 1375 | /// |
| 1376 | /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, |
| 1377 | /// indicates that the Package/Platform Level PL2 Power Limiting Status |
| 1378 | /// bit has asserted since the log bit was last cleared. This log bit will |
| 1379 | /// remain set until cleared by software writing 0. |
| 1380 | /// |
| 1381 | UINT32 PL2Log:1; |
| 1382 | /// |
| 1383 | /// [Bit 28] Inefficient Operation Log When set, indicates that the |
| 1384 | /// Inefficient Operation Status bit has asserted since the log bit was |
| 1385 | /// last cleared. This log bit will remain set until cleared by software |
| 1386 | /// writing 0. |
| 1387 | /// |
| 1388 | UINT32 InefficientOperationLog:1; |
| 1389 | UINT32 Reserved6:3; |
| 1390 | UINT32 Reserved7:32; |
| 1391 | } Bits; |
| 1392 | /// |
| 1393 | /// All bit fields as a 32-bit value |
| 1394 | /// |
| 1395 | UINT32 Uint32; |
| 1396 | /// |
| 1397 | /// All bit fields as a 64-bit value |
| 1398 | /// |
| 1399 | UINT64 Uint64; |
| 1400 | } MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER; |
| 1401 | |
| 1402 | |
| 1403 | /** |
| 1404 | Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) |
| 1405 | (frequency refers to ring interconnect in the uncore). |
| 1406 | |
| 1407 | @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1) |
| 1408 | @param EAX Lower 32-bits of MSR value. |
| 1409 | Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. |
| 1410 | @param EDX Upper 32-bits of MSR value. |
| 1411 | Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. |
| 1412 | |
| 1413 | <b>Example usage</b> |
| 1414 | @code |
| 1415 | MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr; |
| 1416 | |
| 1417 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS); |
| 1418 | AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64); |
| 1419 | @endcode |
| 1420 | @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM. |
| 1421 | **/ |
| 1422 | #define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1 |
| 1423 | |
| 1424 | /** |
| 1425 | MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS |
| 1426 | **/ |
| 1427 | typedef union { |
| 1428 | /// |
| 1429 | /// Individual bit fields |
| 1430 | /// |
| 1431 | struct { |
| 1432 | /// |
| 1433 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to |
| 1434 | /// assertion of external PROCHOT. |
| 1435 | /// |
| 1436 | UINT32 PROCHOT_Status:1; |
| 1437 | /// |
| 1438 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a |
| 1439 | /// thermal event. |
| 1440 | /// |
| 1441 | UINT32 ThermalStatus:1; |
| 1442 | UINT32 Reserved1:3; |
| 1443 | /// |
| 1444 | /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency |
| 1445 | /// is reduced due to running average thermal limit. |
| 1446 | /// |
| 1447 | UINT32 RunningAverageThermalLimitStatus:1; |
| 1448 | /// |
| 1449 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due |
| 1450 | /// to a thermal alert from a processor Voltage Regulator. |
| 1451 | /// |
| 1452 | UINT32 VRThermAlertStatus:1; |
| 1453 | /// |
| 1454 | /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is |
| 1455 | /// reduced due to VR TDC limit. |
| 1456 | /// |
| 1457 | UINT32 VRThermalDesignCurrentStatus:1; |
| 1458 | /// |
| 1459 | /// [Bit 8] Other Status (R0) When set, frequency is reduced due to |
| 1460 | /// electrical or other constraints. |
| 1461 | /// |
| 1462 | UINT32 OtherStatus:1; |
| 1463 | UINT32 Reserved2:1; |
| 1464 | /// |
| 1465 | /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When |
| 1466 | /// set, frequency is reduced due to package/Platform-level power limiting |
| 1467 | /// PL1. |
| 1468 | /// |
| 1469 | UINT32 PL1Status:1; |
| 1470 | /// |
| 1471 | /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When |
| 1472 | /// set, frequency is reduced due to package/Platform-level power limiting |
| 1473 | /// PL2/PL3. |
| 1474 | /// |
| 1475 | UINT32 PL2Status:1; |
| 1476 | UINT32 Reserved3:4; |
| 1477 | /// |
| 1478 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit |
| 1479 | /// has asserted since the log bit was last cleared. This log bit will |
| 1480 | /// remain set until cleared by software writing 0. |
| 1481 | /// |
| 1482 | UINT32 PROCHOT_Log:1; |
| 1483 | /// |
| 1484 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit |
| 1485 | /// has asserted since the log bit was last cleared. This log bit will |
| 1486 | /// remain set until cleared by software writing 0. |
| 1487 | /// |
| 1488 | UINT32 ThermalLog:1; |
| 1489 | UINT32 Reserved4:3; |
| 1490 | /// |
| 1491 | /// [Bit 21] Running Average Thermal Limit Log When set, indicates that |
| 1492 | /// the RATL Status bit has asserted since the log bit was last cleared. |
| 1493 | /// This log bit will remain set until cleared by software writing 0. |
| 1494 | /// |
| 1495 | UINT32 RunningAverageThermalLimitLog:1; |
| 1496 | /// |
| 1497 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm |
| 1498 | /// Alert Status bit has asserted since the log bit was last cleared. This |
| 1499 | /// log bit will remain set until cleared by software writing 0. |
| 1500 | /// |
| 1501 | UINT32 VRThermAlertLog:1; |
| 1502 | /// |
| 1503 | /// [Bit 23] VR Thermal Design Current Log When set, indicates that the |
| 1504 | /// VR Therm Alert Status bit has asserted since the log bit was last |
| 1505 | /// cleared. This log bit will remain set until cleared by software |
| 1506 | /// writing 0. |
| 1507 | /// |
| 1508 | UINT32 VRThermalDesignCurrentLog:1; |
| 1509 | /// |
| 1510 | /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has |
| 1511 | /// asserted since the log bit was last cleared. This log bit will remain |
| 1512 | /// set until cleared by software writing 0. |
| 1513 | /// |
| 1514 | UINT32 OtherLog:1; |
| 1515 | UINT32 Reserved5:1; |
| 1516 | /// |
| 1517 | /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, |
| 1518 | /// indicates that the Package/Platform Level PL1 Power Limiting Status |
| 1519 | /// bit has asserted since the log bit was last cleared. This log bit will |
| 1520 | /// remain set until cleared by software writing 0. |
| 1521 | /// |
| 1522 | UINT32 PL1Log:1; |
| 1523 | /// |
| 1524 | /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, |
| 1525 | /// indicates that the Package/Platform Level PL2 Power Limiting Status |
| 1526 | /// bit has asserted since the log bit was last cleared. This log bit will |
| 1527 | /// remain set until cleared by software writing 0. |
| 1528 | /// |
| 1529 | UINT32 PL2Log:1; |
| 1530 | UINT32 Reserved6:4; |
| 1531 | UINT32 Reserved7:32; |
| 1532 | } Bits; |
| 1533 | /// |
| 1534 | /// All bit fields as a 32-bit value |
| 1535 | /// |
| 1536 | UINT32 Uint32; |
| 1537 | /// |
| 1538 | /// All bit fields as a 64-bit value |
| 1539 | /// |
| 1540 | UINT64 Uint64; |
| 1541 | } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER; |
| 1542 | |
| 1543 | |
| 1544 | /** |
| 1545 | Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch |
| 1546 | record registers on the last branch record stack. This part of the stack |
| 1547 | contains pointers to the destination instruction. See also: - Last Branch |
| 1548 | Record Stack TOS at 1C9H - Section 17.10. |
| 1549 | |
| 1550 | @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP |
| 1551 | @param EAX Lower 32-bits of MSR value. |
| 1552 | @param EDX Upper 32-bits of MSR value. |
| 1553 | |
| 1554 | <b>Example usage</b> |
| 1555 | @code |
| 1556 | UINT64 Msr; |
| 1557 | |
| 1558 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP); |
| 1559 | AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr); |
| 1560 | @endcode |
| 1561 | @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM. |
| 1562 | MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM. |
| 1563 | MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM. |
| 1564 | MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM. |
| 1565 | MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM. |
| 1566 | MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM. |
| 1567 | MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM. |
| 1568 | MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM. |
| 1569 | MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM. |
| 1570 | MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM. |
| 1571 | MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM. |
| 1572 | MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM. |
| 1573 | MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM. |
| 1574 | MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM. |
| 1575 | MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM. |
| 1576 | MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM. |
| 1577 | @{ |
| 1578 | **/ |
| 1579 | #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0 |
| 1580 | #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1 |
| 1581 | #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2 |
| 1582 | #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3 |
| 1583 | #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4 |
| 1584 | #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5 |
| 1585 | #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6 |
| 1586 | #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7 |
| 1587 | #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8 |
| 1588 | #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9 |
| 1589 | #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA |
| 1590 | #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB |
| 1591 | #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC |
| 1592 | #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD |
| 1593 | #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE |
| 1594 | #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF |
| 1595 | /// @} |
| 1596 | |
| 1597 | |
| 1598 | /** |
| 1599 | Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet |
| 1600 | of last branch record registers on the last branch record stack. This part |
| 1601 | of the stack contains flag, TSX-related and elapsed cycle information. See |
| 1602 | also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR |
| 1603 | Stack.". |
| 1604 | |
| 1605 | @param ECX MSR_SKYLAKE_LBR_INFO_n |
| 1606 | @param EAX Lower 32-bits of MSR value. |
| 1607 | @param EDX Upper 32-bits of MSR value. |
| 1608 | |
| 1609 | <b>Example usage</b> |
| 1610 | @code |
| 1611 | UINT64 Msr; |
| 1612 | |
| 1613 | Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0); |
| 1614 | AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr); |
| 1615 | @endcode |
| 1616 | @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM. |
| 1617 | MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM. |
| 1618 | MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM. |
| 1619 | MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM. |
| 1620 | MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM. |
| 1621 | MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM. |
| 1622 | MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM. |
| 1623 | MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM. |
| 1624 | MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM. |
| 1625 | MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM. |
| 1626 | MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM. |
| 1627 | MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM. |
| 1628 | MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM. |
| 1629 | MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM. |
| 1630 | MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM. |
| 1631 | MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM. |
| 1632 | MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM. |
| 1633 | MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM. |
| 1634 | MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM. |
| 1635 | MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM. |
| 1636 | MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM. |
| 1637 | MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM. |
| 1638 | MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM. |
| 1639 | MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM. |
| 1640 | MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM. |
| 1641 | MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM. |
| 1642 | MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM. |
| 1643 | MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM. |
| 1644 | MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM. |
| 1645 | MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM. |
| 1646 | MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM. |
| 1647 | MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM. |
| 1648 | @{ |
| 1649 | **/ |
| 1650 | #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0 |
| 1651 | #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1 |
| 1652 | #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2 |
| 1653 | #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3 |
| 1654 | #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4 |
| 1655 | #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5 |
| 1656 | #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6 |
| 1657 | #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7 |
| 1658 | #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8 |
| 1659 | #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9 |
| 1660 | #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA |
| 1661 | #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB |
| 1662 | #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC |
| 1663 | #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD |
| 1664 | #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE |
| 1665 | #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF |
| 1666 | #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0 |
| 1667 | #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1 |
| 1668 | #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2 |
| 1669 | #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3 |
| 1670 | #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4 |
| 1671 | #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5 |
| 1672 | #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6 |
| 1673 | #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7 |
| 1674 | #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8 |
| 1675 | #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9 |
| 1676 | #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA |
| 1677 | #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB |
| 1678 | #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC |
| 1679 | #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD |
| 1680 | #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE |
| 1681 | #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF |
| 1682 | /// @} |
| 1683 | |
| 1684 | |
| 1685 | /** |
| 1686 | Package. Uncore fixed counter control (R/W). |
| 1687 | |
| 1688 | @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394) |
| 1689 | @param EAX Lower 32-bits of MSR value. |
| 1690 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. |
| 1691 | @param EDX Upper 32-bits of MSR value. |
| 1692 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. |
| 1693 | |
| 1694 | <b>Example usage</b> |
| 1695 | @code |
| 1696 | MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr; |
| 1697 | |
| 1698 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL); |
| 1699 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64); |
| 1700 | @endcode |
| 1701 | @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. |
| 1702 | **/ |
| 1703 | #define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394 |
| 1704 | |
| 1705 | /** |
| 1706 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL |
| 1707 | **/ |
| 1708 | typedef union { |
| 1709 | /// |
| 1710 | /// Individual bit fields |
| 1711 | /// |
| 1712 | struct { |
| 1713 | UINT32 Reserved1:20; |
| 1714 | /// |
| 1715 | /// [Bit 20] Enable overflow propagation. |
| 1716 | /// |
| 1717 | UINT32 EnableOverflow:1; |
| 1718 | UINT32 Reserved2:1; |
| 1719 | /// |
| 1720 | /// [Bit 22] Enable counting. |
| 1721 | /// |
| 1722 | UINT32 EnableCounting:1; |
| 1723 | UINT32 Reserved3:9; |
| 1724 | UINT32 Reserved4:32; |
| 1725 | } Bits; |
| 1726 | /// |
| 1727 | /// All bit fields as a 32-bit value |
| 1728 | /// |
| 1729 | UINT32 Uint32; |
| 1730 | /// |
| 1731 | /// All bit fields as a 64-bit value |
| 1732 | /// |
| 1733 | UINT64 Uint64; |
| 1734 | } MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER; |
| 1735 | |
| 1736 | |
| 1737 | /** |
| 1738 | Package. Uncore fixed counter. |
| 1739 | |
| 1740 | @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395) |
| 1741 | @param EAX Lower 32-bits of MSR value. |
| 1742 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. |
| 1743 | @param EDX Upper 32-bits of MSR value. |
| 1744 | Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. |
| 1745 | |
| 1746 | <b>Example usage</b> |
| 1747 | @code |
| 1748 | MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr; |
| 1749 | |
| 1750 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR); |
| 1751 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64); |
| 1752 | @endcode |
| 1753 | @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. |
| 1754 | **/ |
| 1755 | #define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395 |
| 1756 | |
| 1757 | /** |
| 1758 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR |
| 1759 | **/ |
| 1760 | typedef union { |
| 1761 | /// |
| 1762 | /// Individual bit fields |
| 1763 | /// |
| 1764 | struct { |
| 1765 | /// |
| 1766 | /// [Bits 31:0] Current count. |
| 1767 | /// |
| 1768 | UINT32 CurrentCount:32; |
| 1769 | /// |
| 1770 | /// [Bits 43:32] Current count. |
| 1771 | /// |
| 1772 | UINT32 CurrentCountHi:12; |
| 1773 | UINT32 Reserved:20; |
| 1774 | } Bits; |
| 1775 | /// |
| 1776 | /// All bit fields as a 64-bit value |
| 1777 | /// |
| 1778 | UINT64 Uint64; |
| 1779 | } MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER; |
| 1780 | |
| 1781 | |
| 1782 | /** |
| 1783 | Package. Uncore C-Box configuration information (R/O). |
| 1784 | |
| 1785 | @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396) |
| 1786 | @param EAX Lower 32-bits of MSR value. |
| 1787 | Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. |
| 1788 | @param EDX Upper 32-bits of MSR value. |
| 1789 | Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. |
| 1790 | |
| 1791 | <b>Example usage</b> |
| 1792 | @code |
| 1793 | MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr; |
| 1794 | |
| 1795 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG); |
| 1796 | @endcode |
| 1797 | @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. |
| 1798 | **/ |
| 1799 | #define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396 |
| 1800 | |
| 1801 | /** |
| 1802 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG |
| 1803 | **/ |
| 1804 | typedef union { |
| 1805 | /// |
| 1806 | /// Individual bit fields |
| 1807 | /// |
| 1808 | struct { |
| 1809 | /// |
| 1810 | /// [Bits 3:0] Specifies the number of C-Box units with programmable |
| 1811 | /// counters (including processor cores and processor graphics),. |
| 1812 | /// |
| 1813 | UINT32 CBox:4; |
| 1814 | UINT32 Reserved1:28; |
| 1815 | UINT32 Reserved2:32; |
| 1816 | } Bits; |
| 1817 | /// |
| 1818 | /// All bit fields as a 32-bit value |
| 1819 | /// |
| 1820 | UINT32 Uint32; |
| 1821 | /// |
| 1822 | /// All bit fields as a 64-bit value |
| 1823 | /// |
| 1824 | UINT64 Uint64; |
| 1825 | } MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER; |
| 1826 | |
| 1827 | |
| 1828 | /** |
| 1829 | Package. Uncore Arb unit, performance counter 0. |
| 1830 | |
| 1831 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0) |
| 1832 | @param EAX Lower 32-bits of MSR value. |
| 1833 | @param EDX Upper 32-bits of MSR value. |
| 1834 | |
| 1835 | <b>Example usage</b> |
| 1836 | @code |
| 1837 | UINT64 Msr; |
| 1838 | |
| 1839 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0); |
| 1840 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr); |
| 1841 | @endcode |
| 1842 | @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. |
| 1843 | **/ |
| 1844 | #define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0 |
| 1845 | |
| 1846 | |
| 1847 | /** |
| 1848 | Package. Uncore Arb unit, performance counter 1. |
| 1849 | |
| 1850 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1) |
| 1851 | @param EAX Lower 32-bits of MSR value. |
| 1852 | @param EDX Upper 32-bits of MSR value. |
| 1853 | |
| 1854 | <b>Example usage</b> |
| 1855 | @code |
| 1856 | UINT64 Msr; |
| 1857 | |
| 1858 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1); |
| 1859 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr); |
| 1860 | @endcode |
| 1861 | @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. |
| 1862 | **/ |
| 1863 | #define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1 |
| 1864 | |
| 1865 | |
| 1866 | /** |
| 1867 | Package. Uncore Arb unit, counter 0 event select MSR. |
| 1868 | |
| 1869 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2) |
| 1870 | @param EAX Lower 32-bits of MSR value. |
| 1871 | @param EDX Upper 32-bits of MSR value. |
| 1872 | |
| 1873 | <b>Example usage</b> |
| 1874 | @code |
| 1875 | UINT64 Msr; |
| 1876 | |
| 1877 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0); |
| 1878 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr); |
| 1879 | @endcode |
| 1880 | @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. |
| 1881 | **/ |
| 1882 | #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2 |
| 1883 | |
| 1884 | |
| 1885 | /** |
| 1886 | Package. Uncore Arb unit, counter 1 event select MSR. |
| 1887 | |
| 1888 | @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3) |
| 1889 | @param EAX Lower 32-bits of MSR value. |
| 1890 | @param EDX Upper 32-bits of MSR value. |
| 1891 | |
| 1892 | <b>Example usage</b> |
| 1893 | @code |
| 1894 | UINT64 Msr; |
| 1895 | |
| 1896 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1); |
| 1897 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr); |
| 1898 | @endcode |
| 1899 | @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM. |
| 1900 | **/ |
| 1901 | #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3 |
| 1902 | |
| 1903 | |
| 1904 | /** |
| 1905 | Package. Uncore C-Box 0, counter 0 event select MSR. |
| 1906 | |
| 1907 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700) |
| 1908 | @param EAX Lower 32-bits of MSR value. |
| 1909 | @param EDX Upper 32-bits of MSR value. |
| 1910 | |
| 1911 | <b>Example usage</b> |
| 1912 | @code |
| 1913 | UINT64 Msr; |
| 1914 | |
| 1915 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0); |
| 1916 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr); |
| 1917 | @endcode |
| 1918 | @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. |
| 1919 | **/ |
| 1920 | #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700 |
| 1921 | |
| 1922 | |
| 1923 | /** |
| 1924 | Package. Uncore C-Box 0, counter 1 event select MSR. |
| 1925 | |
| 1926 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701) |
| 1927 | @param EAX Lower 32-bits of MSR value. |
| 1928 | @param EDX Upper 32-bits of MSR value. |
| 1929 | |
| 1930 | <b>Example usage</b> |
| 1931 | @code |
| 1932 | UINT64 Msr; |
| 1933 | |
| 1934 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1); |
| 1935 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr); |
| 1936 | @endcode |
| 1937 | @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. |
| 1938 | **/ |
| 1939 | #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701 |
| 1940 | |
| 1941 | |
| 1942 | /** |
| 1943 | Package. Uncore C-Box 0, performance counter 0. |
| 1944 | |
| 1945 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706) |
| 1946 | @param EAX Lower 32-bits of MSR value. |
| 1947 | @param EDX Upper 32-bits of MSR value. |
| 1948 | |
| 1949 | <b>Example usage</b> |
| 1950 | @code |
| 1951 | UINT64 Msr; |
| 1952 | |
| 1953 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0); |
| 1954 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr); |
| 1955 | @endcode |
| 1956 | @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. |
| 1957 | **/ |
| 1958 | #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706 |
| 1959 | |
| 1960 | |
| 1961 | /** |
| 1962 | Package. Uncore C-Box 0, performance counter 1. |
| 1963 | |
| 1964 | @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707) |
| 1965 | @param EAX Lower 32-bits of MSR value. |
| 1966 | @param EDX Upper 32-bits of MSR value. |
| 1967 | |
| 1968 | <b>Example usage</b> |
| 1969 | @code |
| 1970 | UINT64 Msr; |
| 1971 | |
| 1972 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1); |
| 1973 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr); |
| 1974 | @endcode |
| 1975 | @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. |
| 1976 | **/ |
| 1977 | #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707 |
| 1978 | |
| 1979 | |
| 1980 | /** |
| 1981 | Package. Uncore C-Box 1, counter 0 event select MSR. |
| 1982 | |
| 1983 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710) |
| 1984 | @param EAX Lower 32-bits of MSR value. |
| 1985 | @param EDX Upper 32-bits of MSR value. |
| 1986 | |
| 1987 | <b>Example usage</b> |
| 1988 | @code |
| 1989 | UINT64 Msr; |
| 1990 | |
| 1991 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0); |
| 1992 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr); |
| 1993 | @endcode |
| 1994 | @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. |
| 1995 | **/ |
| 1996 | #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710 |
| 1997 | |
| 1998 | |
| 1999 | /** |
| 2000 | Package. Uncore C-Box 1, counter 1 event select MSR. |
| 2001 | |
| 2002 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711) |
| 2003 | @param EAX Lower 32-bits of MSR value. |
| 2004 | @param EDX Upper 32-bits of MSR value. |
| 2005 | |
| 2006 | <b>Example usage</b> |
| 2007 | @code |
| 2008 | UINT64 Msr; |
| 2009 | |
| 2010 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1); |
| 2011 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr); |
| 2012 | @endcode |
| 2013 | @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. |
| 2014 | **/ |
| 2015 | #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711 |
| 2016 | |
| 2017 | |
| 2018 | /** |
| 2019 | Package. Uncore C-Box 1, performance counter 0. |
| 2020 | |
| 2021 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716) |
| 2022 | @param EAX Lower 32-bits of MSR value. |
| 2023 | @param EDX Upper 32-bits of MSR value. |
| 2024 | |
| 2025 | <b>Example usage</b> |
| 2026 | @code |
| 2027 | UINT64 Msr; |
| 2028 | |
| 2029 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0); |
| 2030 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr); |
| 2031 | @endcode |
| 2032 | @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. |
| 2033 | **/ |
| 2034 | #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716 |
| 2035 | |
| 2036 | |
| 2037 | /** |
| 2038 | Package. Uncore C-Box 1, performance counter 1. |
| 2039 | |
| 2040 | @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717) |
| 2041 | @param EAX Lower 32-bits of MSR value. |
| 2042 | @param EDX Upper 32-bits of MSR value. |
| 2043 | |
| 2044 | <b>Example usage</b> |
| 2045 | @code |
| 2046 | UINT64 Msr; |
| 2047 | |
| 2048 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1); |
| 2049 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr); |
| 2050 | @endcode |
| 2051 | @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. |
| 2052 | **/ |
| 2053 | #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717 |
| 2054 | |
| 2055 | |
| 2056 | /** |
| 2057 | Package. Uncore C-Box 2, counter 0 event select MSR. |
| 2058 | |
| 2059 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720) |
| 2060 | @param EAX Lower 32-bits of MSR value. |
| 2061 | @param EDX Upper 32-bits of MSR value. |
| 2062 | |
| 2063 | <b>Example usage</b> |
| 2064 | @code |
| 2065 | UINT64 Msr; |
| 2066 | |
| 2067 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0); |
| 2068 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr); |
| 2069 | @endcode |
| 2070 | @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. |
| 2071 | **/ |
| 2072 | #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720 |
| 2073 | |
| 2074 | |
| 2075 | /** |
| 2076 | Package. Uncore C-Box 2, counter 1 event select MSR. |
| 2077 | |
| 2078 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721) |
| 2079 | @param EAX Lower 32-bits of MSR value. |
| 2080 | @param EDX Upper 32-bits of MSR value. |
| 2081 | |
| 2082 | <b>Example usage</b> |
| 2083 | @code |
| 2084 | UINT64 Msr; |
| 2085 | |
| 2086 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1); |
| 2087 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr); |
| 2088 | @endcode |
| 2089 | @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. |
| 2090 | **/ |
| 2091 | #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721 |
| 2092 | |
| 2093 | |
| 2094 | /** |
| 2095 | Package. Uncore C-Box 2, performance counter 0. |
| 2096 | |
| 2097 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726) |
| 2098 | @param EAX Lower 32-bits of MSR value. |
| 2099 | @param EDX Upper 32-bits of MSR value. |
| 2100 | |
| 2101 | <b>Example usage</b> |
| 2102 | @code |
| 2103 | UINT64 Msr; |
| 2104 | |
| 2105 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0); |
| 2106 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr); |
| 2107 | @endcode |
| 2108 | @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. |
| 2109 | **/ |
| 2110 | #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726 |
| 2111 | |
| 2112 | |
| 2113 | /** |
| 2114 | Package. Uncore C-Box 2, performance counter 1. |
| 2115 | |
| 2116 | @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727) |
| 2117 | @param EAX Lower 32-bits of MSR value. |
| 2118 | @param EDX Upper 32-bits of MSR value. |
| 2119 | |
| 2120 | <b>Example usage</b> |
| 2121 | @code |
| 2122 | UINT64 Msr; |
| 2123 | |
| 2124 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1); |
| 2125 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr); |
| 2126 | @endcode |
| 2127 | @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. |
| 2128 | **/ |
| 2129 | #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727 |
| 2130 | |
| 2131 | |
| 2132 | /** |
| 2133 | Package. Uncore C-Box 3, counter 0 event select MSR. |
| 2134 | |
| 2135 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730) |
| 2136 | @param EAX Lower 32-bits of MSR value. |
| 2137 | @param EDX Upper 32-bits of MSR value. |
| 2138 | |
| 2139 | <b>Example usage</b> |
| 2140 | @code |
| 2141 | UINT64 Msr; |
| 2142 | |
| 2143 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0); |
| 2144 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr); |
| 2145 | @endcode |
| 2146 | @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. |
| 2147 | **/ |
| 2148 | #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730 |
| 2149 | |
| 2150 | |
| 2151 | /** |
| 2152 | Package. Uncore C-Box 3, counter 1 event select MSR. |
| 2153 | |
| 2154 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731) |
| 2155 | @param EAX Lower 32-bits of MSR value. |
| 2156 | @param EDX Upper 32-bits of MSR value. |
| 2157 | |
| 2158 | <b>Example usage</b> |
| 2159 | @code |
| 2160 | UINT64 Msr; |
| 2161 | |
| 2162 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1); |
| 2163 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr); |
| 2164 | @endcode |
| 2165 | @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. |
| 2166 | **/ |
| 2167 | #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731 |
| 2168 | |
| 2169 | |
| 2170 | /** |
| 2171 | Package. Uncore C-Box 3, performance counter 0. |
| 2172 | |
| 2173 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736) |
| 2174 | @param EAX Lower 32-bits of MSR value. |
| 2175 | @param EDX Upper 32-bits of MSR value. |
| 2176 | |
| 2177 | <b>Example usage</b> |
| 2178 | @code |
| 2179 | UINT64 Msr; |
| 2180 | |
| 2181 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0); |
| 2182 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr); |
| 2183 | @endcode |
| 2184 | @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. |
| 2185 | **/ |
| 2186 | #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736 |
| 2187 | |
| 2188 | |
| 2189 | /** |
| 2190 | Package. Uncore C-Box 3, performance counter 1. |
| 2191 | |
| 2192 | @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737) |
| 2193 | @param EAX Lower 32-bits of MSR value. |
| 2194 | @param EDX Upper 32-bits of MSR value. |
| 2195 | |
| 2196 | <b>Example usage</b> |
| 2197 | @code |
| 2198 | UINT64 Msr; |
| 2199 | |
| 2200 | Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1); |
| 2201 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr); |
| 2202 | @endcode |
| 2203 | @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. |
| 2204 | **/ |
| 2205 | #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737 |
| 2206 | |
| 2207 | |
| 2208 | /** |
| 2209 | Package. Uncore PMU global control. |
| 2210 | |
| 2211 | @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01) |
| 2212 | @param EAX Lower 32-bits of MSR value. |
| 2213 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. |
| 2214 | @param EDX Upper 32-bits of MSR value. |
| 2215 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. |
| 2216 | |
| 2217 | <b>Example usage</b> |
| 2218 | @code |
| 2219 | MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; |
| 2220 | |
| 2221 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL); |
| 2222 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); |
| 2223 | @endcode |
| 2224 | @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. |
| 2225 | **/ |
| 2226 | #define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01 |
| 2227 | |
| 2228 | /** |
| 2229 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL |
| 2230 | **/ |
| 2231 | typedef union { |
| 2232 | /// |
| 2233 | /// Individual bit fields |
| 2234 | /// |
| 2235 | struct { |
| 2236 | /// |
| 2237 | /// [Bit 0] Slice 0 select. |
| 2238 | /// |
| 2239 | UINT32 PMI_Sel_Slice0:1; |
| 2240 | /// |
| 2241 | /// [Bit 1] Slice 1 select. |
| 2242 | /// |
| 2243 | UINT32 PMI_Sel_Slice1:1; |
| 2244 | /// |
| 2245 | /// [Bit 2] Slice 2 select. |
| 2246 | /// |
| 2247 | UINT32 PMI_Sel_Slice2:1; |
| 2248 | /// |
| 2249 | /// [Bit 3] Slice 3 select. |
| 2250 | /// |
| 2251 | UINT32 PMI_Sel_Slice3:1; |
| 2252 | /// |
| 2253 | /// [Bit 4] Slice 4select. |
| 2254 | /// |
| 2255 | UINT32 PMI_Sel_Slice4:1; |
| 2256 | UINT32 Reserved1:14; |
| 2257 | UINT32 Reserved2:10; |
| 2258 | /// |
| 2259 | /// [Bit 29] Enable all uncore counters. |
| 2260 | /// |
| 2261 | UINT32 EN:1; |
| 2262 | /// |
| 2263 | /// [Bit 30] Enable wake on PMI. |
| 2264 | /// |
| 2265 | UINT32 WakePMI:1; |
| 2266 | /// |
| 2267 | /// [Bit 31] Enable Freezing counter when overflow. |
| 2268 | /// |
| 2269 | UINT32 FREEZE:1; |
| 2270 | UINT32 Reserved3:32; |
| 2271 | } Bits; |
| 2272 | /// |
| 2273 | /// All bit fields as a 32-bit value |
| 2274 | /// |
| 2275 | UINT32 Uint32; |
| 2276 | /// |
| 2277 | /// All bit fields as a 64-bit value |
| 2278 | /// |
| 2279 | UINT64 Uint64; |
| 2280 | } MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER; |
| 2281 | |
| 2282 | |
| 2283 | /** |
| 2284 | Package. Uncore PMU main status. |
| 2285 | |
| 2286 | @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02) |
| 2287 | @param EAX Lower 32-bits of MSR value. |
| 2288 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. |
| 2289 | @param EDX Upper 32-bits of MSR value. |
| 2290 | Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. |
| 2291 | |
| 2292 | <b>Example usage</b> |
| 2293 | @code |
| 2294 | MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; |
| 2295 | |
| 2296 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS); |
| 2297 | AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); |
| 2298 | @endcode |
| 2299 | @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. |
| 2300 | **/ |
| 2301 | #define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02 |
| 2302 | |
| 2303 | /** |
| 2304 | MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS |
| 2305 | **/ |
| 2306 | typedef union { |
| 2307 | /// |
| 2308 | /// Individual bit fields |
| 2309 | /// |
| 2310 | struct { |
| 2311 | /// |
| 2312 | /// [Bit 0] Fixed counter overflowed. |
| 2313 | /// |
| 2314 | UINT32 Fixed:1; |
| 2315 | /// |
| 2316 | /// [Bit 1] An ARB counter overflowed. |
| 2317 | /// |
| 2318 | UINT32 ARB:1; |
| 2319 | UINT32 Reserved1:1; |
| 2320 | /// |
| 2321 | /// [Bit 3] A CBox counter overflowed (on any slice). |
| 2322 | /// |
| 2323 | UINT32 CBox:1; |
| 2324 | UINT32 Reserved2:28; |
| 2325 | UINT32 Reserved3:32; |
| 2326 | } Bits; |
| 2327 | /// |
| 2328 | /// All bit fields as a 32-bit value |
| 2329 | /// |
| 2330 | UINT32 Uint32; |
| 2331 | /// |
| 2332 | /// All bit fields as a 64-bit value |
| 2333 | /// |
| 2334 | UINT64 Uint64; |
| 2335 | } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER; |
| 2336 | |
| 2337 | |
| 2338 | /** |
| 2339 | Package. NPK Address Used by AET Messages (R/W). |
| 2340 | |
| 2341 | @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080) |
| 2342 | @param EAX Lower 32-bits of MSR value. |
| 2343 | Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER. |
| 2344 | @param EDX Upper 32-bits of MSR value. |
| 2345 | Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER. |
| 2346 | |
| 2347 | <b>Example usage</b> |
| 2348 | @code |
| 2349 | MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr; |
| 2350 | |
| 2351 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE); |
| 2352 | AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64); |
| 2353 | @endcode |
| 2354 | **/ |
| 2355 | #define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080 |
| 2356 | |
| 2357 | /** |
| 2358 | MSR information returned for MSR index |
| 2359 | #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE |
| 2360 | **/ |
| 2361 | typedef union { |
| 2362 | /// |
| 2363 | /// Individual bit fields |
| 2364 | /// |
| 2365 | struct { |
| 2366 | /// |
| 2367 | /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock |
| 2368 | /// bit has to be set in order for the AET packets to be directed to NPK |
| 2369 | /// MMIO. |
| 2370 | /// |
| 2371 | UINT32 Fix_Me_1:1; |
| 2372 | UINT32 Reserved:17; |
| 2373 | /// |
| 2374 | /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space. |
| 2375 | /// |
| 2376 | UINT32 ACPIBAR_BASE_ADDRESS:14; |
| 2377 | /// |
| 2378 | /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space. |
| 2379 | /// |
| 2380 | UINT32 Fix_Me_2:32; |
| 2381 | } Bits; |
| 2382 | /// |
| 2383 | /// All bit fields as a 64-bit value |
| 2384 | /// |
| 2385 | UINT64 Uint64; |
| 2386 | } MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER; |
| 2387 | |
| 2388 | |
| 2389 | /** |
| 2390 | Core. Processor Reserved Memory Range Register - Physical Base Control |
| 2391 | Register (R/W). |
| 2392 | |
| 2393 | @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4) |
| 2394 | @param EAX Lower 32-bits of MSR value. |
| 2395 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER. |
| 2396 | @param EDX Upper 32-bits of MSR value. |
| 2397 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER. |
| 2398 | |
| 2399 | <b>Example usage</b> |
| 2400 | @code |
| 2401 | MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr; |
| 2402 | |
| 2403 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE); |
| 2404 | AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64); |
| 2405 | @endcode |
| 2406 | **/ |
| 2407 | #define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4 |
| 2408 | |
| 2409 | /** |
| 2410 | MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE |
| 2411 | **/ |
| 2412 | typedef union { |
| 2413 | /// |
| 2414 | /// Individual bit fields |
| 2415 | /// |
| 2416 | struct { |
| 2417 | /// |
| 2418 | /// [Bits 2:0] MemType PRMRR BASE MemType. |
| 2419 | /// |
| 2420 | UINT32 MemTypePRMRRBASEMemType:3; |
| 2421 | UINT32 Reserved1:9; |
| 2422 | /// |
| 2423 | /// [Bits 31:12] Base PRMRR Base Address. |
| 2424 | /// |
| 2425 | UINT32 BasePRMRRBaseAddress:20; |
| 2426 | /// |
| 2427 | /// [Bits 45:32] Base PRMRR Base Address. |
| 2428 | /// |
| 2429 | UINT32 Fix_Me_1:14; |
| 2430 | UINT32 Reserved2:18; |
| 2431 | } Bits; |
| 2432 | /// |
| 2433 | /// All bit fields as a 64-bit value |
| 2434 | /// |
| 2435 | UINT64 Uint64; |
| 2436 | } MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER; |
| 2437 | |
| 2438 | |
| 2439 | /** |
| 2440 | Core. Processor Reserved Memory Range Register - Physical Mask Control |
| 2441 | Register (R/W). |
| 2442 | |
| 2443 | @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5) |
| 2444 | @param EAX Lower 32-bits of MSR value. |
| 2445 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER. |
| 2446 | @param EDX Upper 32-bits of MSR value. |
| 2447 | Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER. |
| 2448 | |
| 2449 | <b>Example usage</b> |
| 2450 | @code |
| 2451 | MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr; |
| 2452 | |
| 2453 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK); |
| 2454 | AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64); |
| 2455 | @endcode |
| 2456 | **/ |
| 2457 | #define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5 |
| 2458 | |
| 2459 | /** |
| 2460 | MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK |
| 2461 | **/ |
| 2462 | typedef union { |
| 2463 | /// |
| 2464 | /// Individual bit fields |
| 2465 | /// |
| 2466 | struct { |
| 2467 | UINT32 Reserved1:10; |
| 2468 | /// |
| 2469 | /// [Bit 10] Lock Lock bit for the PRMRR. |
| 2470 | /// |
| 2471 | UINT32 Fix_Me_1:1; |
| 2472 | /// |
| 2473 | /// [Bit 11] VLD Enable bit for the PRMRR. |
| 2474 | /// |
| 2475 | UINT32 VLD:1; |
| 2476 | /// |
| 2477 | /// [Bits 31:12] Mask PRMRR MASK bits. |
| 2478 | /// |
| 2479 | UINT32 Fix_Me_2:20; |
| 2480 | /// |
| 2481 | /// [Bits 45:32] Mask PRMRR MASK bits. |
| 2482 | /// |
| 2483 | UINT32 Fix_Me_3:14; |
| 2484 | UINT32 Reserved2:18; |
| 2485 | } Bits; |
| 2486 | /// |
| 2487 | /// All bit fields as a 64-bit value |
| 2488 | /// |
| 2489 | UINT64 Uint64; |
| 2490 | } MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER; |
| 2491 | |
| 2492 | |
| 2493 | /** |
| 2494 | Core. Valid PRMRR Configurations (R/W). |
| 2495 | |
| 2496 | @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB) |
| 2497 | @param EAX Lower 32-bits of MSR value. |
| 2498 | Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER. |
| 2499 | @param EDX Upper 32-bits of MSR value. |
| 2500 | Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER. |
| 2501 | |
| 2502 | <b>Example usage</b> |
| 2503 | @code |
| 2504 | MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr; |
| 2505 | |
| 2506 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG); |
| 2507 | AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64); |
| 2508 | @endcode |
| 2509 | **/ |
| 2510 | #define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB |
| 2511 | |
| 2512 | /** |
| 2513 | MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG |
| 2514 | **/ |
| 2515 | typedef union { |
| 2516 | /// |
| 2517 | /// Individual bit fields |
| 2518 | /// |
| 2519 | struct { |
| 2520 | /// |
| 2521 | /// [Bit 0] 1M supported MEE size. |
| 2522 | /// |
| 2523 | UINT32 Fix_Me_1:1; |
| 2524 | UINT32 Reserved1:4; |
| 2525 | /// |
| 2526 | /// [Bit 5] 32M supported MEE size. |
| 2527 | /// |
| 2528 | UINT32 Fix_Me_2:1; |
| 2529 | /// |
| 2530 | /// [Bit 6] 64M supported MEE size. |
| 2531 | /// |
| 2532 | UINT32 Fix_Me_3:1; |
| 2533 | /// |
| 2534 | /// [Bit 7] 128M supported MEE size. |
| 2535 | /// |
| 2536 | UINT32 Fix_Me_4:1; |
| 2537 | UINT32 Reserved2:24; |
| 2538 | UINT32 Reserved3:32; |
| 2539 | } Bits; |
| 2540 | /// |
| 2541 | /// All bit fields as a 32-bit value |
| 2542 | /// |
| 2543 | UINT32 Uint32; |
| 2544 | /// |
| 2545 | /// All bit fields as a 64-bit value |
| 2546 | /// |
| 2547 | UINT64 Uint64; |
| 2548 | } MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER; |
| 2549 | |
| 2550 | |
| 2551 | /** |
| 2552 | Package. (R/W) The PRMRR range is used to protect Xucode memory from |
| 2553 | unauthorized reads and writes. Any IO access to this range is aborted. This |
| 2554 | register controls the location of the PRMRR range by indicating its starting |
| 2555 | address. It functions in tandem with the PRMRR mask register. |
| 2556 | |
| 2557 | @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4) |
| 2558 | @param EAX Lower 32-bits of MSR value. |
| 2559 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER. |
| 2560 | @param EDX Upper 32-bits of MSR value. |
| 2561 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER. |
| 2562 | |
| 2563 | <b>Example usage</b> |
| 2564 | @code |
| 2565 | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr; |
| 2566 | |
| 2567 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE); |
| 2568 | AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64); |
| 2569 | @endcode |
| 2570 | **/ |
| 2571 | #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4 |
| 2572 | |
| 2573 | /** |
| 2574 | MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE |
| 2575 | **/ |
| 2576 | typedef union { |
| 2577 | /// |
| 2578 | /// Individual bit fields |
| 2579 | /// |
| 2580 | struct { |
| 2581 | UINT32 Reserved1:12; |
| 2582 | /// |
| 2583 | /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the |
| 2584 | /// base address memory range which is allocated to PRMRR memory. |
| 2585 | /// |
| 2586 | UINT32 Fix_Me_1:20; |
| 2587 | /// |
| 2588 | /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the |
| 2589 | /// base address memory range which is allocated to PRMRR memory. |
| 2590 | /// |
| 2591 | UINT32 Fix_Me_2:7; |
| 2592 | UINT32 Reserved2:25; |
| 2593 | } Bits; |
| 2594 | /// |
| 2595 | /// All bit fields as a 64-bit value |
| 2596 | /// |
| 2597 | UINT64 Uint64; |
| 2598 | } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER; |
| 2599 | |
| 2600 | |
| 2601 | /** |
| 2602 | Package. (R/W) This register controls the size of the PRMRR range by |
| 2603 | indicating which address bits must match the PRMRR base register value. |
| 2604 | |
| 2605 | @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5) |
| 2606 | @param EAX Lower 32-bits of MSR value. |
| 2607 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER. |
| 2608 | @param EDX Upper 32-bits of MSR value. |
| 2609 | Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER. |
| 2610 | |
| 2611 | <b>Example usage</b> |
| 2612 | @code |
| 2613 | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr; |
| 2614 | |
| 2615 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK); |
| 2616 | AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64); |
| 2617 | @endcode |
| 2618 | **/ |
| 2619 | #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5 |
| 2620 | |
| 2621 | /** |
| 2622 | MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK |
| 2623 | **/ |
| 2624 | typedef union { |
| 2625 | /// |
| 2626 | /// Individual bit fields |
| 2627 | /// |
| 2628 | struct { |
| 2629 | UINT32 Reserved1:10; |
| 2630 | /// |
| 2631 | /// [Bit 10] Lock Setting this bit locks all writeable settings in this |
| 2632 | /// register, including itself. |
| 2633 | /// |
| 2634 | UINT32 Fix_Me_1:1; |
| 2635 | /// |
| 2636 | /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and |
| 2637 | /// valid. |
| 2638 | /// |
| 2639 | UINT32 Fix_Me_2:1; |
| 2640 | UINT32 Reserved2:20; |
| 2641 | UINT32 Reserved3:32; |
| 2642 | } Bits; |
| 2643 | /// |
| 2644 | /// All bit fields as a 32-bit value |
| 2645 | /// |
| 2646 | UINT32 Uint32; |
| 2647 | /// |
| 2648 | /// All bit fields as a 64-bit value |
| 2649 | /// |
| 2650 | UINT64 Uint64; |
| 2651 | } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER; |
| 2652 | |
| 2653 | /** |
| 2654 | Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits |
| 2655 | for the LLC and Ring. |
| 2656 | |
| 2657 | @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620) |
| 2658 | @param EAX Lower 32-bits of MSR value. |
| 2659 | Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER. |
| 2660 | @param EDX Upper 32-bits of MSR value. |
| 2661 | Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER. |
| 2662 | |
| 2663 | <b>Example usage</b> |
| 2664 | @code |
| 2665 | MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr; |
| 2666 | |
| 2667 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT); |
| 2668 | AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64); |
| 2669 | @endcode |
| 2670 | **/ |
| 2671 | #define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620 |
| 2672 | |
| 2673 | /** |
| 2674 | MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT |
| 2675 | **/ |
| 2676 | typedef union { |
| 2677 | /// |
| 2678 | /// Individual bit fields |
| 2679 | /// |
| 2680 | struct { |
| 2681 | /// |
| 2682 | /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the |
| 2683 | /// LLC/Ring. |
| 2684 | /// |
| 2685 | UINT32 Fix_Me_1:7; |
| 2686 | UINT32 Reserved1:1; |
| 2687 | /// |
| 2688 | /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum |
| 2689 | /// possible ratio of the LLC/Ring. |
| 2690 | /// |
| 2691 | UINT32 Fix_Me_2:7; |
| 2692 | UINT32 Reserved2:17; |
| 2693 | UINT32 Reserved3:32; |
| 2694 | } Bits; |
| 2695 | /// |
| 2696 | /// All bit fields as a 32-bit value |
| 2697 | /// |
| 2698 | UINT32 Uint32; |
| 2699 | /// |
| 2700 | /// All bit fields as a 64-bit value |
| 2701 | /// |
| 2702 | UINT64 Uint64; |
| 2703 | } MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER; |
| 2704 | |
| 2705 | |
| 2706 | /** |
| 2707 | Branch Monitoring Global Control (R/W). |
| 2708 | |
| 2709 | @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350) |
| 2710 | @param EAX Lower 32-bits of MSR value. |
| 2711 | Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER. |
| 2712 | @param EDX Upper 32-bits of MSR value. |
| 2713 | Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER. |
| 2714 | |
| 2715 | <b>Example usage</b> |
| 2716 | @code |
| 2717 | MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr; |
| 2718 | |
| 2719 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL); |
| 2720 | AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64); |
| 2721 | @endcode |
| 2722 | **/ |
| 2723 | #define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350 |
| 2724 | |
| 2725 | /** |
| 2726 | MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL |
| 2727 | **/ |
| 2728 | typedef union { |
| 2729 | /// |
| 2730 | /// Individual bit fields |
| 2731 | /// |
| 2732 | struct { |
| 2733 | /// |
| 2734 | /// [Bit 0] EnMonitoring Global enable for branch monitoring. |
| 2735 | /// |
| 2736 | UINT32 EnMonitoring:1; |
| 2737 | /// |
| 2738 | /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold |
| 2739 | /// trip. The branch monitoring event handler is signaled via the existing |
| 2740 | /// PMI signaling mechanism as programmed from the corresponding local |
| 2741 | /// APIC LVT entry. |
| 2742 | /// |
| 2743 | UINT32 EnExcept:1; |
| 2744 | /// |
| 2745 | /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause |
| 2746 | /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a |
| 2747 | /// triggering condition occurs and this bit is enabled. |
| 2748 | /// |
| 2749 | UINT32 EnLBRFrz:1; |
| 2750 | /// |
| 2751 | /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event |
| 2752 | /// triggering and LBR freeze actions are disabled when operating at VMX |
| 2753 | /// non-root operation. |
| 2754 | /// |
| 2755 | UINT32 DisableInGuest:1; |
| 2756 | UINT32 Reserved1:4; |
| 2757 | /// |
| 2758 | /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 - |
| 2759 | /// 1023 are supported. Once the Window counter reaches the WindowSize |
| 2760 | /// count both the Window Counter and all Branch Monitoring Counters are |
| 2761 | /// cleared. |
| 2762 | /// |
| 2763 | UINT32 WindowSize:10; |
| 2764 | UINT32 Reserved2:6; |
| 2765 | /// |
| 2766 | /// [Bits 25:24] WindowCntSel Window event count select: '00 = |
| 2767 | /// Instructions retired. '01 = Branch instructions retired '10 = Return |
| 2768 | /// instructions retired. '11 = Indirect branch instructions retired. |
| 2769 | /// |
| 2770 | UINT32 WindowCntSel:2; |
| 2771 | /// |
| 2772 | /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring |
| 2773 | /// event triggering condition is true only if all enabled counters' |
| 2774 | /// threshold conditions are true. When '0', the threshold tripping |
| 2775 | /// condition is true if any enabled counters' threshold is true. |
| 2776 | /// |
| 2777 | UINT32 CntAndMode:1; |
| 2778 | UINT32 Reserved3:5; |
| 2779 | UINT32 Reserved4:32; |
| 2780 | } Bits; |
| 2781 | /// |
| 2782 | /// All bit fields as a 32-bit value |
| 2783 | /// |
| 2784 | UINT32 Uint32; |
| 2785 | /// |
| 2786 | /// All bit fields as a 64-bit value |
| 2787 | /// |
| 2788 | UINT64 Uint64; |
| 2789 | } MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER; |
| 2790 | |
| 2791 | /** |
| 2792 | Branch Monitoring Global Status (R/W). |
| 2793 | |
| 2794 | @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351) |
| 2795 | @param EAX Lower 32-bits of MSR value. |
| 2796 | Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER. |
| 2797 | @param EDX Upper 32-bits of MSR value. |
| 2798 | Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER. |
| 2799 | |
| 2800 | <b>Example usage</b> |
| 2801 | @code |
| 2802 | MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr; |
| 2803 | |
| 2804 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS); |
| 2805 | AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64); |
| 2806 | @endcode |
| 2807 | **/ |
| 2808 | #define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351 |
| 2809 | |
| 2810 | /** |
| 2811 | MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS |
| 2812 | **/ |
| 2813 | typedef union { |
| 2814 | /// |
| 2815 | /// Individual bit fields |
| 2816 | /// |
| 2817 | struct { |
| 2818 | /// |
| 2819 | /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch |
| 2820 | /// Monitoring event signaling is blocked until this bit is cleared by |
| 2821 | /// software. |
| 2822 | /// |
| 2823 | UINT32 BranchMonitoringEventSignaled:1; |
| 2824 | /// |
| 2825 | /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is |
| 2826 | /// considered valid for sampling by branch monitoring software. |
| 2827 | /// |
| 2828 | UINT32 LBRsValid:1; |
| 2829 | UINT32 Reserved1:6; |
| 2830 | /// |
| 2831 | /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This |
| 2832 | /// status bit is sticky and once set requires clearing by software. |
| 2833 | /// Counter operation continues independent of the state of the bit. |
| 2834 | /// |
| 2835 | UINT32 CntrHit0:1; |
| 2836 | /// |
| 2837 | /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This |
| 2838 | /// status bit is sticky and once set requires clearing by software. |
| 2839 | /// Counter operation continues independent of the state of the bit. |
| 2840 | /// |
| 2841 | UINT32 CntrHit1:1; |
| 2842 | UINT32 Reserved2:6; |
| 2843 | /// |
| 2844 | /// [Bits 25:16] CountWindow The current value of the window counter. The |
| 2845 | /// count value is frozen on a valid branch monitoring triggering |
| 2846 | /// condition. This is a 10-bit unsigned value. |
| 2847 | /// |
| 2848 | UINT32 CountWindow:10; |
| 2849 | UINT32 Reserved3:6; |
| 2850 | /// |
| 2851 | /// [Bits 39:32] Count0 The current value of counter 0 updated after each |
| 2852 | /// occurrence of the event being counted. The count value is frozen on a |
| 2853 | /// valid branch monitoring triggering condition (in which case CntrHit0 |
| 2854 | /// will also be set). This is an 8-bit signed value (2's complement). |
| 2855 | /// Heuristic events which only increment will saturate and freeze at |
| 2856 | /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum |
| 2857 | /// value 0x7F (+127) and minimum value 0x80 (-128). |
| 2858 | /// |
| 2859 | UINT32 Count0:8; |
| 2860 | /// |
| 2861 | /// [Bits 47:40] Count1 The current value of counter 1 updated after each |
| 2862 | /// occurrence of the event being counted. The count value is frozen on a |
| 2863 | /// valid branch monitoring triggering condition (in which case CntrHit1 |
| 2864 | /// will also be set). This is an 8-bit signed value (2's complement). |
| 2865 | /// Heuristic events which only increment will saturate and freeze at |
| 2866 | /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum |
| 2867 | /// value 0x7F (+127) and minimum value 0x80 (-128). |
| 2868 | /// |
| 2869 | UINT32 Count1:8; |
| 2870 | UINT32 Reserved4:16; |
| 2871 | } Bits; |
| 2872 | /// |
| 2873 | /// All bit fields as a 32-bit value |
| 2874 | /// |
| 2875 | UINT32 Uint32; |
| 2876 | /// |
| 2877 | /// All bit fields as a 64-bit value |
| 2878 | /// |
| 2879 | UINT64 Uint64; |
| 2880 | } MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER; |
| 2881 | |
| 2882 | |
| 2883 | /** |
| 2884 | Package. Package C3 Residency Counter (R/O). Note: C-state values are |
| 2885 | processor specific C-state code names, unrelated to MWAIT extension C-state |
| 2886 | parameters or ACPI C-states. |
| 2887 | |
| 2888 | @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8) |
| 2889 | @param EAX Lower 32-bits of MSR value. |
| 2890 | @param EDX Upper 32-bits of MSR value. |
| 2891 | |
| 2892 | <b>Example usage</b> |
| 2893 | @code |
| 2894 | UINT64 Msr; |
| 2895 | |
| 2896 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY); |
| 2897 | @endcode |
| 2898 | **/ |
| 2899 | #define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8 |
| 2900 | |
| 2901 | |
| 2902 | /** |
| 2903 | Core. Core C1 Residency Counter (R/O). Value since last reset for the Core |
| 2904 | C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC). |
| 2905 | This counter counts in case both of the core's threads are in an idle state |
| 2906 | and at least one of the core's thread residency is in a C1 state or in one |
| 2907 | of its sub states. The counter is updated only after a core C state exit. |
| 2908 | Note: Always reads 0 if core C1 is unsupported. A value of zero indicates |
| 2909 | that this processor does not support core C1 or never entered core C1 level |
| 2910 | state. |
| 2911 | |
| 2912 | @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660) |
| 2913 | @param EAX Lower 32-bits of MSR value. |
| 2914 | @param EDX Upper 32-bits of MSR value. |
| 2915 | |
| 2916 | <b>Example usage</b> |
| 2917 | @code |
| 2918 | UINT64 Msr; |
| 2919 | |
| 2920 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY); |
| 2921 | @endcode |
| 2922 | **/ |
| 2923 | #define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660 |
| 2924 | |
| 2925 | |
| 2926 | /** |
| 2927 | Core. Core C3 Residency Counter (R/O). Will always return 0. |
| 2928 | |
| 2929 | @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662) |
| 2930 | @param EAX Lower 32-bits of MSR value. |
| 2931 | @param EDX Upper 32-bits of MSR value. |
| 2932 | |
| 2933 | <b>Example usage</b> |
| 2934 | @code |
| 2935 | UINT64 Msr; |
| 2936 | |
| 2937 | Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY); |
| 2938 | @endcode |
| 2939 | **/ |
| 2940 | #define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662 |
| 2941 | |
| 2942 | |
| 2943 | /** |
| 2944 | Package. Protected Processor Inventory Number Enable Control (R/W). |
| 2945 | |
| 2946 | @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E) |
| 2947 | @param EAX Lower 32-bits of MSR value. |
| 2948 | Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER. |
| 2949 | @param EDX Upper 32-bits of MSR value. |
| 2950 | Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER. |
| 2951 | |
| 2952 | <b>Example usage</b> |
| 2953 | @code |
| 2954 | MSR_SKYLAKE_PPIN_CTL_REGISTER Msr; |
| 2955 | |
| 2956 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL); |
| 2957 | AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64); |
| 2958 | @endcode |
| 2959 | **/ |
| 2960 | #define MSR_SKYLAKE_PPIN_CTL 0x0000004E |
| 2961 | |
| 2962 | /** |
| 2963 | MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL |
| 2964 | **/ |
| 2965 | typedef union { |
| 2966 | /// |
| 2967 | /// Individual bit fields |
| 2968 | /// |
| 2969 | struct { |
| 2970 | /// |
| 2971 | /// [Bit 0] LockOut (R/WO) See Table 2-25. |
| 2972 | /// |
| 2973 | UINT32 LockOut:1; |
| 2974 | /// |
| 2975 | /// [Bit 1] Enable_PPIN (R/W) See Table 2-25. |
| 2976 | /// |
| 2977 | UINT32 Enable_PPIN:1; |
| 2978 | UINT32 Reserved1:30; |
| 2979 | UINT32 Reserved2:32; |
| 2980 | } Bits; |
| 2981 | /// |
| 2982 | /// All bit fields as a 32-bit value |
| 2983 | /// |
| 2984 | UINT32 Uint32; |
| 2985 | /// |
| 2986 | /// All bit fields as a 64-bit value |
| 2987 | /// |
| 2988 | UINT64 Uint64; |
| 2989 | } MSR_SKYLAKE_PPIN_CTL_REGISTER; |
| 2990 | |
| 2991 | |
| 2992 | /** |
| 2993 | Package. Protected Processor Inventory Number (R/O). Protected Processor |
| 2994 | Inventory Number (R/O) See Table 2-25. |
| 2995 | |
| 2996 | @param ECX MSR_SKYLAKE_PPIN (0x0000004F) |
| 2997 | @param EAX Lower 32-bits of MSR value. |
| 2998 | @param EDX Upper 32-bits of MSR value. |
| 2999 | |
| 3000 | <b>Example usage</b> |
| 3001 | @code |
| 3002 | UINT64 Msr; |
| 3003 | |
| 3004 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN); |
| 3005 | @endcode |
| 3006 | **/ |
| 3007 | #define MSR_SKYLAKE_PPIN 0x0000004F |
| 3008 | |
| 3009 | |
| 3010 | /** |
| 3011 | Package. Platform Information Contains power management and other model |
| 3012 | specific features enumeration. See http://biosbits.org. |
| 3013 | |
| 3014 | @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE) |
| 3015 | @param EAX Lower 32-bits of MSR value. |
| 3016 | Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER. |
| 3017 | @param EDX Upper 32-bits of MSR value. |
| 3018 | Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER. |
| 3019 | |
| 3020 | <b>Example usage</b> |
| 3021 | @code |
| 3022 | MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr; |
| 3023 | |
| 3024 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO); |
| 3025 | AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64); |
| 3026 | @endcode |
| 3027 | **/ |
| 3028 | #define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE |
| 3029 | |
| 3030 | /** |
| 3031 | MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO |
| 3032 | **/ |
| 3033 | typedef union { |
| 3034 | /// |
| 3035 | /// Individual bit fields |
| 3036 | /// |
| 3037 | struct { |
| 3038 | UINT32 Reserved1:8; |
| 3039 | /// |
| 3040 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25. |
| 3041 | /// |
| 3042 | UINT32 MaximumNon_TurboRatio:8; |
| 3043 | UINT32 Reserved2:7; |
| 3044 | /// |
| 3045 | /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25. |
| 3046 | /// |
| 3047 | UINT32 PPIN_CAP:1; |
| 3048 | UINT32 Reserved3:4; |
| 3049 | /// |
| 3050 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See |
| 3051 | /// Table 2-25. |
| 3052 | /// |
| 3053 | UINT32 ProgrammableRatioLimit:1; |
| 3054 | /// |
| 3055 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See |
| 3056 | /// Table 2-25. |
| 3057 | /// |
| 3058 | UINT32 ProgrammableTDPLimit:1; |
| 3059 | /// |
| 3060 | /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25. |
| 3061 | /// |
| 3062 | UINT32 ProgrammableTJOFFSET:1; |
| 3063 | UINT32 Reserved4:1; |
| 3064 | UINT32 Reserved5:8; |
| 3065 | /// |
| 3066 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25. |
| 3067 | /// |
| 3068 | UINT32 MaximumEfficiencyRatio:8; |
| 3069 | UINT32 Reserved6:16; |
| 3070 | } Bits; |
| 3071 | /// |
| 3072 | /// All bit fields as a 64-bit value |
| 3073 | /// |
| 3074 | UINT64 Uint64; |
| 3075 | } MSR_SKYLAKE_PLATFORM_INFO_REGISTER; |
| 3076 | |
| 3077 | |
| 3078 | /** |
| 3079 | Core. C-State Configuration Control (R/W) Note: C-state values are processor |
| 3080 | specific C-state code names, unrelated to MWAIT extension C-state parameters |
| 3081 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__. |
| 3082 | |
| 3083 | @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2) |
| 3084 | @param EAX Lower 32-bits of MSR value. |
| 3085 | Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 3086 | @param EDX Upper 32-bits of MSR value. |
| 3087 | Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 3088 | |
| 3089 | <b>Example usage</b> |
| 3090 | @code |
| 3091 | MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; |
| 3092 | |
| 3093 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL); |
| 3094 | AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); |
| 3095 | @endcode |
| 3096 | **/ |
| 3097 | #define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2 |
| 3098 | |
| 3099 | /** |
| 3100 | MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL |
| 3101 | **/ |
| 3102 | typedef union { |
| 3103 | /// |
| 3104 | /// Individual bit fields |
| 3105 | /// |
| 3106 | struct { |
| 3107 | /// |
| 3108 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest |
| 3109 | /// processor-specific C-state code name (consuming the least power) for |
| 3110 | /// the package. The default is set as factory-configured package Cstate |
| 3111 | /// limit. The following C-state code name encodings are supported: 000b: |
| 3112 | /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) |
| 3113 | /// 011b: C6 (retention) 111b: No Package C state limits. All C states |
| 3114 | /// supported by the processor are available. |
| 3115 | /// |
| 3116 | UINT32 C_StateLimit:3; |
| 3117 | UINT32 Reserved1:7; |
| 3118 | /// |
| 3119 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W). |
| 3120 | /// |
| 3121 | UINT32 MWAITRedirectionEnable:1; |
| 3122 | UINT32 Reserved2:4; |
| 3123 | /// |
| 3124 | /// [Bit 15] CFG Lock (R/WO). |
| 3125 | /// |
| 3126 | UINT32 CFGLock:1; |
| 3127 | /// |
| 3128 | /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor |
| 3129 | /// will convert HALT or MWAT(C1) to MWAIT(C6). |
| 3130 | /// |
| 3131 | UINT32 AutomaticC_StateConversionEnable:1; |
| 3132 | UINT32 Reserved3:8; |
| 3133 | /// |
| 3134 | /// [Bit 25] C3 State Auto Demotion Enable (R/W). |
| 3135 | /// |
| 3136 | UINT32 C3StateAutoDemotionEnable:1; |
| 3137 | /// |
| 3138 | /// [Bit 26] C1 State Auto Demotion Enable (R/W). |
| 3139 | /// |
| 3140 | UINT32 C1StateAutoDemotionEnable:1; |
| 3141 | /// |
| 3142 | /// [Bit 27] Enable C3 Undemotion (R/W). |
| 3143 | /// |
| 3144 | UINT32 EnableC3Undemotion:1; |
| 3145 | /// |
| 3146 | /// [Bit 28] Enable C1 Undemotion (R/W). |
| 3147 | /// |
| 3148 | UINT32 EnableC1Undemotion:1; |
| 3149 | /// |
| 3150 | /// [Bit 29] Package C State Demotion Enable (R/W). |
| 3151 | /// |
| 3152 | UINT32 CStateDemotionEnable:1; |
| 3153 | /// |
| 3154 | /// [Bit 30] Package C State UnDemotion Enable (R/W). |
| 3155 | /// |
| 3156 | UINT32 CStateUnDemotionEnable:1; |
| 3157 | UINT32 Reserved4:1; |
| 3158 | UINT32 Reserved5:32; |
| 3159 | } Bits; |
| 3160 | /// |
| 3161 | /// All bit fields as a 32-bit value |
| 3162 | /// |
| 3163 | UINT32 Uint32; |
| 3164 | /// |
| 3165 | /// All bit fields as a 64-bit value |
| 3166 | /// |
| 3167 | UINT64 Uint64; |
| 3168 | } MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER; |
| 3169 | |
| 3170 | |
| 3171 | /** |
| 3172 | Thread. Global Machine Check Capability (R/O). |
| 3173 | |
| 3174 | @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179) |
| 3175 | @param EAX Lower 32-bits of MSR value. |
| 3176 | Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER. |
| 3177 | @param EDX Upper 32-bits of MSR value. |
| 3178 | Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER. |
| 3179 | |
| 3180 | <b>Example usage</b> |
| 3181 | @code |
| 3182 | MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr; |
| 3183 | |
| 3184 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP); |
| 3185 | @endcode |
| 3186 | **/ |
| 3187 | #define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179 |
| 3188 | |
| 3189 | /** |
| 3190 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP |
| 3191 | **/ |
| 3192 | typedef union { |
| 3193 | /// |
| 3194 | /// Individual bit fields |
| 3195 | /// |
| 3196 | struct { |
| 3197 | /// |
| 3198 | /// [Bits 7:0] Count. |
| 3199 | /// |
| 3200 | UINT32 Count:8; |
| 3201 | /// |
| 3202 | /// [Bit 8] MCG_CTL_P. |
| 3203 | /// |
| 3204 | UINT32 MCG_CTL_P:1; |
| 3205 | /// |
| 3206 | /// [Bit 9] MCG_EXT_P. |
| 3207 | /// |
| 3208 | UINT32 MCG_EXT_P:1; |
| 3209 | /// |
| 3210 | /// [Bit 10] MCP_CMCI_P. |
| 3211 | /// |
| 3212 | UINT32 MCP_CMCI_P:1; |
| 3213 | /// |
| 3214 | /// [Bit 11] MCG_TES_P. |
| 3215 | /// |
| 3216 | UINT32 MCG_TES_P:1; |
| 3217 | UINT32 Reserved1:4; |
| 3218 | /// |
| 3219 | /// [Bits 23:16] MCG_EXT_CNT. |
| 3220 | /// |
| 3221 | UINT32 MCG_EXT_CNT:8; |
| 3222 | /// |
| 3223 | /// [Bit 24] MCG_SER_P. |
| 3224 | /// |
| 3225 | UINT32 MCG_SER_P:1; |
| 3226 | /// |
| 3227 | /// [Bit 25] MCG_EM_P. |
| 3228 | /// |
| 3229 | UINT32 MCG_EM_P:1; |
| 3230 | /// |
| 3231 | /// [Bit 26] MCG_ELOG_P. |
| 3232 | /// |
| 3233 | UINT32 MCG_ELOG_P:1; |
| 3234 | UINT32 Reserved2:5; |
| 3235 | UINT32 Reserved3:32; |
| 3236 | } Bits; |
| 3237 | /// |
| 3238 | /// All bit fields as a 32-bit value |
| 3239 | /// |
| 3240 | UINT32 Uint32; |
| 3241 | /// |
| 3242 | /// All bit fields as a 64-bit value |
| 3243 | /// |
| 3244 | UINT64 Uint64; |
| 3245 | } MSR_SKYLAKE_IA32_MCG_CAP_REGISTER; |
| 3246 | |
| 3247 | |
| 3248 | /** |
| 3249 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability |
| 3250 | Enhancement. Accessible only while in SMM. |
| 3251 | |
| 3252 | @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D) |
| 3253 | @param EAX Lower 32-bits of MSR value. |
| 3254 | Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER. |
| 3255 | @param EDX Upper 32-bits of MSR value. |
| 3256 | Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER. |
| 3257 | |
| 3258 | <b>Example usage</b> |
| 3259 | @code |
| 3260 | MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr; |
| 3261 | |
| 3262 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP); |
| 3263 | AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64); |
| 3264 | @endcode |
| 3265 | **/ |
| 3266 | #define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D |
| 3267 | |
| 3268 | /** |
| 3269 | MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP |
| 3270 | **/ |
| 3271 | typedef union { |
| 3272 | /// |
| 3273 | /// Individual bit fields |
| 3274 | /// |
| 3275 | struct { |
| 3276 | UINT32 Reserved1:32; |
| 3277 | UINT32 Reserved2:26; |
| 3278 | /// |
| 3279 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the |
| 3280 | /// SMM code access restriction is supported and a host-space interface is |
| 3281 | /// available to SMM handler. |
| 3282 | /// |
| 3283 | UINT32 SMM_Code_Access_Chk:1; |
| 3284 | /// |
| 3285 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the |
| 3286 | /// SMM long flow indicator is supported and a host-space interface is |
| 3287 | /// available to SMM handler. |
| 3288 | /// |
| 3289 | UINT32 Long_Flow_Indication:1; |
| 3290 | UINT32 Reserved3:4; |
| 3291 | } Bits; |
| 3292 | /// |
| 3293 | /// All bit fields as a 64-bit value |
| 3294 | /// |
| 3295 | UINT64 Uint64; |
| 3296 | } MSR_SKYLAKE_SMM_MCA_CAP_REGISTER; |
| 3297 | |
| 3298 | |
| 3299 | /** |
| 3300 | Package. Temperature Target. |
| 3301 | |
| 3302 | @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2) |
| 3303 | @param EAX Lower 32-bits of MSR value. |
| 3304 | Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER. |
| 3305 | @param EDX Upper 32-bits of MSR value. |
| 3306 | Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER. |
| 3307 | |
| 3308 | <b>Example usage</b> |
| 3309 | @code |
| 3310 | MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr; |
| 3311 | |
| 3312 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET); |
| 3313 | AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64); |
| 3314 | @endcode |
| 3315 | **/ |
| 3316 | #define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2 |
| 3317 | |
| 3318 | /** |
| 3319 | MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET |
| 3320 | **/ |
| 3321 | typedef union { |
| 3322 | /// |
| 3323 | /// Individual bit fields |
| 3324 | /// |
| 3325 | struct { |
| 3326 | UINT32 Reserved1:16; |
| 3327 | /// |
| 3328 | /// [Bits 23:16] Temperature Target (RO) See Table 2-25. |
| 3329 | /// |
| 3330 | UINT32 TemperatureTarget:8; |
| 3331 | /// |
| 3332 | /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25. |
| 3333 | /// |
| 3334 | UINT32 TCCActivationOffset:4; |
| 3335 | UINT32 Reserved2:4; |
| 3336 | UINT32 Reserved3:32; |
| 3337 | } Bits; |
| 3338 | /// |
| 3339 | /// All bit fields as a 32-bit value |
| 3340 | /// |
| 3341 | UINT32 Uint32; |
| 3342 | /// |
| 3343 | /// All bit fields as a 64-bit value |
| 3344 | /// |
| 3345 | UINT64 Uint64; |
| 3346 | } MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER; |
| 3347 | |
| 3348 | /** |
| 3349 | Package. This register defines the active core ranges for each frequency |
| 3350 | point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must |
| 3351 | be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. |
| 3352 | The last valid entry must have NUMCORE >= the number of cores in the SKU. If |
| 3353 | any of the rules above are broken, the configuration is silently rejected. |
| 3354 | |
| 3355 | @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE) |
| 3356 | @param EAX Lower 32-bits of MSR value. |
| 3357 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER. |
| 3358 | @param EDX Upper 32-bits of MSR value. |
| 3359 | Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER. |
| 3360 | |
| 3361 | <b>Example usage</b> |
| 3362 | @code |
| 3363 | MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr; |
| 3364 | |
| 3365 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES); |
| 3366 | AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64); |
| 3367 | @endcode |
| 3368 | **/ |
| 3369 | #define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE |
| 3370 | |
| 3371 | /** |
| 3372 | MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES |
| 3373 | **/ |
| 3374 | typedef union { |
| 3375 | /// |
| 3376 | /// Individual bit fields |
| 3377 | /// |
| 3378 | struct { |
| 3379 | /// |
| 3380 | /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency |
| 3381 | /// point. |
| 3382 | /// |
| 3383 | UINT32 NUMCORE_0:8; |
| 3384 | /// |
| 3385 | /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each |
| 3386 | /// frequency point. |
| 3387 | /// |
| 3388 | UINT32 NUMCORE_1:8; |
| 3389 | /// |
| 3390 | /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each |
| 3391 | /// frequency point. |
| 3392 | /// |
| 3393 | UINT32 NUMCORE_2:8; |
| 3394 | /// |
| 3395 | /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each |
| 3396 | /// frequency point. |
| 3397 | /// |
| 3398 | UINT32 NUMCORE_3:8; |
| 3399 | /// |
| 3400 | /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each |
| 3401 | /// frequency point. |
| 3402 | /// |
| 3403 | UINT32 NUMCORE_4:8; |
| 3404 | /// |
| 3405 | /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each |
| 3406 | /// frequency point. |
| 3407 | /// |
| 3408 | UINT32 NUMCORE_5:8; |
| 3409 | /// |
| 3410 | /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each |
| 3411 | /// frequency point. |
| 3412 | /// |
| 3413 | UINT32 NUMCORE_6:8; |
| 3414 | /// |
| 3415 | /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each |
| 3416 | /// frequency point. |
| 3417 | /// |
| 3418 | UINT32 NUMCORE_7:8; |
| 3419 | } Bits; |
| 3420 | /// |
| 3421 | /// All bit fields as a 64-bit value |
| 3422 | /// |
| 3423 | UINT64 Uint64; |
| 3424 | } MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER; |
| 3425 | |
| 3426 | |
| 3427 | /** |
| 3428 | Package. Unit Multipliers Used in RAPL Interfaces (R/O). |
| 3429 | |
| 3430 | @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606) |
| 3431 | @param EAX Lower 32-bits of MSR value. |
| 3432 | Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER. |
| 3433 | @param EDX Upper 32-bits of MSR value. |
| 3434 | Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER. |
| 3435 | |
| 3436 | <b>Example usage</b> |
| 3437 | @code |
| 3438 | MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr; |
| 3439 | |
| 3440 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT); |
| 3441 | @endcode |
| 3442 | **/ |
| 3443 | #define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606 |
| 3444 | |
| 3445 | /** |
| 3446 | MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT |
| 3447 | **/ |
| 3448 | typedef union { |
| 3449 | /// |
| 3450 | /// Individual bit fields |
| 3451 | /// |
| 3452 | struct { |
| 3453 | /// |
| 3454 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". |
| 3455 | /// |
| 3456 | UINT32 PowerUnits:4; |
| 3457 | UINT32 Reserved1:4; |
| 3458 | /// |
| 3459 | /// [Bits 12:8] Package. Energy Status Units Energy related information |
| 3460 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an |
| 3461 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 |
| 3462 | /// micro-joules). |
| 3463 | /// |
| 3464 | UINT32 EnergyStatusUnits:5; |
| 3465 | UINT32 Reserved2:3; |
| 3466 | /// |
| 3467 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL |
| 3468 | /// Interfaces.". |
| 3469 | /// |
| 3470 | UINT32 TimeUnits:4; |
| 3471 | UINT32 Reserved3:12; |
| 3472 | UINT32 Reserved4:32; |
| 3473 | } Bits; |
| 3474 | /// |
| 3475 | /// All bit fields as a 32-bit value |
| 3476 | /// |
| 3477 | UINT32 Uint32; |
| 3478 | /// |
| 3479 | /// All bit fields as a 64-bit value |
| 3480 | /// |
| 3481 | UINT64 Uint64; |
| 3482 | } MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER; |
| 3483 | |
| 3484 | |
| 3485 | /** |
| 3486 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL |
| 3487 | Domain.". |
| 3488 | |
| 3489 | @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618) |
| 3490 | @param EAX Lower 32-bits of MSR value. |
| 3491 | @param EDX Upper 32-bits of MSR value. |
| 3492 | |
| 3493 | <b>Example usage</b> |
| 3494 | @code |
| 3495 | UINT64 Msr; |
| 3496 | |
| 3497 | Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT); |
| 3498 | AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr); |
| 3499 | @endcode |
| 3500 | **/ |
| 3501 | #define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618 |
| 3502 | |
| 3503 | |
| 3504 | /** |
| 3505 | Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices. |
| 3506 | |
| 3507 | @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619) |
| 3508 | @param EAX Lower 32-bits of MSR value. |
| 3509 | Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER. |
| 3510 | @param EDX Upper 32-bits of MSR value. |
| 3511 | Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER. |
| 3512 | |
| 3513 | <b>Example usage</b> |
| 3514 | @code |
| 3515 | MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr; |
| 3516 | |
| 3517 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS); |
| 3518 | @endcode |
| 3519 | **/ |
| 3520 | #define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619 |
| 3521 | |
| 3522 | /** |
| 3523 | MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS |
| 3524 | **/ |
| 3525 | typedef union { |
| 3526 | /// |
| 3527 | /// Individual bit fields |
| 3528 | /// |
| 3529 | struct { |
| 3530 | /// |
| 3531 | /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration |
| 3532 | /// to enable DRAM RAPL mode 0 (Direct VR). |
| 3533 | /// |
| 3534 | UINT32 Energy:32; |
| 3535 | UINT32 Reserved:32; |
| 3536 | } Bits; |
| 3537 | /// |
| 3538 | /// All bit fields as a 32-bit value |
| 3539 | /// |
| 3540 | UINT32 Uint32; |
| 3541 | /// |
| 3542 | /// All bit fields as a 64-bit value |
| 3543 | /// |
| 3544 | UINT64 Uint64; |
| 3545 | } MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER; |
| 3546 | |
| 3547 | |
| 3548 | /** |
| 3549 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM |
| 3550 | RAPL Domain.". |
| 3551 | |
| 3552 | @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B) |
| 3553 | @param EAX Lower 32-bits of MSR value. |
| 3554 | @param EDX Upper 32-bits of MSR value. |
| 3555 | |
| 3556 | <b>Example usage</b> |
| 3557 | @code |
| 3558 | UINT64 Msr; |
| 3559 | |
| 3560 | Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS); |
| 3561 | @endcode |
| 3562 | **/ |
| 3563 | #define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B |
| 3564 | |
| 3565 | |
| 3566 | /** |
| 3567 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". |
| 3568 | |
| 3569 | @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C) |
| 3570 | @param EAX Lower 32-bits of MSR value. |
| 3571 | @param EDX Upper 32-bits of MSR value. |
| 3572 | |
| 3573 | <b>Example usage</b> |
| 3574 | @code |
| 3575 | UINT64 Msr; |
| 3576 | |
| 3577 | Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO); |
| 3578 | AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr); |
| 3579 | @endcode |
| 3580 | **/ |
| 3581 | #define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C |
| 3582 | |
| 3583 | |
| 3584 | /** |
| 3585 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio |
| 3586 | fields represent the widest possible range of uncore frequencies. Writing to |
| 3587 | these fields allows software to control the minimum and the maximum |
| 3588 | frequency that hardware will select. |
| 3589 | |
| 3590 | @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620) |
| 3591 | @param EAX Lower 32-bits of MSR value. |
| 3592 | Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER. |
| 3593 | @param EDX Upper 32-bits of MSR value. |
| 3594 | Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER. |
| 3595 | |
| 3596 | <b>Example usage</b> |
| 3597 | @code |
| 3598 | MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; |
| 3599 | |
| 3600 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT); |
| 3601 | AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); |
| 3602 | @endcode |
| 3603 | **/ |
| 3604 | #define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620 |
| 3605 | |
| 3606 | /** |
| 3607 | MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT |
| 3608 | **/ |
| 3609 | typedef union { |
| 3610 | /// |
| 3611 | /// Individual bit fields |
| 3612 | /// |
| 3613 | struct { |
| 3614 | /// |
| 3615 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the |
| 3616 | /// LLC/Ring. |
| 3617 | /// |
| 3618 | UINT32 MAX_RATIO:7; |
| 3619 | UINT32 Reserved1:1; |
| 3620 | /// |
| 3621 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum |
| 3622 | /// possible ratio of the LLC/Ring. |
| 3623 | /// |
| 3624 | UINT32 MIN_RATIO:7; |
| 3625 | UINT32 Reserved2:17; |
| 3626 | UINT32 Reserved3:32; |
| 3627 | } Bits; |
| 3628 | /// |
| 3629 | /// All bit fields as a 32-bit value |
| 3630 | /// |
| 3631 | UINT32 Uint32; |
| 3632 | /// |
| 3633 | /// All bit fields as a 64-bit value |
| 3634 | /// |
| 3635 | UINT64 Uint64; |
| 3636 | } MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER; |
| 3637 | |
| 3638 | |
| 3639 | /** |
| 3640 | Package. Reserved (R/O) Reads return 0. |
| 3641 | |
| 3642 | @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) |
| 3643 | @param EAX Lower 32-bits of MSR value. |
| 3644 | @param EDX Upper 32-bits of MSR value. |
| 3645 | |
| 3646 | <b>Example usage</b> |
| 3647 | @code |
| 3648 | UINT64 Msr; |
| 3649 | |
| 3650 | Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS); |
| 3651 | @endcode |
| 3652 | **/ |
| 3653 | #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639 |
| 3654 | |
| 3655 | |
| 3656 | /** |
| 3657 | THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H, |
| 3658 | ECX=0):EBX.RDT-M[bit 12] = 1. |
| 3659 | |
| 3660 | @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D) |
| 3661 | @param EAX Lower 32-bits of MSR value. |
| 3662 | Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER. |
| 3663 | @param EDX Upper 32-bits of MSR value. |
| 3664 | Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER. |
| 3665 | |
| 3666 | <b>Example usage</b> |
| 3667 | @code |
| 3668 | MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr; |
| 3669 | |
| 3670 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL); |
| 3671 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64); |
| 3672 | @endcode |
| 3673 | **/ |
| 3674 | #define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D |
| 3675 | |
| 3676 | /** |
| 3677 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL |
| 3678 | **/ |
| 3679 | typedef union { |
| 3680 | /// |
| 3681 | /// Individual bit fields |
| 3682 | /// |
| 3683 | struct { |
| 3684 | /// |
| 3685 | /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3 |
| 3686 | /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03: |
| 3687 | /// Local memory bandwidth monitoring. All other encoding reserved. |
| 3688 | /// |
| 3689 | UINT32 EventID:8; |
| 3690 | UINT32 Reserved1:24; |
| 3691 | /// |
| 3692 | /// [Bits 41:32] RMID (RW). |
| 3693 | /// |
| 3694 | UINT32 RMID:10; |
| 3695 | UINT32 Reserved2:22; |
| 3696 | } Bits; |
| 3697 | /// |
| 3698 | /// All bit fields as a 64-bit value |
| 3699 | /// |
| 3700 | UINT64 Uint64; |
| 3701 | } MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER; |
| 3702 | |
| 3703 | |
| 3704 | /** |
| 3705 | THREAD. Resource Association Register (R/W). |
| 3706 | |
| 3707 | @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F) |
| 3708 | @param EAX Lower 32-bits of MSR value. |
| 3709 | Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER. |
| 3710 | @param EDX Upper 32-bits of MSR value. |
| 3711 | Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER. |
| 3712 | |
| 3713 | <b>Example usage</b> |
| 3714 | @code |
| 3715 | MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr; |
| 3716 | |
| 3717 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC); |
| 3718 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64); |
| 3719 | @endcode |
| 3720 | **/ |
| 3721 | #define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F |
| 3722 | |
| 3723 | /** |
| 3724 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC |
| 3725 | **/ |
| 3726 | typedef union { |
| 3727 | /// |
| 3728 | /// Individual bit fields |
| 3729 | /// |
| 3730 | struct { |
| 3731 | /// |
| 3732 | /// [Bits 9:0] RMID. |
| 3733 | /// |
| 3734 | UINT32 RMID:10; |
| 3735 | UINT32 Reserved1:22; |
| 3736 | /// |
| 3737 | /// [Bits 51:32] COS (R/W). |
| 3738 | /// |
| 3739 | UINT32 COS:20; |
| 3740 | UINT32 Reserved2:12; |
| 3741 | } Bits; |
| 3742 | /// |
| 3743 | /// All bit fields as a 64-bit value |
| 3744 | /// |
| 3745 | UINT64 Uint64; |
| 3746 | } MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER; |
| 3747 | |
| 3748 | |
| 3749 | /** |
| 3750 | Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H, |
| 3751 | ECX=1):EDX.COS_MAX[15:0] >=0. |
| 3752 | |
| 3753 | @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N |
| 3754 | @param EAX Lower 32-bits of MSR value. |
| 3755 | Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER. |
| 3756 | @param EDX Upper 32-bits of MSR value. |
| 3757 | Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER. |
| 3758 | |
| 3759 | <b>Example usage</b> |
| 3760 | @code |
| 3761 | MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr; |
| 3762 | |
| 3763 | Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N); |
| 3764 | AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64); |
| 3765 | @endcode |
| 3766 | **/ |
| 3767 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90 |
| 3768 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91 |
| 3769 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92 |
| 3770 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93 |
| 3771 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94 |
| 3772 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95 |
| 3773 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96 |
| 3774 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97 |
| 3775 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98 |
| 3776 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99 |
| 3777 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A |
| 3778 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B |
| 3779 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C |
| 3780 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D |
| 3781 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E |
| 3782 | #define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F |
| 3783 | |
| 3784 | /** |
| 3785 | MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N |
| 3786 | **/ |
| 3787 | typedef union { |
| 3788 | /// |
| 3789 | /// Individual bit fields |
| 3790 | /// |
| 3791 | struct { |
| 3792 | /// |
| 3793 | /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement. |
| 3794 | /// |
| 3795 | UINT32 CBM:20; |
| 3796 | UINT32 Reserved2:12; |
| 3797 | UINT32 Reserved3:32; |
| 3798 | } Bits; |
| 3799 | /// |
| 3800 | /// All bit fields as a 32-bit value |
| 3801 | /// |
| 3802 | UINT32 Uint32; |
| 3803 | /// |
| 3804 | /// All bit fields as a 64-bit value |
| 3805 | /// |
| 3806 | UINT64 Uint64; |
| 3807 | } MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER; |
| 3808 | |
| 3809 | |
| 3810 | #endif |