Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | MSR Definitions for Intel processors based on the Silvermont microarchitecture. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __SILVERMONT_MSR_H__ |
| 19 | #define __SILVERMONT_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is Intel processors based on the Silvermont microarchitecture? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x06 && \ |
| 34 | ( \ |
| 35 | DisplayModel == 0x37 || \ |
| 36 | DisplayModel == 0x4A || \ |
| 37 | DisplayModel == 0x4D || \ |
| 38 | DisplayModel == 0x5A || \ |
| 39 | DisplayModel == 0x5D \ |
| 40 | ) \ |
| 41 | ) |
| 42 | |
| 43 | /** |
| 44 | Module. Model Specific Platform ID (R). |
| 45 | |
| 46 | @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017) |
| 47 | @param EAX Lower 32-bits of MSR value. |
| 48 | Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. |
| 49 | @param EDX Upper 32-bits of MSR value. |
| 50 | Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. |
| 51 | |
| 52 | <b>Example usage</b> |
| 53 | @code |
| 54 | MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr; |
| 55 | |
| 56 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID); |
| 57 | @endcode |
| 58 | @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. |
| 59 | **/ |
| 60 | #define MSR_SILVERMONT_PLATFORM_ID 0x00000017 |
| 61 | |
| 62 | /** |
| 63 | MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID |
| 64 | **/ |
| 65 | typedef union { |
| 66 | /// |
| 67 | /// Individual bit fields |
| 68 | /// |
| 69 | struct { |
| 70 | UINT32 Reserved1:8; |
| 71 | /// |
| 72 | /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio. |
| 73 | /// |
| 74 | UINT32 MaximumQualifiedRatio:5; |
| 75 | UINT32 Reserved2:19; |
| 76 | UINT32 Reserved3:18; |
| 77 | /// |
| 78 | /// [Bits 52:50] See Table 2-2. |
| 79 | /// |
| 80 | UINT32 PlatformId:3; |
| 81 | UINT32 Reserved4:11; |
| 82 | } Bits; |
| 83 | /// |
| 84 | /// All bit fields as a 64-bit value |
| 85 | /// |
| 86 | UINT64 Uint64; |
| 87 | } MSR_SILVERMONT_PLATFORM_ID_REGISTER; |
| 88 | |
| 89 | |
| 90 | /** |
| 91 | Module. Processor Hard Power-On Configuration (R/W) Writes ignored. |
| 92 | |
| 93 | @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A) |
| 94 | @param EAX Lower 32-bits of MSR value. |
| 95 | Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. |
| 96 | @param EDX Upper 32-bits of MSR value. |
| 97 | Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. |
| 98 | |
| 99 | <b>Example usage</b> |
| 100 | @code |
| 101 | MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr; |
| 102 | |
| 103 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON); |
| 104 | AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64); |
| 105 | @endcode |
| 106 | @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. |
| 107 | **/ |
| 108 | #define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A |
| 109 | |
| 110 | /** |
| 111 | MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON |
| 112 | **/ |
| 113 | typedef union { |
| 114 | /// |
| 115 | /// Individual bit fields |
| 116 | /// |
| 117 | struct { |
| 118 | UINT32 Reserved1:32; |
| 119 | UINT32 Reserved2:32; |
| 120 | } Bits; |
| 121 | /// |
| 122 | /// All bit fields as a 32-bit value |
| 123 | /// |
| 124 | UINT32 Uint32; |
| 125 | /// |
| 126 | /// All bit fields as a 64-bit value |
| 127 | /// |
| 128 | UINT64 Uint64; |
| 129 | } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER; |
| 130 | |
| 131 | |
| 132 | /** |
| 133 | Core. SMI Counter (R/O). |
| 134 | |
| 135 | @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034) |
| 136 | @param EAX Lower 32-bits of MSR value. |
| 137 | Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. |
| 138 | @param EDX Upper 32-bits of MSR value. |
| 139 | Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. |
| 140 | |
| 141 | <b>Example usage</b> |
| 142 | @code |
| 143 | MSR_SILVERMONT_SMI_COUNT_REGISTER Msr; |
| 144 | |
| 145 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT); |
| 146 | @endcode |
| 147 | @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. |
| 148 | **/ |
| 149 | #define MSR_SILVERMONT_SMI_COUNT 0x00000034 |
| 150 | |
| 151 | /** |
| 152 | MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT |
| 153 | **/ |
| 154 | typedef union { |
| 155 | /// |
| 156 | /// Individual bit fields |
| 157 | /// |
| 158 | struct { |
| 159 | /// |
| 160 | /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last |
| 161 | /// RESET. |
| 162 | /// |
| 163 | UINT32 SMICount:32; |
| 164 | UINT32 Reserved:32; |
| 165 | } Bits; |
| 166 | /// |
| 167 | /// All bit fields as a 32-bit value |
| 168 | /// |
| 169 | UINT32 Uint32; |
| 170 | /// |
| 171 | /// All bit fields as a 64-bit value |
| 172 | /// |
| 173 | UINT64 Uint64; |
| 174 | } MSR_SILVERMONT_SMI_COUNT_REGISTER; |
| 175 | |
| 176 | |
| 177 | /** |
| 178 | Core. Control Features in Intel 64 Processor (R/W). See Table 2-2. |
| 179 | |
| 180 | @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A) |
| 181 | @param EAX Lower 32-bits of MSR value. |
| 182 | Described by the type |
| 183 | MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER. |
| 184 | @param EDX Upper 32-bits of MSR value. |
| 185 | Described by the type |
| 186 | MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER. |
| 187 | |
| 188 | <b>Example usage</b> |
| 189 | @code |
| 190 | MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr; |
| 191 | |
| 192 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL); |
| 193 | AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64); |
| 194 | @endcode |
| 195 | @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. |
| 196 | **/ |
| 197 | #define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A |
| 198 | |
| 199 | /** |
| 200 | MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL |
| 201 | **/ |
| 202 | typedef union { |
| 203 | /// |
| 204 | /// Individual bit fields |
| 205 | /// |
| 206 | struct { |
| 207 | /// |
| 208 | /// [Bit 0] Lock (R/WL). |
| 209 | /// |
| 210 | UINT32 Lock:1; |
| 211 | UINT32 Reserved1:1; |
| 212 | /// |
| 213 | /// [Bit 2] Enable VMX outside SMX operation (R/WL). |
| 214 | /// |
| 215 | UINT32 EnableVmxOutsideSmx:1; |
| 216 | UINT32 Reserved2:29; |
| 217 | UINT32 Reserved3:32; |
| 218 | } Bits; |
| 219 | /// |
| 220 | /// All bit fields as a 32-bit value |
| 221 | /// |
| 222 | UINT32 Uint32; |
| 223 | /// |
| 224 | /// All bit fields as a 64-bit value |
| 225 | /// |
| 226 | UINT64 Uint64; |
| 227 | } MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER; |
| 228 | |
| 229 | |
| 230 | /** |
| 231 | Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch |
| 232 | record registers on the last branch record stack. The From_IP part of the |
| 233 | stack contains pointers to the source instruction. See also: - Last Branch |
| 234 | Record Stack TOS at 1C9H - Section 17.5 and record format in Section |
| 235 | 17.4.8.1. |
| 236 | |
| 237 | @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP |
| 238 | @param EAX Lower 32-bits of MSR value. |
| 239 | @param EDX Upper 32-bits of MSR value. |
| 240 | |
| 241 | <b>Example usage</b> |
| 242 | @code |
| 243 | UINT64 Msr; |
| 244 | |
| 245 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP); |
| 246 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr); |
| 247 | @endcode |
| 248 | @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. |
| 249 | MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. |
| 250 | MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. |
| 251 | MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. |
| 252 | MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. |
| 253 | MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. |
| 254 | MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. |
| 255 | MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. |
| 256 | @{ |
| 257 | **/ |
| 258 | #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040 |
| 259 | #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041 |
| 260 | #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042 |
| 261 | #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043 |
| 262 | #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044 |
| 263 | #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045 |
| 264 | #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046 |
| 265 | #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047 |
| 266 | /// @} |
| 267 | |
| 268 | |
| 269 | /** |
| 270 | Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch |
| 271 | record registers on the last branch record stack. The To_IP part of the |
| 272 | stack contains pointers to the destination instruction. |
| 273 | |
| 274 | @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP |
| 275 | @param EAX Lower 32-bits of MSR value. |
| 276 | @param EDX Upper 32-bits of MSR value. |
| 277 | |
| 278 | <b>Example usage</b> |
| 279 | @code |
| 280 | UINT64 Msr; |
| 281 | |
| 282 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP); |
| 283 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr); |
| 284 | @endcode |
| 285 | @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. |
| 286 | MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. |
| 287 | MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. |
| 288 | MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. |
| 289 | MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. |
| 290 | MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. |
| 291 | MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. |
| 292 | MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. |
| 293 | @{ |
| 294 | **/ |
| 295 | #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060 |
| 296 | #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061 |
| 297 | #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062 |
| 298 | #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063 |
| 299 | #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064 |
| 300 | #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065 |
| 301 | #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066 |
| 302 | #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067 |
| 303 | /// @} |
| 304 | |
| 305 | |
| 306 | /** |
| 307 | Module. Scalable Bus Speed(RO) This field indicates the intended scalable |
| 308 | bus clock speed for processors based on Silvermont microarchitecture:. |
| 309 | |
| 310 | @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD) |
| 311 | @param EAX Lower 32-bits of MSR value. |
| 312 | Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. |
| 313 | @param EDX Upper 32-bits of MSR value. |
| 314 | Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. |
| 315 | |
| 316 | <b>Example usage</b> |
| 317 | @code |
| 318 | MSR_SILVERMONT_FSB_FREQ_REGISTER Msr; |
| 319 | |
| 320 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ); |
| 321 | @endcode |
| 322 | @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM. |
| 323 | **/ |
| 324 | #define MSR_SILVERMONT_FSB_FREQ 0x000000CD |
| 325 | |
| 326 | /** |
| 327 | MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ |
| 328 | **/ |
| 329 | typedef union { |
| 330 | /// |
| 331 | /// Individual bit fields |
| 332 | /// |
| 333 | struct { |
| 334 | /// |
| 335 | /// [Bits 3:0] Scalable Bus Speed |
| 336 | /// |
| 337 | /// Silvermont Processor Family |
| 338 | /// --------------------------- |
| 339 | /// 100B: 080.0 MHz |
| 340 | /// 000B: 083.3 MHz |
| 341 | /// 001B: 100.0 MHz |
| 342 | /// 010B: 133.3 MHz |
| 343 | /// 011B: 116.7 MHz |
| 344 | /// |
| 345 | /// Airmont Processor Family |
| 346 | /// --------------------------- |
| 347 | /// 0000B: 083.3 MHz |
| 348 | /// 0001B: 100.0 MHz |
| 349 | /// 0010B: 133.3 MHz |
| 350 | /// 0011B: 116.7 MHz |
| 351 | /// 0100B: 080.0 MHz |
| 352 | /// 0101B: 093.3 MHz |
| 353 | /// 0110B: 090.0 MHz |
| 354 | /// 0111B: 088.9 MHz |
| 355 | /// 1000B: 087.5 MHz |
| 356 | /// |
| 357 | UINT32 ScalableBusSpeed:4; |
| 358 | UINT32 Reserved1:28; |
| 359 | UINT32 Reserved2:32; |
| 360 | } Bits; |
| 361 | /// |
| 362 | /// All bit fields as a 32-bit value |
| 363 | /// |
| 364 | UINT32 Uint32; |
| 365 | /// |
| 366 | /// All bit fields as a 64-bit value |
| 367 | /// |
| 368 | UINT64 Uint64; |
| 369 | } MSR_SILVERMONT_FSB_FREQ_REGISTER; |
| 370 | |
| 371 | |
| 372 | /** |
| 373 | Package. Platform Information: Contains power management and other model |
| 374 | specific features enumeration. See http://biosbits.org. |
| 375 | |
| 376 | @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE) |
| 377 | @param EAX Lower 32-bits of MSR value. |
| 378 | Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER. |
| 379 | @param EDX Upper 32-bits of MSR value. |
| 380 | Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER. |
| 381 | |
| 382 | <b>Example usage</b> |
| 383 | @code |
| 384 | MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr; |
| 385 | |
| 386 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO); |
| 387 | AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64); |
| 388 | @endcode |
| 389 | **/ |
| 390 | #define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE |
| 391 | |
| 392 | /** |
| 393 | MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO |
| 394 | **/ |
| 395 | typedef union { |
| 396 | /// |
| 397 | /// Individual bit fields |
| 398 | /// |
| 399 | struct { |
| 400 | UINT32 Reserved1:8; |
| 401 | /// |
| 402 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio |
| 403 | /// of the maximum frequency that does not require turbo. Frequency = |
| 404 | /// ratio * Scalable Bus Frequency. |
| 405 | /// |
| 406 | UINT32 MaximumNon_TurboRatio:8; |
| 407 | UINT32 Reserved2:16; |
| 408 | UINT32 Reserved3:32; |
| 409 | } Bits; |
| 410 | /// |
| 411 | /// All bit fields as a 32-bit value |
| 412 | /// |
| 413 | UINT32 Uint32; |
| 414 | /// |
| 415 | /// All bit fields as a 64-bit value |
| 416 | /// |
| 417 | UINT64 Uint64; |
| 418 | } MSR_SILVERMONT_PLATFORM_INFO_REGISTER; |
| 419 | |
| 420 | /** |
| 421 | Module. C-State Configuration Control (R/W) Note: C-state values are |
| 422 | processor specific C-state code names, unrelated to MWAIT extension C-state |
| 423 | parameters or ACPI CStates. See http://biosbits.org. |
| 424 | |
| 425 | @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2) |
| 426 | @param EAX Lower 32-bits of MSR value. |
| 427 | Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 428 | @param EDX Upper 32-bits of MSR value. |
| 429 | Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 430 | |
| 431 | <b>Example usage</b> |
| 432 | @code |
| 433 | MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr; |
| 434 | |
| 435 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL); |
| 436 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64); |
| 437 | @endcode |
| 438 | @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. |
| 439 | **/ |
| 440 | #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2 |
| 441 | |
| 442 | /** |
| 443 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL |
| 444 | **/ |
| 445 | typedef union { |
| 446 | /// |
| 447 | /// Individual bit fields |
| 448 | /// |
| 449 | struct { |
| 450 | /// |
| 451 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest |
| 452 | /// processor-specific C-state code name (consuming the least power). for |
| 453 | /// the package. The default is set as factory-configured package C-state |
| 454 | /// limit. The following C-state code name encodings are supported: 000b: |
| 455 | /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) |
| 456 | /// 100b: C4 110b: C6 111b: C7 (Silvermont only). |
| 457 | /// |
| 458 | UINT32 Limit:3; |
| 459 | UINT32 Reserved1:7; |
| 460 | /// |
| 461 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map |
| 462 | /// IO_read instructions sent to IO register specified by |
| 463 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. |
| 464 | /// |
| 465 | UINT32 IO_MWAIT:1; |
| 466 | UINT32 Reserved2:4; |
| 467 | /// |
| 468 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register |
| 469 | /// until next reset. |
| 470 | /// |
| 471 | UINT32 CFGLock:1; |
| 472 | UINT32 Reserved3:16; |
| 473 | UINT32 Reserved4:32; |
| 474 | } Bits; |
| 475 | /// |
| 476 | /// All bit fields as a 32-bit value |
| 477 | /// |
| 478 | UINT32 Uint32; |
| 479 | /// |
| 480 | /// All bit fields as a 64-bit value |
| 481 | /// |
| 482 | UINT64 Uint64; |
| 483 | } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER; |
| 484 | |
| 485 | |
| 486 | /** |
| 487 | Module. Power Management IO Redirection in C-state (R/W) See |
| 488 | http://biosbits.org. |
| 489 | |
| 490 | @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4) |
| 491 | @param EAX Lower 32-bits of MSR value. |
| 492 | Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER. |
| 493 | @param EDX Upper 32-bits of MSR value. |
| 494 | Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER. |
| 495 | |
| 496 | <b>Example usage</b> |
| 497 | @code |
| 498 | MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr; |
| 499 | |
| 500 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE); |
| 501 | AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64); |
| 502 | @endcode |
| 503 | @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. |
| 504 | **/ |
| 505 | #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4 |
| 506 | |
| 507 | /** |
| 508 | MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE |
| 509 | **/ |
| 510 | typedef union { |
| 511 | /// |
| 512 | /// Individual bit fields |
| 513 | /// |
| 514 | struct { |
| 515 | /// |
| 516 | /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address |
| 517 | /// visible to software for IO redirection. If IO MWAIT Redirection is |
| 518 | /// enabled, reads to this address will be consumed by the power |
| 519 | /// management logic and decoded to MWAIT instructions. When IO port |
| 520 | /// address redirection is enabled, this is the IO port address reported |
| 521 | /// to the OS/software. |
| 522 | /// |
| 523 | UINT32 Lvl2Base:16; |
| 524 | /// |
| 525 | /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the |
| 526 | /// maximum C-State code name to be included when IO read to MWAIT |
| 527 | /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 |
| 528 | /// is the max C-State to include 110b - C6 is the max C-State to include |
| 529 | /// 111b - C7 is the max C-State to include. |
| 530 | /// |
| 531 | UINT32 CStateRange:3; |
| 532 | UINT32 Reserved1:13; |
| 533 | UINT32 Reserved2:32; |
| 534 | } Bits; |
| 535 | /// |
| 536 | /// All bit fields as a 32-bit value |
| 537 | /// |
| 538 | UINT32 Uint32; |
| 539 | /// |
| 540 | /// All bit fields as a 64-bit value |
| 541 | /// |
| 542 | UINT64 Uint64; |
| 543 | } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER; |
| 544 | |
| 545 | |
| 546 | /** |
| 547 | Module. |
| 548 | |
| 549 | @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E) |
| 550 | @param EAX Lower 32-bits of MSR value. |
| 551 | Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER. |
| 552 | @param EDX Upper 32-bits of MSR value. |
| 553 | Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER. |
| 554 | |
| 555 | <b>Example usage</b> |
| 556 | @code |
| 557 | MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr; |
| 558 | |
| 559 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3); |
| 560 | AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64); |
| 561 | @endcode |
| 562 | @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. |
| 563 | **/ |
| 564 | #define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E |
| 565 | |
| 566 | /** |
| 567 | MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3 |
| 568 | **/ |
| 569 | typedef union { |
| 570 | /// |
| 571 | /// Individual bit fields |
| 572 | /// |
| 573 | struct { |
| 574 | /// |
| 575 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = |
| 576 | /// Indicates if the L2 is hardware-disabled. |
| 577 | /// |
| 578 | UINT32 L2HardwareEnabled:1; |
| 579 | UINT32 Reserved1:7; |
| 580 | /// |
| 581 | /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 = |
| 582 | /// Disabled (default) Until this bit is set the processor will not |
| 583 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input. |
| 584 | /// |
| 585 | UINT32 L2Enabled:1; |
| 586 | UINT32 Reserved2:14; |
| 587 | /// |
| 588 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. |
| 589 | /// |
| 590 | UINT32 L2NotPresent:1; |
| 591 | UINT32 Reserved3:8; |
| 592 | UINT32 Reserved4:32; |
| 593 | } Bits; |
| 594 | /// |
| 595 | /// All bit fields as a 32-bit value |
| 596 | /// |
| 597 | UINT32 Uint32; |
| 598 | /// |
| 599 | /// All bit fields as a 64-bit value |
| 600 | /// |
| 601 | UINT64 Uint64; |
| 602 | } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER; |
| 603 | |
| 604 | |
| 605 | /** |
| 606 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP |
| 607 | handler to handle unsuccessful read of this MSR. |
| 608 | |
| 609 | @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C) |
| 610 | @param EAX Lower 32-bits of MSR value. |
| 611 | Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER. |
| 612 | @param EDX Upper 32-bits of MSR value. |
| 613 | Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER. |
| 614 | |
| 615 | <b>Example usage</b> |
| 616 | @code |
| 617 | MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr; |
| 618 | |
| 619 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG); |
| 620 | AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64); |
| 621 | @endcode |
| 622 | @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. |
| 623 | **/ |
| 624 | #define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C |
| 625 | |
| 626 | /** |
| 627 | MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG |
| 628 | **/ |
| 629 | typedef union { |
| 630 | /// |
| 631 | /// Individual bit fields |
| 632 | /// |
| 633 | struct { |
| 634 | /// |
| 635 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this |
| 636 | /// MSR, the configuration of AES instruction set availability is as |
| 637 | /// follows: 11b: AES instructions are not available until next RESET. |
| 638 | /// otherwise, AES instructions are available. Note, AES instruction set |
| 639 | /// is not available if read is unsuccessful. If the configuration is not |
| 640 | /// 01b, AES instruction can be mis-configured if a privileged agent |
| 641 | /// unintentionally writes 11b. |
| 642 | /// |
| 643 | UINT32 AESConfiguration:2; |
| 644 | UINT32 Reserved1:30; |
| 645 | UINT32 Reserved2:32; |
| 646 | } Bits; |
| 647 | /// |
| 648 | /// All bit fields as a 32-bit value |
| 649 | /// |
| 650 | UINT32 Uint32; |
| 651 | /// |
| 652 | /// All bit fields as a 64-bit value |
| 653 | /// |
| 654 | UINT64 Uint64; |
| 655 | } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER; |
| 656 | |
| 657 | |
| 658 | /** |
| 659 | Enable Misc. Processor Features (R/W) Allows a variety of processor |
| 660 | functions to be enabled and disabled. |
| 661 | |
| 662 | @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0) |
| 663 | @param EAX Lower 32-bits of MSR value. |
| 664 | Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER. |
| 665 | @param EDX Upper 32-bits of MSR value. |
| 666 | Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER. |
| 667 | |
| 668 | <b>Example usage</b> |
| 669 | @code |
| 670 | MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr; |
| 671 | |
| 672 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE); |
| 673 | AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64); |
| 674 | @endcode |
| 675 | @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. |
| 676 | **/ |
| 677 | #define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0 |
| 678 | |
| 679 | /** |
| 680 | MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE |
| 681 | **/ |
| 682 | typedef union { |
| 683 | /// |
| 684 | /// Individual bit fields |
| 685 | /// |
| 686 | struct { |
| 687 | /// |
| 688 | /// [Bit 0] Core. Fast-Strings Enable See Table 2-2. |
| 689 | /// |
| 690 | UINT32 FastStrings:1; |
| 691 | UINT32 Reserved1:2; |
| 692 | /// |
| 693 | /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See |
| 694 | /// Table 2-2. Default value is 0. |
| 695 | /// |
| 696 | UINT32 AutomaticThermalControlCircuit:1; |
| 697 | UINT32 Reserved2:3; |
| 698 | /// |
| 699 | /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2. |
| 700 | /// |
| 701 | UINT32 PerformanceMonitoring:1; |
| 702 | UINT32 Reserved3:3; |
| 703 | /// |
| 704 | /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2. |
| 705 | /// |
| 706 | UINT32 BTS:1; |
| 707 | /// |
| 708 | /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See |
| 709 | /// Table 2-2. |
| 710 | /// |
| 711 | UINT32 PEBS:1; |
| 712 | UINT32 Reserved4:3; |
| 713 | /// |
| 714 | /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See |
| 715 | /// Table 2-2. |
| 716 | /// |
| 717 | UINT32 EIST:1; |
| 718 | UINT32 Reserved5:1; |
| 719 | /// |
| 720 | /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2. |
| 721 | /// |
| 722 | UINT32 MONITOR:1; |
| 723 | UINT32 Reserved6:3; |
| 724 | /// |
| 725 | /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2. |
| 726 | /// |
| 727 | UINT32 LimitCpuidMaxval:1; |
| 728 | /// |
| 729 | /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2. |
| 730 | /// |
| 731 | UINT32 xTPR_Message_Disable:1; |
| 732 | UINT32 Reserved7:8; |
| 733 | UINT32 Reserved8:2; |
| 734 | /// |
| 735 | /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2. |
| 736 | /// |
| 737 | UINT32 XD:1; |
| 738 | UINT32 Reserved9:3; |
| 739 | /// |
| 740 | /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors |
| 741 | /// that support Intel Turbo Boost Technology, the turbo mode feature is |
| 742 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: |
| 743 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: |
| 744 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note: |
| 745 | /// the power-on default value is used by BIOS to detect hardware support |
| 746 | /// of turbo mode. If power-on default value is 1, turbo mode is available |
| 747 | /// in the processor. If power-on default value is 0, turbo mode is not |
| 748 | /// available. |
| 749 | /// |
| 750 | UINT32 TurboModeDisable:1; |
| 751 | UINT32 Reserved10:25; |
| 752 | } Bits; |
| 753 | /// |
| 754 | /// All bit fields as a 64-bit value |
| 755 | /// |
| 756 | UINT64 Uint64; |
| 757 | } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER; |
| 758 | |
| 759 | |
| 760 | /** |
| 761 | Package. |
| 762 | |
| 763 | @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2) |
| 764 | @param EAX Lower 32-bits of MSR value. |
| 765 | Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER. |
| 766 | @param EDX Upper 32-bits of MSR value. |
| 767 | Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER. |
| 768 | |
| 769 | <b>Example usage</b> |
| 770 | @code |
| 771 | MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr; |
| 772 | |
| 773 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET); |
| 774 | AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64); |
| 775 | @endcode |
| 776 | @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. |
| 777 | **/ |
| 778 | #define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2 |
| 779 | |
| 780 | /** |
| 781 | MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET |
| 782 | **/ |
| 783 | typedef union { |
| 784 | /// |
| 785 | /// Individual bit fields |
| 786 | /// |
| 787 | struct { |
| 788 | UINT32 Reserved1:16; |
| 789 | /// |
| 790 | /// [Bits 23:16] Temperature Target (R) The default thermal throttling or |
| 791 | /// PROCHOT# activation temperature in degree C, The effective temperature |
| 792 | /// for thermal throttling or PROCHOT# activation is "Temperature Target" |
| 793 | /// + "Target Offset". |
| 794 | /// |
| 795 | UINT32 TemperatureTarget:8; |
| 796 | /// |
| 797 | /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to |
| 798 | /// adjust the throttling and PROCHOT# activation temperature from the |
| 799 | /// default target specified in TEMPERATURE_TARGET (bits 23:16). |
| 800 | /// |
| 801 | UINT32 TargetOffset:6; |
| 802 | UINT32 Reserved2:2; |
| 803 | UINT32 Reserved3:32; |
| 804 | } Bits; |
| 805 | /// |
| 806 | /// All bit fields as a 32-bit value |
| 807 | /// |
| 808 | UINT32 Uint32; |
| 809 | /// |
| 810 | /// All bit fields as a 64-bit value |
| 811 | /// |
| 812 | UINT64 Uint64; |
| 813 | } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER; |
| 814 | |
| 815 | |
| 816 | /** |
| 817 | Miscellaneous Feature Control (R/W). |
| 818 | |
| 819 | @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4) |
| 820 | @param EAX Lower 32-bits of MSR value. |
| 821 | Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER. |
| 822 | @param EDX Upper 32-bits of MSR value. |
| 823 | Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER. |
| 824 | |
| 825 | <b>Example usage</b> |
| 826 | @code |
| 827 | MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr; |
| 828 | |
| 829 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL); |
| 830 | AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64); |
| 831 | @endcode |
| 832 | @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. |
| 833 | **/ |
| 834 | #define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4 |
| 835 | |
| 836 | /** |
| 837 | MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL |
| 838 | **/ |
| 839 | typedef union { |
| 840 | /// |
| 841 | /// Individual bit fields |
| 842 | /// |
| 843 | struct { |
| 844 | /// |
| 845 | /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the |
| 846 | /// L2 hardware prefetcher, which fetches additional lines of code or data |
| 847 | /// into the L2 cache. |
| 848 | /// |
| 849 | UINT32 L2HardwarePrefetcherDisable:1; |
| 850 | UINT32 Reserved1:1; |
| 851 | /// |
| 852 | /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables |
| 853 | /// the L1 data cache prefetcher, which fetches the next cache line into |
| 854 | /// L1 data cache. |
| 855 | /// |
| 856 | UINT32 DCUHardwarePrefetcherDisable:1; |
| 857 | UINT32 Reserved2:29; |
| 858 | UINT32 Reserved3:32; |
| 859 | } Bits; |
| 860 | /// |
| 861 | /// All bit fields as a 32-bit value |
| 862 | /// |
| 863 | UINT32 Uint32; |
| 864 | /// |
| 865 | /// All bit fields as a 64-bit value |
| 866 | /// |
| 867 | UINT64 Uint64; |
| 868 | } MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER; |
| 869 | |
| 870 | |
| 871 | /** |
| 872 | Module. Offcore Response Event Select Register (R/W). |
| 873 | |
| 874 | @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6) |
| 875 | @param EAX Lower 32-bits of MSR value. |
| 876 | @param EDX Upper 32-bits of MSR value. |
| 877 | |
| 878 | <b>Example usage</b> |
| 879 | @code |
| 880 | UINT64 Msr; |
| 881 | |
| 882 | Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0); |
| 883 | AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr); |
| 884 | @endcode |
| 885 | @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. |
| 886 | **/ |
| 887 | #define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6 |
| 888 | |
| 889 | |
| 890 | /** |
| 891 | Module. Offcore Response Event Select Register (R/W). |
| 892 | |
| 893 | @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7) |
| 894 | @param EAX Lower 32-bits of MSR value. |
| 895 | @param EDX Upper 32-bits of MSR value. |
| 896 | |
| 897 | <b>Example usage</b> |
| 898 | @code |
| 899 | UINT64 Msr; |
| 900 | |
| 901 | Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1); |
| 902 | AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr); |
| 903 | @endcode |
| 904 | @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. |
| 905 | **/ |
| 906 | #define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7 |
| 907 | |
| 908 | |
| 909 | /** |
| 910 | Package. Maximum Ratio Limit of Turbo Mode (RW). |
| 911 | |
| 912 | @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD) |
| 913 | @param EAX Lower 32-bits of MSR value. |
| 914 | Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER. |
| 915 | @param EDX Upper 32-bits of MSR value. |
| 916 | Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER. |
| 917 | |
| 918 | <b>Example usage</b> |
| 919 | @code |
| 920 | MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr; |
| 921 | |
| 922 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT); |
| 923 | AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64); |
| 924 | @endcode |
| 925 | @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. |
| 926 | **/ |
| 927 | #define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD |
| 928 | |
| 929 | /** |
| 930 | MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT |
| 931 | **/ |
| 932 | typedef union { |
| 933 | /// |
| 934 | /// Individual bit fields |
| 935 | /// |
| 936 | struct { |
| 937 | /// |
| 938 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio |
| 939 | /// limit of 1 core active. |
| 940 | /// |
| 941 | UINT32 Maximum1C:8; |
| 942 | /// |
| 943 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio |
| 944 | /// limit of 2 core active. |
| 945 | /// |
| 946 | UINT32 Maximum2C:8; |
| 947 | /// |
| 948 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio |
| 949 | /// limit of 3 core active. |
| 950 | /// |
| 951 | UINT32 Maximum3C:8; |
| 952 | /// |
| 953 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio |
| 954 | /// limit of 4 core active. |
| 955 | /// |
| 956 | UINT32 Maximum4C:8; |
| 957 | /// |
| 958 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio |
| 959 | /// limit of 5 core active. |
| 960 | /// |
| 961 | UINT32 Maximum5C:8; |
| 962 | /// |
| 963 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio |
| 964 | /// limit of 6 core active. |
| 965 | /// |
| 966 | UINT32 Maximum6C:8; |
| 967 | /// |
| 968 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio |
| 969 | /// limit of 7 core active. |
| 970 | /// |
| 971 | UINT32 Maximum7C:8; |
| 972 | /// |
| 973 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio |
| 974 | /// limit of 8 core active. |
| 975 | /// |
| 976 | UINT32 Maximum8C:8; |
| 977 | } Bits; |
| 978 | /// |
| 979 | /// All bit fields as a 64-bit value |
| 980 | /// |
| 981 | UINT64 Uint64; |
| 982 | } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER; |
| 983 | |
| 984 | |
| 985 | /** |
| 986 | Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, |
| 987 | "Filtering of Last Branch Records.". |
| 988 | |
| 989 | @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8) |
| 990 | @param EAX Lower 32-bits of MSR value. |
| 991 | Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER. |
| 992 | @param EDX Upper 32-bits of MSR value. |
| 993 | Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER. |
| 994 | |
| 995 | <b>Example usage</b> |
| 996 | @code |
| 997 | MSR_SILVERMONT_LBR_SELECT_REGISTER Msr; |
| 998 | |
| 999 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT); |
| 1000 | AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64); |
| 1001 | @endcode |
| 1002 | @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. |
| 1003 | **/ |
| 1004 | #define MSR_SILVERMONT_LBR_SELECT 0x000001C8 |
| 1005 | |
| 1006 | /** |
| 1007 | MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT |
| 1008 | **/ |
| 1009 | typedef union { |
| 1010 | /// |
| 1011 | /// Individual bit fields |
| 1012 | /// |
| 1013 | struct { |
| 1014 | /// |
| 1015 | /// [Bit 0] CPL_EQ_0. |
| 1016 | /// |
| 1017 | UINT32 CPL_EQ_0:1; |
| 1018 | /// |
| 1019 | /// [Bit 1] CPL_NEQ_0. |
| 1020 | /// |
| 1021 | UINT32 CPL_NEQ_0:1; |
| 1022 | /// |
| 1023 | /// [Bit 2] JCC. |
| 1024 | /// |
| 1025 | UINT32 JCC:1; |
| 1026 | /// |
| 1027 | /// [Bit 3] NEAR_REL_CALL. |
| 1028 | /// |
| 1029 | UINT32 NEAR_REL_CALL:1; |
| 1030 | /// |
| 1031 | /// [Bit 4] NEAR_IND_CALL. |
| 1032 | /// |
| 1033 | UINT32 NEAR_IND_CALL:1; |
| 1034 | /// |
| 1035 | /// [Bit 5] NEAR_RET. |
| 1036 | /// |
| 1037 | UINT32 NEAR_RET:1; |
| 1038 | /// |
| 1039 | /// [Bit 6] NEAR_IND_JMP. |
| 1040 | /// |
| 1041 | UINT32 NEAR_IND_JMP:1; |
| 1042 | /// |
| 1043 | /// [Bit 7] NEAR_REL_JMP. |
| 1044 | /// |
| 1045 | UINT32 NEAR_REL_JMP:1; |
| 1046 | /// |
| 1047 | /// [Bit 8] FAR_BRANCH. |
| 1048 | /// |
| 1049 | UINT32 FAR_BRANCH:1; |
| 1050 | UINT32 Reserved1:23; |
| 1051 | UINT32 Reserved2:32; |
| 1052 | } Bits; |
| 1053 | /// |
| 1054 | /// All bit fields as a 32-bit value |
| 1055 | /// |
| 1056 | UINT32 Uint32; |
| 1057 | /// |
| 1058 | /// All bit fields as a 64-bit value |
| 1059 | /// |
| 1060 | UINT64 Uint64; |
| 1061 | } MSR_SILVERMONT_LBR_SELECT_REGISTER; |
| 1062 | |
| 1063 | |
| 1064 | /** |
| 1065 | Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that |
| 1066 | points to the MSR containing the most recent branch record. See |
| 1067 | MSR_LASTBRANCH_0_FROM_IP. |
| 1068 | |
| 1069 | @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9) |
| 1070 | @param EAX Lower 32-bits of MSR value. |
| 1071 | @param EDX Upper 32-bits of MSR value. |
| 1072 | |
| 1073 | <b>Example usage</b> |
| 1074 | @code |
| 1075 | UINT64 Msr; |
| 1076 | |
| 1077 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS); |
| 1078 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr); |
| 1079 | @endcode |
| 1080 | @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. |
| 1081 | **/ |
| 1082 | #define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9 |
| 1083 | |
| 1084 | |
| 1085 | /** |
| 1086 | Core. Last Exception Record From Linear IP (R) Contains a pointer to the |
| 1087 | last branch instruction that the processor executed prior to the last |
| 1088 | exception that was generated or the last interrupt that was handled. |
| 1089 | |
| 1090 | @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD) |
| 1091 | @param EAX Lower 32-bits of MSR value. |
| 1092 | @param EDX Upper 32-bits of MSR value. |
| 1093 | |
| 1094 | <b>Example usage</b> |
| 1095 | @code |
| 1096 | UINT64 Msr; |
| 1097 | |
| 1098 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP); |
| 1099 | @endcode |
| 1100 | @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. |
| 1101 | **/ |
| 1102 | #define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD |
| 1103 | |
| 1104 | |
| 1105 | /** |
| 1106 | Core. Last Exception Record To Linear IP (R) This area contains a pointer |
| 1107 | to the target of the last branch instruction that the processor executed |
| 1108 | prior to the last exception that was generated or the last interrupt that |
| 1109 | was handled. |
| 1110 | |
| 1111 | @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE) |
| 1112 | @param EAX Lower 32-bits of MSR value. |
| 1113 | @param EDX Upper 32-bits of MSR value. |
| 1114 | |
| 1115 | <b>Example usage</b> |
| 1116 | @code |
| 1117 | UINT64 Msr; |
| 1118 | |
| 1119 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP); |
| 1120 | @endcode |
| 1121 | @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. |
| 1122 | **/ |
| 1123 | #define MSR_SILVERMONT_LER_TO_LIP 0x000001DE |
| 1124 | |
| 1125 | |
| 1126 | /** |
| 1127 | Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling |
| 1128 | (PEBS).". |
| 1129 | |
| 1130 | @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1) |
| 1131 | @param EAX Lower 32-bits of MSR value. |
| 1132 | Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER. |
| 1133 | @param EDX Upper 32-bits of MSR value. |
| 1134 | Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER. |
| 1135 | |
| 1136 | <b>Example usage</b> |
| 1137 | @code |
| 1138 | MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr; |
| 1139 | |
| 1140 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE); |
| 1141 | AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64); |
| 1142 | @endcode |
| 1143 | @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. |
| 1144 | **/ |
| 1145 | #define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1 |
| 1146 | |
| 1147 | /** |
| 1148 | MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE |
| 1149 | **/ |
| 1150 | typedef union { |
| 1151 | /// |
| 1152 | /// Individual bit fields |
| 1153 | /// |
| 1154 | struct { |
| 1155 | /// |
| 1156 | /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W). |
| 1157 | /// |
| 1158 | UINT32 PEBS:1; |
| 1159 | UINT32 Reserved1:31; |
| 1160 | UINT32 Reserved2:32; |
| 1161 | } Bits; |
| 1162 | /// |
| 1163 | /// All bit fields as a 32-bit value |
| 1164 | /// |
| 1165 | UINT32 Uint32; |
| 1166 | /// |
| 1167 | /// All bit fields as a 64-bit value |
| 1168 | /// |
| 1169 | UINT64 Uint64; |
| 1170 | } MSR_SILVERMONT_PEBS_ENABLE_REGISTER; |
| 1171 | |
| 1172 | |
| 1173 | /** |
| 1174 | Package. Note: C-state values are processor specific C-state code names, |
| 1175 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 |
| 1176 | Residency Counter. (R/O) Value since last reset that this package is in |
| 1177 | processor-specific C6 states. Counts at the TSC Frequency. |
| 1178 | |
| 1179 | @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA) |
| 1180 | @param EAX Lower 32-bits of MSR value. |
| 1181 | @param EDX Upper 32-bits of MSR value. |
| 1182 | |
| 1183 | <b>Example usage</b> |
| 1184 | @code |
| 1185 | UINT64 Msr; |
| 1186 | |
| 1187 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY); |
| 1188 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr); |
| 1189 | @endcode |
| 1190 | @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. |
| 1191 | **/ |
| 1192 | #define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA |
| 1193 | |
| 1194 | |
| 1195 | /** |
| 1196 | Core. Note: C-state values are processor specific C-state code names, |
| 1197 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 |
| 1198 | Residency Counter. (R/O) Value since last reset that this core is in |
| 1199 | processor-specific C6 states. Counts at the TSC Frequency. |
| 1200 | |
| 1201 | @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD) |
| 1202 | @param EAX Lower 32-bits of MSR value. |
| 1203 | @param EDX Upper 32-bits of MSR value. |
| 1204 | |
| 1205 | <b>Example usage</b> |
| 1206 | @code |
| 1207 | UINT64 Msr; |
| 1208 | |
| 1209 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY); |
| 1210 | AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr); |
| 1211 | @endcode |
| 1212 | @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. |
| 1213 | **/ |
| 1214 | #define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD |
| 1215 | |
| 1216 | |
| 1217 | /** |
| 1218 | Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2. |
| 1219 | |
| 1220 | @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C) |
| 1221 | @param EAX Lower 32-bits of MSR value. |
| 1222 | @param EDX Upper 32-bits of MSR value. |
| 1223 | |
| 1224 | <b>Example usage</b> |
| 1225 | @code |
| 1226 | UINT64 Msr; |
| 1227 | |
| 1228 | Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM); |
| 1229 | @endcode |
| 1230 | @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM. |
| 1231 | **/ |
| 1232 | #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C |
| 1233 | |
| 1234 | |
| 1235 | /** |
| 1236 | Core. Capability Reporting Register of VM-Function Controls (R/O) See Table |
| 1237 | 2-2. |
| 1238 | |
| 1239 | @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491) |
| 1240 | @param EAX Lower 32-bits of MSR value. |
| 1241 | @param EDX Upper 32-bits of MSR value. |
| 1242 | |
| 1243 | <b>Example usage</b> |
| 1244 | @code |
| 1245 | UINT64 Msr; |
| 1246 | |
| 1247 | Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC); |
| 1248 | @endcode |
| 1249 | @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM. |
| 1250 | **/ |
| 1251 | #define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491 |
| 1252 | |
| 1253 | |
| 1254 | /** |
| 1255 | Core. Note: C-state values are processor specific C-state code names, |
| 1256 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1 |
| 1257 | Residency Counter. (R/O) Value since last reset that this core is in |
| 1258 | processor-specific C1 states. Counts at the TSC frequency. |
| 1259 | |
| 1260 | @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660) |
| 1261 | @param EAX Lower 32-bits of MSR value. |
| 1262 | @param EDX Upper 32-bits of MSR value. |
| 1263 | |
| 1264 | <b>Example usage</b> |
| 1265 | @code |
| 1266 | UINT64 Msr; |
| 1267 | |
| 1268 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY); |
| 1269 | AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr); |
| 1270 | @endcode |
| 1271 | @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM. |
| 1272 | **/ |
| 1273 | #define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660 |
| 1274 | |
| 1275 | |
| 1276 | /** |
| 1277 | Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, |
| 1278 | "RAPL Interfaces.". |
| 1279 | |
| 1280 | @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606) |
| 1281 | @param EAX Lower 32-bits of MSR value. |
| 1282 | Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER. |
| 1283 | @param EDX Upper 32-bits of MSR value. |
| 1284 | Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER. |
| 1285 | |
| 1286 | <b>Example usage</b> |
| 1287 | @code |
| 1288 | MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr; |
| 1289 | |
| 1290 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT); |
| 1291 | @endcode |
| 1292 | @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. |
| 1293 | **/ |
| 1294 | #define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606 |
| 1295 | |
| 1296 | /** |
| 1297 | MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT |
| 1298 | **/ |
| 1299 | typedef union { |
| 1300 | /// |
| 1301 | /// Individual bit fields |
| 1302 | /// |
| 1303 | struct { |
| 1304 | /// |
| 1305 | /// [Bits 3:0] Power Units. Power related information (in milliWatts) is |
| 1306 | /// based on the multiplier, 2^PU; where PU is an unsigned integer |
| 1307 | /// represented by bits 3:0. Default value is 0101b, indicating power unit |
| 1308 | /// is in 32 milliWatts increment. |
| 1309 | /// |
| 1310 | UINT32 PowerUnits:4; |
| 1311 | UINT32 Reserved1:4; |
| 1312 | /// |
| 1313 | /// [Bits 12:8] Energy Status Units. Energy related information (in |
| 1314 | /// microJoules) is based on the multiplier, 2^ESU; where ESU is an |
| 1315 | /// unsigned integer represented by bits 12:8. Default value is 00101b, |
| 1316 | /// indicating energy unit is in 32 microJoules increment. |
| 1317 | /// |
| 1318 | UINT32 EnergyStatusUnits:5; |
| 1319 | UINT32 Reserved2:3; |
| 1320 | /// |
| 1321 | /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in |
| 1322 | /// one second. |
| 1323 | /// |
| 1324 | UINT32 TimeUnits:4; |
| 1325 | UINT32 Reserved3:12; |
| 1326 | UINT32 Reserved4:32; |
| 1327 | } Bits; |
| 1328 | /// |
| 1329 | /// All bit fields as a 32-bit value |
| 1330 | /// |
| 1331 | UINT32 Uint32; |
| 1332 | /// |
| 1333 | /// All bit fields as a 64-bit value |
| 1334 | /// |
| 1335 | UINT64 Uint64; |
| 1336 | } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER; |
| 1337 | |
| 1338 | |
| 1339 | /** |
| 1340 | Package. PKG RAPL Power Limit Control (R/W). |
| 1341 | |
| 1342 | @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610) |
| 1343 | @param EAX Lower 32-bits of MSR value. |
| 1344 | Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER. |
| 1345 | @param EDX Upper 32-bits of MSR value. |
| 1346 | Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER. |
| 1347 | |
| 1348 | <b>Example usage</b> |
| 1349 | @code |
| 1350 | MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr; |
| 1351 | |
| 1352 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT); |
| 1353 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64); |
| 1354 | @endcode |
| 1355 | @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. |
| 1356 | **/ |
| 1357 | #define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610 |
| 1358 | |
| 1359 | /** |
| 1360 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT |
| 1361 | **/ |
| 1362 | typedef union { |
| 1363 | /// |
| 1364 | /// Individual bit fields |
| 1365 | /// |
| 1366 | struct { |
| 1367 | /// |
| 1368 | /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package |
| 1369 | /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8. |
| 1370 | /// |
| 1371 | UINT32 Limit:15; |
| 1372 | /// |
| 1373 | /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package |
| 1374 | /// RAPL Domain.". |
| 1375 | /// |
| 1376 | UINT32 Enable:1; |
| 1377 | /// |
| 1378 | /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3, |
| 1379 | /// "Package RAPL Domain.". |
| 1380 | /// |
| 1381 | UINT32 ClampingLimit:1; |
| 1382 | /// |
| 1383 | /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second. |
| 1384 | /// If 0 is specified in bits [23:17], defaults to 1 second window. |
| 1385 | /// |
| 1386 | UINT32 Time:7; |
| 1387 | UINT32 Reserved1:8; |
| 1388 | UINT32 Reserved2:32; |
| 1389 | } Bits; |
| 1390 | /// |
| 1391 | /// All bit fields as a 32-bit value |
| 1392 | /// |
| 1393 | UINT32 Uint32; |
| 1394 | /// |
| 1395 | /// All bit fields as a 64-bit value |
| 1396 | /// |
| 1397 | UINT64 Uint64; |
| 1398 | } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER; |
| 1399 | |
| 1400 | |
| 1401 | /** |
| 1402 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain." |
| 1403 | and MSR_RAPL_POWER_UNIT in Table 2-8. |
| 1404 | |
| 1405 | @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611) |
| 1406 | @param EAX Lower 32-bits of MSR value. |
| 1407 | @param EDX Upper 32-bits of MSR value. |
| 1408 | |
| 1409 | <b>Example usage</b> |
| 1410 | @code |
| 1411 | UINT64 Msr; |
| 1412 | |
| 1413 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS); |
| 1414 | @endcode |
| 1415 | @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. |
| 1416 | **/ |
| 1417 | #define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611 |
| 1418 | |
| 1419 | |
| 1420 | /** |
| 1421 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains." |
| 1422 | and MSR_RAPL_POWER_UNIT in Table 2-8. |
| 1423 | |
| 1424 | @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639) |
| 1425 | @param EAX Lower 32-bits of MSR value. |
| 1426 | @param EDX Upper 32-bits of MSR value. |
| 1427 | |
| 1428 | <b>Example usage</b> |
| 1429 | @code |
| 1430 | UINT64 Msr; |
| 1431 | |
| 1432 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS); |
| 1433 | @endcode |
| 1434 | @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. |
| 1435 | **/ |
| 1436 | #define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639 |
| 1437 | |
| 1438 | |
| 1439 | /** |
| 1440 | Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion |
| 1441 | policy. Writing a value of 0 disables core level HW demotion policy. |
| 1442 | |
| 1443 | @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668) |
| 1444 | @param EAX Lower 32-bits of MSR value. |
| 1445 | @param EDX Upper 32-bits of MSR value. |
| 1446 | |
| 1447 | <b>Example usage</b> |
| 1448 | @code |
| 1449 | UINT64 Msr; |
| 1450 | |
| 1451 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG); |
| 1452 | AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr); |
| 1453 | @endcode |
| 1454 | @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM. |
| 1455 | **/ |
| 1456 | #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
| 1457 | |
| 1458 | |
| 1459 | /** |
| 1460 | Package. Module C6 demotion policy config MSR. Controls module (i.e. two |
| 1461 | cores sharing the second-level cache) C6 demotion policy. Writing a value of |
| 1462 | 0 disables module level HW demotion policy. |
| 1463 | |
| 1464 | @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669) |
| 1465 | @param EAX Lower 32-bits of MSR value. |
| 1466 | @param EDX Upper 32-bits of MSR value. |
| 1467 | |
| 1468 | <b>Example usage</b> |
| 1469 | @code |
| 1470 | UINT64 Msr; |
| 1471 | |
| 1472 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG); |
| 1473 | AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr); |
| 1474 | @endcode |
| 1475 | @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM. |
| 1476 | **/ |
| 1477 | #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669 |
| 1478 | |
| 1479 | |
| 1480 | /** |
| 1481 | Module. Module C6 Residency Counter (R/0) Note: C-state values are processor |
| 1482 | specific C-state code names, unrelated to MWAIT extension C-state parameters |
| 1483 | or ACPI CStates. Time that this module is in module-specific C6 states since |
| 1484 | last reset. Counts at 1 Mhz frequency. |
| 1485 | |
| 1486 | @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664) |
| 1487 | @param EAX Lower 32-bits of MSR value. |
| 1488 | @param EDX Upper 32-bits of MSR value. |
| 1489 | |
| 1490 | <b>Example usage</b> |
| 1491 | @code |
| 1492 | UINT64 Msr; |
| 1493 | |
| 1494 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER); |
| 1495 | @endcode |
| 1496 | @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM. |
| 1497 | **/ |
| 1498 | #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664 |
| 1499 | |
| 1500 | |
| 1501 | /** |
| 1502 | Package. PKG RAPL Parameter (R/0). |
| 1503 | |
| 1504 | @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E) |
| 1505 | @param EAX Lower 32-bits of MSR value. |
| 1506 | Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER. |
| 1507 | @param EDX Upper 32-bits of MSR value. |
| 1508 | Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER. |
| 1509 | |
| 1510 | <b>Example usage</b> |
| 1511 | @code |
| 1512 | MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr; |
| 1513 | |
| 1514 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO); |
| 1515 | @endcode |
| 1516 | @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. |
| 1517 | **/ |
| 1518 | #define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E |
| 1519 | |
| 1520 | /** |
| 1521 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO |
| 1522 | **/ |
| 1523 | typedef union { |
| 1524 | /// |
| 1525 | /// Individual bit fields |
| 1526 | /// |
| 1527 | struct { |
| 1528 | /// |
| 1529 | /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is |
| 1530 | /// the equivalent of thermal specification power of the package domain. |
| 1531 | /// The unit of this field is specified by the "Power Units" field of |
| 1532 | /// MSR_RAPL_POWER_UNIT. |
| 1533 | /// |
| 1534 | UINT32 ThermalSpecPower:15; |
| 1535 | UINT32 Reserved1:17; |
| 1536 | UINT32 Reserved2:32; |
| 1537 | } Bits; |
| 1538 | /// |
| 1539 | /// All bit fields as a 32-bit value |
| 1540 | /// |
| 1541 | UINT32 Uint32; |
| 1542 | /// |
| 1543 | /// All bit fields as a 64-bit value |
| 1544 | /// |
| 1545 | UINT64 Uint64; |
| 1546 | } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER; |
| 1547 | |
| 1548 | |
| 1549 | /** |
| 1550 | Package. PP0 RAPL Power Limit Control (R/W). |
| 1551 | |
| 1552 | @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638) |
| 1553 | @param EAX Lower 32-bits of MSR value. |
| 1554 | Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER. |
| 1555 | @param EDX Upper 32-bits of MSR value. |
| 1556 | Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER. |
| 1557 | |
| 1558 | <b>Example usage</b> |
| 1559 | @code |
| 1560 | MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr; |
| 1561 | |
| 1562 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT); |
| 1563 | AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64); |
| 1564 | @endcode |
| 1565 | @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM. |
| 1566 | **/ |
| 1567 | #define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638 |
| 1568 | |
| 1569 | /** |
| 1570 | MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT |
| 1571 | **/ |
| 1572 | typedef union { |
| 1573 | /// |
| 1574 | /// Individual bit fields |
| 1575 | /// |
| 1576 | struct { |
| 1577 | /// |
| 1578 | /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 |
| 1579 | /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8. |
| 1580 | /// |
| 1581 | UINT32 Limit:15; |
| 1582 | /// |
| 1583 | /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 |
| 1584 | /// RAPL Domains.". |
| 1585 | /// |
| 1586 | UINT32 Enable:1; |
| 1587 | UINT32 Reserved1:1; |
| 1588 | /// |
| 1589 | /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time |
| 1590 | /// duration over which the average power must remain below |
| 1591 | /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time |
| 1592 | /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time |
| 1593 | /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration. |
| 1594 | /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35 |
| 1595 | /// second time duration. 0x8: 40 second time duration. 0x9: 45 second |
| 1596 | /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved. |
| 1597 | /// |
| 1598 | UINT32 Time:7; |
| 1599 | UINT32 Reserved2:8; |
| 1600 | UINT32 Reserved3:32; |
| 1601 | } Bits; |
| 1602 | /// |
| 1603 | /// All bit fields as a 32-bit value |
| 1604 | /// |
| 1605 | UINT32 Uint32; |
| 1606 | /// |
| 1607 | /// All bit fields as a 64-bit value |
| 1608 | /// |
| 1609 | UINT64 Uint64; |
| 1610 | } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER; |
| 1611 | |
| 1612 | #endif |