Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __SANDY_BRIDGE_MSR_H__ |
| 19 | #define __SANDY_BRIDGE_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is Intel processors based on the Sandy Bridge microarchitecture? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x06 && \ |
| 34 | ( \ |
| 35 | DisplayModel == 0x2A || \ |
| 36 | DisplayModel == 0x2D \ |
| 37 | ) \ |
| 38 | ) |
| 39 | |
| 40 | /** |
| 41 | Thread. SMI Counter (R/O). |
| 42 | |
| 43 | @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034) |
| 44 | @param EAX Lower 32-bits of MSR value. |
| 45 | Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER. |
| 46 | @param EDX Upper 32-bits of MSR value. |
| 47 | Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER. |
| 48 | |
| 49 | <b>Example usage</b> |
| 50 | @code |
| 51 | MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr; |
| 52 | |
| 53 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT); |
| 54 | @endcode |
| 55 | @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. |
| 56 | **/ |
| 57 | #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034 |
| 58 | |
| 59 | /** |
| 60 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT |
| 61 | **/ |
| 62 | typedef union { |
| 63 | /// |
| 64 | /// Individual bit fields |
| 65 | /// |
| 66 | struct { |
| 67 | /// |
| 68 | /// [Bits 31:0] SMI Count (R/O) Count SMIs. |
| 69 | /// |
| 70 | UINT32 SMICount:32; |
| 71 | UINT32 Reserved:32; |
| 72 | } Bits; |
| 73 | /// |
| 74 | /// All bit fields as a 32-bit value |
| 75 | /// |
| 76 | UINT32 Uint32; |
| 77 | /// |
| 78 | /// All bit fields as a 64-bit value |
| 79 | /// |
| 80 | UINT64 Uint64; |
| 81 | } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER; |
| 82 | |
| 83 | |
| 84 | /** |
| 85 | Package. Platform Information Contains power management and other model |
| 86 | specific features enumeration. See http://biosbits.org. |
| 87 | |
| 88 | @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE) |
| 89 | @param EAX Lower 32-bits of MSR value. |
| 90 | Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER. |
| 91 | @param EDX Upper 32-bits of MSR value. |
| 92 | Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER. |
| 93 | |
| 94 | <b>Example usage</b> |
| 95 | @code |
| 96 | MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr; |
| 97 | |
| 98 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO); |
| 99 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64); |
| 100 | @endcode |
| 101 | @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. |
| 102 | **/ |
| 103 | #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE |
| 104 | |
| 105 | /** |
| 106 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO |
| 107 | **/ |
| 108 | typedef union { |
| 109 | /// |
| 110 | /// Individual bit fields |
| 111 | /// |
| 112 | struct { |
| 113 | UINT32 Reserved1:8; |
| 114 | /// |
| 115 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio |
| 116 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 |
| 117 | /// MHz. |
| 118 | /// |
| 119 | UINT32 MaximumNonTurboRatio:8; |
| 120 | UINT32 Reserved2:12; |
| 121 | /// |
| 122 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When |
| 123 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is |
| 124 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for |
| 125 | /// Turbo mode is disabled. |
| 126 | /// |
| 127 | UINT32 RatioLimit:1; |
| 128 | /// |
| 129 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When |
| 130 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable, |
| 131 | /// and when set to 0, indicates TDP Limit for Turbo mode is not |
| 132 | /// programmable. |
| 133 | /// |
| 134 | UINT32 TDPLimit:1; |
| 135 | UINT32 Reserved3:2; |
| 136 | UINT32 Reserved4:8; |
| 137 | /// |
| 138 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the |
| 139 | /// minimum ratio (maximum efficiency) that the processor can operates, in |
| 140 | /// units of 100MHz. |
| 141 | /// |
| 142 | UINT32 MaximumEfficiencyRatio:8; |
| 143 | UINT32 Reserved5:16; |
| 144 | } Bits; |
| 145 | /// |
| 146 | /// All bit fields as a 64-bit value |
| 147 | /// |
| 148 | UINT64 Uint64; |
| 149 | } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER; |
| 150 | |
| 151 | |
| 152 | /** |
| 153 | Core. C-State Configuration Control (R/W) Note: C-state values are |
| 154 | processor specific C-state code names, unrelated to MWAIT extension C-state |
| 155 | parameters or ACPI CStates. See http://biosbits.org. |
| 156 | |
| 157 | @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2) |
| 158 | @param EAX Lower 32-bits of MSR value. |
| 159 | Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 160 | @param EDX Upper 32-bits of MSR value. |
| 161 | Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 162 | |
| 163 | <b>Example usage</b> |
| 164 | @code |
| 165 | MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; |
| 166 | |
| 167 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL); |
| 168 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); |
| 169 | @endcode |
| 170 | @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. |
| 171 | **/ |
| 172 | #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2 |
| 173 | |
| 174 | /** |
| 175 | MSR information returned for MSR index |
| 176 | #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL |
| 177 | **/ |
| 178 | typedef union { |
| 179 | /// |
| 180 | /// Individual bit fields |
| 181 | /// |
| 182 | struct { |
| 183 | /// |
| 184 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest |
| 185 | /// processor-specific C-state code name (consuming the least power). for |
| 186 | /// the package. The default is set as factory-configured package C-state |
| 187 | /// limit. The following C-state code name encodings are supported: 000b: |
| 188 | /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: |
| 189 | /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: |
| 190 | /// This field cannot be used to limit package C-state to C3. |
| 191 | /// |
| 192 | UINT32 Limit:3; |
| 193 | UINT32 Reserved1:7; |
| 194 | /// |
| 195 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map |
| 196 | /// IO_read instructions sent to IO register specified by |
| 197 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. |
| 198 | /// |
| 199 | UINT32 IO_MWAIT:1; |
| 200 | UINT32 Reserved2:4; |
| 201 | /// |
| 202 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register |
| 203 | /// until next reset. |
| 204 | /// |
| 205 | UINT32 CFGLock:1; |
| 206 | UINT32 Reserved3:9; |
| 207 | /// |
| 208 | /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor |
| 209 | /// will conditionally demote C6/C7 requests to C3 based on uncore |
| 210 | /// auto-demote information. |
| 211 | /// |
| 212 | UINT32 C3AutoDemotion:1; |
| 213 | /// |
| 214 | /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor |
| 215 | /// will conditionally demote C3/C6/C7 requests to C1 based on uncore |
| 216 | /// auto-demote information. |
| 217 | /// |
| 218 | UINT32 C1AutoDemotion:1; |
| 219 | /// |
| 220 | /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from |
| 221 | /// demoted C3. |
| 222 | /// |
| 223 | UINT32 C3Undemotion:1; |
| 224 | /// |
| 225 | /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from |
| 226 | /// demoted C1. |
| 227 | /// |
| 228 | UINT32 C1Undemotion:1; |
| 229 | UINT32 Reserved4:3; |
| 230 | UINT32 Reserved5:32; |
| 231 | } Bits; |
| 232 | /// |
| 233 | /// All bit fields as a 32-bit value |
| 234 | /// |
| 235 | UINT32 Uint32; |
| 236 | /// |
| 237 | /// All bit fields as a 64-bit value |
| 238 | /// |
| 239 | UINT64 Uint64; |
| 240 | } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER; |
| 241 | |
| 242 | |
| 243 | /** |
| 244 | Core. Power Management IO Redirection in C-state (R/W) See |
| 245 | http://biosbits.org. |
| 246 | |
| 247 | @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4) |
| 248 | @param EAX Lower 32-bits of MSR value. |
| 249 | Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER. |
| 250 | @param EDX Upper 32-bits of MSR value. |
| 251 | Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER. |
| 252 | |
| 253 | <b>Example usage</b> |
| 254 | @code |
| 255 | MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr; |
| 256 | |
| 257 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE); |
| 258 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64); |
| 259 | @endcode |
| 260 | @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. |
| 261 | **/ |
| 262 | #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4 |
| 263 | |
| 264 | /** |
| 265 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE |
| 266 | **/ |
| 267 | typedef union { |
| 268 | /// |
| 269 | /// Individual bit fields |
| 270 | /// |
| 271 | struct { |
| 272 | /// |
| 273 | /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address |
| 274 | /// visible to software for IO redirection. If IO MWAIT Redirection is |
| 275 | /// enabled, reads to this address will be consumed by the power |
| 276 | /// management logic and decoded to MWAIT instructions. When IO port |
| 277 | /// address redirection is enabled, this is the IO port address reported |
| 278 | /// to the OS/software. |
| 279 | /// |
| 280 | UINT32 Lvl2Base:16; |
| 281 | /// |
| 282 | /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the |
| 283 | /// maximum C-State code name to be included when IO read to MWAIT |
| 284 | /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 |
| 285 | /// is the max C-State to include 001b - C6 is the max C-State to include |
| 286 | /// 010b - C7 is the max C-State to include. |
| 287 | /// |
| 288 | UINT32 CStateRange:3; |
| 289 | UINT32 Reserved1:13; |
| 290 | UINT32 Reserved2:32; |
| 291 | } Bits; |
| 292 | /// |
| 293 | /// All bit fields as a 32-bit value |
| 294 | /// |
| 295 | UINT32 Uint32; |
| 296 | /// |
| 297 | /// All bit fields as a 64-bit value |
| 298 | /// |
| 299 | UINT64 Uint64; |
| 300 | } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER; |
| 301 | |
| 302 | |
| 303 | /** |
| 304 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP |
| 305 | handler to handle unsuccessful read of this MSR. |
| 306 | |
| 307 | @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C) |
| 308 | @param EAX Lower 32-bits of MSR value. |
| 309 | Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER. |
| 310 | @param EDX Upper 32-bits of MSR value. |
| 311 | Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER. |
| 312 | |
| 313 | <b>Example usage</b> |
| 314 | @code |
| 315 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr; |
| 316 | |
| 317 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG); |
| 318 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64); |
| 319 | @endcode |
| 320 | @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. |
| 321 | **/ |
| 322 | #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C |
| 323 | |
| 324 | /** |
| 325 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG |
| 326 | **/ |
| 327 | typedef union { |
| 328 | /// |
| 329 | /// Individual bit fields |
| 330 | /// |
| 331 | struct { |
| 332 | /// |
| 333 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this |
| 334 | /// MSR, the configuration of AES instruction set availability is as |
| 335 | /// follows: 11b: AES instructions are not available until next RESET. |
| 336 | /// otherwise, AES instructions are available. Note, AES instruction set |
| 337 | /// is not available if read is unsuccessful. If the configuration is not |
| 338 | /// 01b, AES instruction can be mis-configured if a privileged agent |
| 339 | /// unintentionally writes 11b. |
| 340 | /// |
| 341 | UINT32 AESConfiguration:2; |
| 342 | UINT32 Reserved1:30; |
| 343 | UINT32 Reserved2:32; |
| 344 | } Bits; |
| 345 | /// |
| 346 | /// All bit fields as a 32-bit value |
| 347 | /// |
| 348 | UINT32 Uint32; |
| 349 | /// |
| 350 | /// All bit fields as a 64-bit value |
| 351 | /// |
| 352 | UINT64 Uint64; |
| 353 | } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER; |
| 354 | |
| 355 | |
| 356 | /** |
| 357 | Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8. |
| 358 | |
| 359 | @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn |
| 360 | @param EAX Lower 32-bits of MSR value. |
| 361 | @param EDX Upper 32-bits of MSR value. |
| 362 | |
| 363 | <b>Example usage</b> |
| 364 | @code |
| 365 | UINT64 Msr; |
| 366 | |
| 367 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4); |
| 368 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr); |
| 369 | @endcode |
| 370 | @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM. |
| 371 | MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM. |
| 372 | MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM. |
| 373 | MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM. |
| 374 | @{ |
| 375 | **/ |
| 376 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A |
| 377 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B |
| 378 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C |
| 379 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D |
| 380 | /// @} |
| 381 | |
| 382 | |
| 383 | /** |
| 384 | Package. |
| 385 | |
| 386 | @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198) |
| 387 | @param EAX Lower 32-bits of MSR value. |
| 388 | Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER. |
| 389 | @param EDX Upper 32-bits of MSR value. |
| 390 | Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER. |
| 391 | |
| 392 | <b>Example usage</b> |
| 393 | @code |
| 394 | MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr; |
| 395 | |
| 396 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS); |
| 397 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64); |
| 398 | @endcode |
| 399 | @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM. |
| 400 | **/ |
| 401 | #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198 |
| 402 | |
| 403 | /** |
| 404 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS |
| 405 | **/ |
| 406 | typedef union { |
| 407 | /// |
| 408 | /// Individual bit fields |
| 409 | /// |
| 410 | struct { |
| 411 | UINT32 Reserved1:32; |
| 412 | /// |
| 413 | /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed |
| 414 | /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13). |
| 415 | /// |
| 416 | UINT32 CoreVoltage:16; |
| 417 | UINT32 Reserved2:16; |
| 418 | } Bits; |
| 419 | /// |
| 420 | /// All bit fields as a 64-bit value |
| 421 | /// |
| 422 | UINT64 Uint64; |
| 423 | } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER; |
| 424 | |
| 425 | |
| 426 | /** |
| 427 | Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was |
| 428 | originally named IA32_THERM_CONTROL MSR. |
| 429 | |
| 430 | @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A) |
| 431 | @param EAX Lower 32-bits of MSR value. |
| 432 | Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER. |
| 433 | @param EDX Upper 32-bits of MSR value. |
| 434 | Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER. |
| 435 | |
| 436 | <b>Example usage</b> |
| 437 | @code |
| 438 | MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr; |
| 439 | |
| 440 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION); |
| 441 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64); |
| 442 | @endcode |
| 443 | @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. |
| 444 | **/ |
| 445 | #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A |
| 446 | |
| 447 | /** |
| 448 | MSR information returned for MSR index |
| 449 | #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION |
| 450 | **/ |
| 451 | typedef union { |
| 452 | /// |
| 453 | /// Individual bit fields |
| 454 | /// |
| 455 | struct { |
| 456 | /// |
| 457 | /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25% |
| 458 | /// increment. |
| 459 | /// |
| 460 | UINT32 OnDemandClockModulationDutyCycle:4; |
| 461 | /// |
| 462 | /// [Bit 4] On demand Clock Modulation Enable (R/W). |
| 463 | /// |
| 464 | UINT32 OnDemandClockModulationEnable:1; |
| 465 | UINT32 Reserved1:27; |
| 466 | UINT32 Reserved2:32; |
| 467 | } Bits; |
| 468 | /// |
| 469 | /// All bit fields as a 32-bit value |
| 470 | /// |
| 471 | UINT32 Uint32; |
| 472 | /// |
| 473 | /// All bit fields as a 64-bit value |
| 474 | /// |
| 475 | UINT64 Uint64; |
| 476 | } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER; |
| 477 | |
| 478 | |
| 479 | /** |
| 480 | Enable Misc. Processor Features (R/W) Allows a variety of processor |
| 481 | functions to be enabled and disabled. |
| 482 | |
| 483 | @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0) |
| 484 | @param EAX Lower 32-bits of MSR value. |
| 485 | Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER. |
| 486 | @param EDX Upper 32-bits of MSR value. |
| 487 | Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER. |
| 488 | |
| 489 | <b>Example usage</b> |
| 490 | @code |
| 491 | MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr; |
| 492 | |
| 493 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE); |
| 494 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64); |
| 495 | @endcode |
| 496 | @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. |
| 497 | **/ |
| 498 | #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0 |
| 499 | |
| 500 | /** |
| 501 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE |
| 502 | **/ |
| 503 | typedef union { |
| 504 | /// |
| 505 | /// Individual bit fields |
| 506 | /// |
| 507 | struct { |
| 508 | /// |
| 509 | /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2. |
| 510 | /// |
| 511 | UINT32 FastStrings:1; |
| 512 | UINT32 Reserved1:6; |
| 513 | /// |
| 514 | /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2. |
| 515 | /// |
| 516 | UINT32 PerformanceMonitoring:1; |
| 517 | UINT32 Reserved2:3; |
| 518 | /// |
| 519 | /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2. |
| 520 | /// |
| 521 | UINT32 BTS:1; |
| 522 | /// |
| 523 | /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See |
| 524 | /// Table 2-2. |
| 525 | /// |
| 526 | UINT32 PEBS:1; |
| 527 | UINT32 Reserved3:3; |
| 528 | /// |
| 529 | /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See |
| 530 | /// Table 2-2. |
| 531 | /// |
| 532 | UINT32 EIST:1; |
| 533 | UINT32 Reserved4:1; |
| 534 | /// |
| 535 | /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2. |
| 536 | /// |
| 537 | UINT32 MONITOR:1; |
| 538 | UINT32 Reserved5:3; |
| 539 | /// |
| 540 | /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2. |
| 541 | /// |
| 542 | UINT32 LimitCpuidMaxval:1; |
| 543 | /// |
| 544 | /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2. |
| 545 | /// |
| 546 | UINT32 xTPR_Message_Disable:1; |
| 547 | UINT32 Reserved6:8; |
| 548 | UINT32 Reserved7:2; |
| 549 | /// |
| 550 | /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2. |
| 551 | /// |
| 552 | UINT32 XD:1; |
| 553 | UINT32 Reserved8:3; |
| 554 | /// |
| 555 | /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors |
| 556 | /// that support Intel Turbo Boost Technology, the turbo mode feature is |
| 557 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: |
| 558 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: |
| 559 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note: |
| 560 | /// the power-on default value is used by BIOS to detect hardware support |
| 561 | /// of turbo mode. If power-on default value is 1, turbo mode is available |
| 562 | /// in the processor. If power-on default value is 0, turbo mode is not |
| 563 | /// available. |
| 564 | /// |
| 565 | UINT32 TurboModeDisable:1; |
| 566 | UINT32 Reserved9:25; |
| 567 | } Bits; |
| 568 | /// |
| 569 | /// All bit fields as a 64-bit value |
| 570 | /// |
| 571 | UINT64 Uint64; |
| 572 | } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER; |
| 573 | |
| 574 | |
| 575 | /** |
| 576 | Unique. |
| 577 | |
| 578 | @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2) |
| 579 | @param EAX Lower 32-bits of MSR value. |
| 580 | Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER. |
| 581 | @param EDX Upper 32-bits of MSR value. |
| 582 | Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER. |
| 583 | |
| 584 | <b>Example usage</b> |
| 585 | @code |
| 586 | MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr; |
| 587 | |
| 588 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET); |
| 589 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64); |
| 590 | @endcode |
| 591 | @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. |
| 592 | **/ |
| 593 | #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2 |
| 594 | |
| 595 | /** |
| 596 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET |
| 597 | **/ |
| 598 | typedef union { |
| 599 | /// |
| 600 | /// Individual bit fields |
| 601 | /// |
| 602 | struct { |
| 603 | UINT32 Reserved1:16; |
| 604 | /// |
| 605 | /// [Bits 23:16] Temperature Target (R) The minimum temperature at which |
| 606 | /// PROCHOT# will be asserted. The value is degree C. |
| 607 | /// |
| 608 | UINT32 TemperatureTarget:8; |
| 609 | UINT32 Reserved2:8; |
| 610 | UINT32 Reserved3:32; |
| 611 | } Bits; |
| 612 | /// |
| 613 | /// All bit fields as a 32-bit value |
| 614 | /// |
| 615 | UINT32 Uint32; |
| 616 | /// |
| 617 | /// All bit fields as a 64-bit value |
| 618 | /// |
| 619 | UINT64 Uint64; |
| 620 | } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER; |
| 621 | |
| 622 | |
| 623 | /** |
| 624 | Miscellaneous Feature Control (R/W). |
| 625 | |
| 626 | @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4) |
| 627 | @param EAX Lower 32-bits of MSR value. |
| 628 | Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER. |
| 629 | @param EDX Upper 32-bits of MSR value. |
| 630 | Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER. |
| 631 | |
| 632 | <b>Example usage</b> |
| 633 | @code |
| 634 | MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr; |
| 635 | |
| 636 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL); |
| 637 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64); |
| 638 | @endcode |
| 639 | @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. |
| 640 | **/ |
| 641 | #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4 |
| 642 | |
| 643 | /** |
| 644 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL |
| 645 | **/ |
| 646 | typedef union { |
| 647 | /// |
| 648 | /// Individual bit fields |
| 649 | /// |
| 650 | struct { |
| 651 | /// |
| 652 | /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the |
| 653 | /// L2 hardware prefetcher, which fetches additional lines of code or data |
| 654 | /// into the L2 cache. |
| 655 | /// |
| 656 | UINT32 L2HardwarePrefetcherDisable:1; |
| 657 | /// |
| 658 | /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, |
| 659 | /// disables the adjacent cache line prefetcher, which fetches the cache |
| 660 | /// line that comprises a cache line pair (128 bytes). |
| 661 | /// |
| 662 | UINT32 L2AdjacentCacheLinePrefetcherDisable:1; |
| 663 | /// |
| 664 | /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables |
| 665 | /// the L1 data cache prefetcher, which fetches the next cache line into |
| 666 | /// L1 data cache. |
| 667 | /// |
| 668 | UINT32 DCUHardwarePrefetcherDisable:1; |
| 669 | /// |
| 670 | /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 |
| 671 | /// data cache IP prefetcher, which uses sequential load history (based on |
| 672 | /// instruction Pointer of previous loads) to determine whether to |
| 673 | /// prefetch additional lines. |
| 674 | /// |
| 675 | UINT32 DCUIPPrefetcherDisable:1; |
| 676 | UINT32 Reserved1:28; |
| 677 | UINT32 Reserved2:32; |
| 678 | } Bits; |
| 679 | /// |
| 680 | /// All bit fields as a 32-bit value |
| 681 | /// |
| 682 | UINT32 Uint32; |
| 683 | /// |
| 684 | /// All bit fields as a 64-bit value |
| 685 | /// |
| 686 | UINT64 Uint64; |
| 687 | } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER; |
| 688 | |
| 689 | |
| 690 | /** |
| 691 | Thread. Offcore Response Event Select Register (R/W). |
| 692 | |
| 693 | @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6) |
| 694 | @param EAX Lower 32-bits of MSR value. |
| 695 | @param EDX Upper 32-bits of MSR value. |
| 696 | |
| 697 | <b>Example usage</b> |
| 698 | @code |
| 699 | UINT64 Msr; |
| 700 | |
| 701 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0); |
| 702 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr); |
| 703 | @endcode |
| 704 | @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. |
| 705 | **/ |
| 706 | #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6 |
| 707 | |
| 708 | |
| 709 | /** |
| 710 | Thread. Offcore Response Event Select Register (R/W). |
| 711 | |
| 712 | @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7) |
| 713 | @param EAX Lower 32-bits of MSR value. |
| 714 | @param EDX Upper 32-bits of MSR value. |
| 715 | |
| 716 | <b>Example usage</b> |
| 717 | @code |
| 718 | UINT64 Msr; |
| 719 | |
| 720 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1); |
| 721 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr); |
| 722 | @endcode |
| 723 | @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. |
| 724 | **/ |
| 725 | #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7 |
| 726 | |
| 727 | |
| 728 | /** |
| 729 | See http://biosbits.org. |
| 730 | |
| 731 | @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA) |
| 732 | @param EAX Lower 32-bits of MSR value. |
| 733 | @param EDX Upper 32-bits of MSR value. |
| 734 | |
| 735 | <b>Example usage</b> |
| 736 | @code |
| 737 | UINT64 Msr; |
| 738 | |
| 739 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT); |
| 740 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr); |
| 741 | @endcode |
| 742 | @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM. |
| 743 | **/ |
| 744 | #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA |
| 745 | |
| 746 | |
| 747 | /** |
| 748 | Thread. Last Branch Record Filtering Select Register (R/W) See Section |
| 749 | 17.9.2, "Filtering of Last Branch Records.". |
| 750 | |
| 751 | @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8) |
| 752 | @param EAX Lower 32-bits of MSR value. |
| 753 | Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER. |
| 754 | @param EDX Upper 32-bits of MSR value. |
| 755 | Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER. |
| 756 | |
| 757 | <b>Example usage</b> |
| 758 | @code |
| 759 | MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr; |
| 760 | |
| 761 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT); |
| 762 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64); |
| 763 | @endcode |
| 764 | @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. |
| 765 | **/ |
| 766 | #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8 |
| 767 | |
| 768 | /** |
| 769 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT |
| 770 | **/ |
| 771 | typedef union { |
| 772 | /// |
| 773 | /// Individual bit fields |
| 774 | /// |
| 775 | struct { |
| 776 | /// |
| 777 | /// [Bit 0] CPL_EQ_0. |
| 778 | /// |
| 779 | UINT32 CPL_EQ_0:1; |
| 780 | /// |
| 781 | /// [Bit 1] CPL_NEQ_0. |
| 782 | /// |
| 783 | UINT32 CPL_NEQ_0:1; |
| 784 | /// |
| 785 | /// [Bit 2] JCC. |
| 786 | /// |
| 787 | UINT32 JCC:1; |
| 788 | /// |
| 789 | /// [Bit 3] NEAR_REL_CALL. |
| 790 | /// |
| 791 | UINT32 NEAR_REL_CALL:1; |
| 792 | /// |
| 793 | /// [Bit 4] NEAR_IND_CALL. |
| 794 | /// |
| 795 | UINT32 NEAR_IND_CALL:1; |
| 796 | /// |
| 797 | /// [Bit 5] NEAR_RET. |
| 798 | /// |
| 799 | UINT32 NEAR_RET:1; |
| 800 | /// |
| 801 | /// [Bit 6] NEAR_IND_JMP. |
| 802 | /// |
| 803 | UINT32 NEAR_IND_JMP:1; |
| 804 | /// |
| 805 | /// [Bit 7] NEAR_REL_JMP. |
| 806 | /// |
| 807 | UINT32 NEAR_REL_JMP:1; |
| 808 | /// |
| 809 | /// [Bit 8] FAR_BRANCH. |
| 810 | /// |
| 811 | UINT32 FAR_BRANCH:1; |
| 812 | UINT32 Reserved1:23; |
| 813 | UINT32 Reserved2:32; |
| 814 | } Bits; |
| 815 | /// |
| 816 | /// All bit fields as a 32-bit value |
| 817 | /// |
| 818 | UINT32 Uint32; |
| 819 | /// |
| 820 | /// All bit fields as a 64-bit value |
| 821 | /// |
| 822 | UINT64 Uint64; |
| 823 | } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER; |
| 824 | |
| 825 | |
| 826 | /** |
| 827 | Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) |
| 828 | that points to the MSR containing the most recent branch record. See |
| 829 | MSR_LASTBRANCH_0_FROM_IP (at 680H). |
| 830 | |
| 831 | @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9) |
| 832 | @param EAX Lower 32-bits of MSR value. |
| 833 | @param EDX Upper 32-bits of MSR value. |
| 834 | |
| 835 | <b>Example usage</b> |
| 836 | @code |
| 837 | UINT64 Msr; |
| 838 | |
| 839 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS); |
| 840 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr); |
| 841 | @endcode |
| 842 | @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. |
| 843 | **/ |
| 844 | #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9 |
| 845 | |
| 846 | |
| 847 | /** |
| 848 | Thread. Last Exception Record From Linear IP (R) Contains a pointer to the |
| 849 | last branch instruction that the processor executed prior to the last |
| 850 | exception that was generated or the last interrupt that was handled. |
| 851 | |
| 852 | @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD) |
| 853 | @param EAX Lower 32-bits of MSR value. |
| 854 | @param EDX Upper 32-bits of MSR value. |
| 855 | |
| 856 | <b>Example usage</b> |
| 857 | @code |
| 858 | UINT64 Msr; |
| 859 | |
| 860 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP); |
| 861 | @endcode |
| 862 | @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. |
| 863 | **/ |
| 864 | #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD |
| 865 | |
| 866 | |
| 867 | /** |
| 868 | Thread. Last Exception Record To Linear IP (R) This area contains a pointer |
| 869 | to the target of the last branch instruction that the processor executed |
| 870 | prior to the last exception that was generated or the last interrupt that |
| 871 | was handled. |
| 872 | |
| 873 | @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE) |
| 874 | @param EAX Lower 32-bits of MSR value. |
| 875 | @param EDX Upper 32-bits of MSR value. |
| 876 | |
| 877 | <b>Example usage</b> |
| 878 | @code |
| 879 | UINT64 Msr; |
| 880 | |
| 881 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP); |
| 882 | @endcode |
| 883 | @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. |
| 884 | **/ |
| 885 | #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE |
| 886 | |
| 887 | |
| 888 | /** |
| 889 | Core. See http://biosbits.org. |
| 890 | |
| 891 | @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC) |
| 892 | @param EAX Lower 32-bits of MSR value. |
| 893 | @param EDX Upper 32-bits of MSR value. |
| 894 | |
| 895 | <b>Example usage</b> |
| 896 | @code |
| 897 | UINT64 Msr; |
| 898 | |
| 899 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL); |
| 900 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr); |
| 901 | @endcode |
| 902 | @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM. |
| 903 | **/ |
| 904 | #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC |
| 905 | |
| 906 | |
| 907 | /** |
| 908 | Package. Always 0 (CMCI not supported). |
| 909 | |
| 910 | @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284) |
| 911 | @param EAX Lower 32-bits of MSR value. |
| 912 | @param EDX Upper 32-bits of MSR value. |
| 913 | |
| 914 | <b>Example usage</b> |
| 915 | @code |
| 916 | UINT64 Msr; |
| 917 | |
| 918 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2); |
| 919 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr); |
| 920 | @endcode |
| 921 | @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. |
| 922 | **/ |
| 923 | #define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284 |
| 924 | |
| 925 | |
| 926 | /** |
| 927 | See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.". |
| 928 | |
| 929 | @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E) |
| 930 | @param EAX Lower 32-bits of MSR value. |
| 931 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER. |
| 932 | @param EDX Upper 32-bits of MSR value. |
| 933 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER. |
| 934 | |
| 935 | <b>Example usage</b> |
| 936 | @code |
| 937 | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; |
| 938 | |
| 939 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS); |
| 940 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); |
| 941 | @endcode |
| 942 | @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. |
| 943 | **/ |
| 944 | #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E |
| 945 | |
| 946 | /** |
| 947 | MSR information returned for MSR index |
| 948 | #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS |
| 949 | **/ |
| 950 | typedef union { |
| 951 | /// |
| 952 | /// Individual bit fields |
| 953 | /// |
| 954 | struct { |
| 955 | /// |
| 956 | /// [Bit 0] Thread. Ovf_PMC0. |
| 957 | /// |
| 958 | UINT32 Ovf_PMC0:1; |
| 959 | /// |
| 960 | /// [Bit 1] Thread. Ovf_PMC1. |
| 961 | /// |
| 962 | UINT32 Ovf_PMC1:1; |
| 963 | /// |
| 964 | /// [Bit 2] Thread. Ovf_PMC2. |
| 965 | /// |
| 966 | UINT32 Ovf_PMC2:1; |
| 967 | /// |
| 968 | /// [Bit 3] Thread. Ovf_PMC3. |
| 969 | /// |
| 970 | UINT32 Ovf_PMC3:1; |
| 971 | /// |
| 972 | /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). |
| 973 | /// |
| 974 | UINT32 Ovf_PMC4:1; |
| 975 | /// |
| 976 | /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). |
| 977 | /// |
| 978 | UINT32 Ovf_PMC5:1; |
| 979 | /// |
| 980 | /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). |
| 981 | /// |
| 982 | UINT32 Ovf_PMC6:1; |
| 983 | /// |
| 984 | /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). |
| 985 | /// |
| 986 | UINT32 Ovf_PMC7:1; |
| 987 | UINT32 Reserved1:24; |
| 988 | /// |
| 989 | /// [Bit 32] Thread. Ovf_FixedCtr0. |
| 990 | /// |
| 991 | UINT32 Ovf_FixedCtr0:1; |
| 992 | /// |
| 993 | /// [Bit 33] Thread. Ovf_FixedCtr1. |
| 994 | /// |
| 995 | UINT32 Ovf_FixedCtr1:1; |
| 996 | /// |
| 997 | /// [Bit 34] Thread. Ovf_FixedCtr2. |
| 998 | /// |
| 999 | UINT32 Ovf_FixedCtr2:1; |
| 1000 | UINT32 Reserved2:26; |
| 1001 | /// |
| 1002 | /// [Bit 61] Thread. Ovf_Uncore. |
| 1003 | /// |
| 1004 | UINT32 Ovf_Uncore:1; |
| 1005 | /// |
| 1006 | /// [Bit 62] Thread. Ovf_BufDSSAVE. |
| 1007 | /// |
| 1008 | UINT32 Ovf_BufDSSAVE:1; |
| 1009 | /// |
| 1010 | /// [Bit 63] Thread. CondChgd. |
| 1011 | /// |
| 1012 | UINT32 CondChgd:1; |
| 1013 | } Bits; |
| 1014 | /// |
| 1015 | /// All bit fields as a 64-bit value |
| 1016 | /// |
| 1017 | UINT64 Uint64; |
| 1018 | } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER; |
| 1019 | |
| 1020 | |
| 1021 | /** |
| 1022 | Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control |
| 1023 | Facilities.". |
| 1024 | |
| 1025 | @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F) |
| 1026 | @param EAX Lower 32-bits of MSR value. |
| 1027 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER. |
| 1028 | @param EDX Upper 32-bits of MSR value. |
| 1029 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER. |
| 1030 | |
| 1031 | <b>Example usage</b> |
| 1032 | @code |
| 1033 | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; |
| 1034 | |
| 1035 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL); |
| 1036 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); |
| 1037 | @endcode |
| 1038 | @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. |
| 1039 | **/ |
| 1040 | #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F |
| 1041 | |
| 1042 | /** |
| 1043 | MSR information returned for MSR index |
| 1044 | #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL |
| 1045 | **/ |
| 1046 | typedef union { |
| 1047 | /// |
| 1048 | /// Individual bit fields |
| 1049 | /// |
| 1050 | struct { |
| 1051 | /// |
| 1052 | /// [Bit 0] Thread. Set 1 to enable PMC0 to count. |
| 1053 | /// |
| 1054 | UINT32 PCM0_EN:1; |
| 1055 | /// |
| 1056 | /// [Bit 1] Thread. Set 1 to enable PMC1 to count. |
| 1057 | /// |
| 1058 | UINT32 PCM1_EN:1; |
| 1059 | /// |
| 1060 | /// [Bit 2] Thread. Set 1 to enable PMC2 to count. |
| 1061 | /// |
| 1062 | UINT32 PCM2_EN:1; |
| 1063 | /// |
| 1064 | /// [Bit 3] Thread. Set 1 to enable PMC3 to count. |
| 1065 | /// |
| 1066 | UINT32 PCM3_EN:1; |
| 1067 | /// |
| 1068 | /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > |
| 1069 | /// 4). |
| 1070 | /// |
| 1071 | UINT32 PCM4_EN:1; |
| 1072 | /// |
| 1073 | /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > |
| 1074 | /// 5). |
| 1075 | /// |
| 1076 | UINT32 PCM5_EN:1; |
| 1077 | /// |
| 1078 | /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > |
| 1079 | /// 6). |
| 1080 | /// |
| 1081 | UINT32 PCM6_EN:1; |
| 1082 | /// |
| 1083 | /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > |
| 1084 | /// 7). |
| 1085 | /// |
| 1086 | UINT32 PCM7_EN:1; |
| 1087 | UINT32 Reserved1:24; |
| 1088 | /// |
| 1089 | /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count. |
| 1090 | /// |
| 1091 | UINT32 FIXED_CTR0:1; |
| 1092 | /// |
| 1093 | /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count. |
| 1094 | /// |
| 1095 | UINT32 FIXED_CTR1:1; |
| 1096 | /// |
| 1097 | /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count. |
| 1098 | /// |
| 1099 | UINT32 FIXED_CTR2:1; |
| 1100 | UINT32 Reserved2:29; |
| 1101 | } Bits; |
| 1102 | /// |
| 1103 | /// All bit fields as a 64-bit value |
| 1104 | /// |
| 1105 | UINT64 Uint64; |
| 1106 | } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER; |
| 1107 | |
| 1108 | |
| 1109 | /** |
| 1110 | See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.". |
| 1111 | |
| 1112 | @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) |
| 1113 | @param EAX Lower 32-bits of MSR value. |
| 1114 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. |
| 1115 | @param EDX Upper 32-bits of MSR value. |
| 1116 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. |
| 1117 | |
| 1118 | <b>Example usage</b> |
| 1119 | @code |
| 1120 | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; |
| 1121 | |
| 1122 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL); |
| 1123 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); |
| 1124 | @endcode |
| 1125 | @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. |
| 1126 | **/ |
| 1127 | #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 |
| 1128 | |
| 1129 | /** |
| 1130 | MSR information returned for MSR index |
| 1131 | #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL |
| 1132 | **/ |
| 1133 | typedef union { |
| 1134 | /// |
| 1135 | /// Individual bit fields |
| 1136 | /// |
| 1137 | struct { |
| 1138 | /// |
| 1139 | /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0. |
| 1140 | /// |
| 1141 | UINT32 Ovf_PMC0:1; |
| 1142 | /// |
| 1143 | /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1. |
| 1144 | /// |
| 1145 | UINT32 Ovf_PMC1:1; |
| 1146 | /// |
| 1147 | /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2. |
| 1148 | /// |
| 1149 | UINT32 Ovf_PMC2:1; |
| 1150 | /// |
| 1151 | /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3. |
| 1152 | /// |
| 1153 | UINT32 Ovf_PMC3:1; |
| 1154 | /// |
| 1155 | /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). |
| 1156 | /// |
| 1157 | UINT32 Ovf_PMC4:1; |
| 1158 | /// |
| 1159 | /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). |
| 1160 | /// |
| 1161 | UINT32 Ovf_PMC5:1; |
| 1162 | /// |
| 1163 | /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). |
| 1164 | /// |
| 1165 | UINT32 Ovf_PMC6:1; |
| 1166 | /// |
| 1167 | /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). |
| 1168 | /// |
| 1169 | UINT32 Ovf_PMC7:1; |
| 1170 | UINT32 Reserved1:24; |
| 1171 | /// |
| 1172 | /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0. |
| 1173 | /// |
| 1174 | UINT32 Ovf_FixedCtr0:1; |
| 1175 | /// |
| 1176 | /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1. |
| 1177 | /// |
| 1178 | UINT32 Ovf_FixedCtr1:1; |
| 1179 | /// |
| 1180 | /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2. |
| 1181 | /// |
| 1182 | UINT32 Ovf_FixedCtr2:1; |
| 1183 | UINT32 Reserved2:26; |
| 1184 | /// |
| 1185 | /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore. |
| 1186 | /// |
| 1187 | UINT32 Ovf_Uncore:1; |
| 1188 | /// |
| 1189 | /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE. |
| 1190 | /// |
| 1191 | UINT32 Ovf_BufDSSAVE:1; |
| 1192 | /// |
| 1193 | /// [Bit 63] Thread. Set 1 to clear CondChgd. |
| 1194 | /// |
| 1195 | UINT32 CondChgd:1; |
| 1196 | } Bits; |
| 1197 | /// |
| 1198 | /// All bit fields as a 64-bit value |
| 1199 | /// |
| 1200 | UINT64 Uint64; |
| 1201 | } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; |
| 1202 | |
| 1203 | |
| 1204 | /** |
| 1205 | Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).". |
| 1206 | |
| 1207 | @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1) |
| 1208 | @param EAX Lower 32-bits of MSR value. |
| 1209 | Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER. |
| 1210 | @param EDX Upper 32-bits of MSR value. |
| 1211 | Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER. |
| 1212 | |
| 1213 | <b>Example usage</b> |
| 1214 | @code |
| 1215 | MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr; |
| 1216 | |
| 1217 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE); |
| 1218 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64); |
| 1219 | @endcode |
| 1220 | @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. |
| 1221 | **/ |
| 1222 | #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1 |
| 1223 | |
| 1224 | /** |
| 1225 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE |
| 1226 | **/ |
| 1227 | typedef union { |
| 1228 | /// |
| 1229 | /// Individual bit fields |
| 1230 | /// |
| 1231 | struct { |
| 1232 | /// |
| 1233 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). |
| 1234 | /// |
| 1235 | UINT32 PEBS_EN_PMC0:1; |
| 1236 | /// |
| 1237 | /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). |
| 1238 | /// |
| 1239 | UINT32 PEBS_EN_PMC1:1; |
| 1240 | /// |
| 1241 | /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). |
| 1242 | /// |
| 1243 | UINT32 PEBS_EN_PMC2:1; |
| 1244 | /// |
| 1245 | /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). |
| 1246 | /// |
| 1247 | UINT32 PEBS_EN_PMC3:1; |
| 1248 | UINT32 Reserved1:28; |
| 1249 | /// |
| 1250 | /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). |
| 1251 | /// |
| 1252 | UINT32 LL_EN_PMC0:1; |
| 1253 | /// |
| 1254 | /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). |
| 1255 | /// |
| 1256 | UINT32 LL_EN_PMC1:1; |
| 1257 | /// |
| 1258 | /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). |
| 1259 | /// |
| 1260 | UINT32 LL_EN_PMC2:1; |
| 1261 | /// |
| 1262 | /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). |
| 1263 | /// |
| 1264 | UINT32 LL_EN_PMC3:1; |
| 1265 | UINT32 Reserved2:27; |
| 1266 | /// |
| 1267 | /// [Bit 63] Enable Precise Store. (R/W). |
| 1268 | /// |
| 1269 | UINT32 PS_EN:1; |
| 1270 | } Bits; |
| 1271 | /// |
| 1272 | /// All bit fields as a 64-bit value |
| 1273 | /// |
| 1274 | UINT64 Uint64; |
| 1275 | } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER; |
| 1276 | |
| 1277 | |
| 1278 | /** |
| 1279 | Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring |
| 1280 | Facility.". |
| 1281 | |
| 1282 | @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6) |
| 1283 | @param EAX Lower 32-bits of MSR value. |
| 1284 | Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER. |
| 1285 | @param EDX Upper 32-bits of MSR value. |
| 1286 | Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER. |
| 1287 | |
| 1288 | <b>Example usage</b> |
| 1289 | @code |
| 1290 | MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr; |
| 1291 | |
| 1292 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT); |
| 1293 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64); |
| 1294 | @endcode |
| 1295 | @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM. |
| 1296 | **/ |
| 1297 | #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6 |
| 1298 | |
| 1299 | /** |
| 1300 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT |
| 1301 | **/ |
| 1302 | typedef union { |
| 1303 | /// |
| 1304 | /// Individual bit fields |
| 1305 | /// |
| 1306 | struct { |
| 1307 | /// |
| 1308 | /// [Bits 15:0] Minimum threshold latency value of tagged load operation |
| 1309 | /// that will be counted. (R/W). |
| 1310 | /// |
| 1311 | UINT32 MinimumThreshold:16; |
| 1312 | UINT32 Reserved1:16; |
| 1313 | UINT32 Reserved2:32; |
| 1314 | } Bits; |
| 1315 | /// |
| 1316 | /// All bit fields as a 32-bit value |
| 1317 | /// |
| 1318 | UINT32 Uint32; |
| 1319 | /// |
| 1320 | /// All bit fields as a 64-bit value |
| 1321 | /// |
| 1322 | UINT64 Uint64; |
| 1323 | } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER; |
| 1324 | |
| 1325 | |
| 1326 | /** |
| 1327 | Package. Note: C-state values are processor specific C-state code names, |
| 1328 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 |
| 1329 | Residency Counter. (R/O) Value since last reset that this package is in |
| 1330 | processor-specific C3 states. Count at the same frequency as the TSC. |
| 1331 | |
| 1332 | @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8) |
| 1333 | @param EAX Lower 32-bits of MSR value. |
| 1334 | @param EDX Upper 32-bits of MSR value. |
| 1335 | |
| 1336 | <b>Example usage</b> |
| 1337 | @code |
| 1338 | UINT64 Msr; |
| 1339 | |
| 1340 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY); |
| 1341 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr); |
| 1342 | @endcode |
| 1343 | @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. |
| 1344 | **/ |
| 1345 | #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8 |
| 1346 | |
| 1347 | |
| 1348 | /** |
| 1349 | Package. Note: C-state values are processor specific C-state code names, |
| 1350 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 |
| 1351 | Residency Counter. (R/O) Value since last reset that this package is in |
| 1352 | processor-specific C6 states. Count at the same frequency as the TSC. |
| 1353 | |
| 1354 | @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9) |
| 1355 | @param EAX Lower 32-bits of MSR value. |
| 1356 | @param EDX Upper 32-bits of MSR value. |
| 1357 | |
| 1358 | <b>Example usage</b> |
| 1359 | @code |
| 1360 | UINT64 Msr; |
| 1361 | |
| 1362 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY); |
| 1363 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr); |
| 1364 | @endcode |
| 1365 | @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. |
| 1366 | **/ |
| 1367 | #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9 |
| 1368 | |
| 1369 | |
| 1370 | /** |
| 1371 | Package. Note: C-state values are processor specific C-state code names, |
| 1372 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7 |
| 1373 | Residency Counter. (R/O) Value since last reset that this package is in |
| 1374 | processor-specific C7 states. Count at the same frequency as the TSC. |
| 1375 | |
| 1376 | @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA) |
| 1377 | @param EAX Lower 32-bits of MSR value. |
| 1378 | @param EDX Upper 32-bits of MSR value. |
| 1379 | |
| 1380 | <b>Example usage</b> |
| 1381 | @code |
| 1382 | UINT64 Msr; |
| 1383 | |
| 1384 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY); |
| 1385 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr); |
| 1386 | @endcode |
| 1387 | @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM. |
| 1388 | **/ |
| 1389 | #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA |
| 1390 | |
| 1391 | |
| 1392 | /** |
| 1393 | Core. Note: C-state values are processor specific C-state code names, |
| 1394 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 |
| 1395 | Residency Counter. (R/O) Value since last reset that this core is in |
| 1396 | processor-specific C3 states. Count at the same frequency as the TSC. |
| 1397 | |
| 1398 | @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC) |
| 1399 | @param EAX Lower 32-bits of MSR value. |
| 1400 | @param EDX Upper 32-bits of MSR value. |
| 1401 | |
| 1402 | <b>Example usage</b> |
| 1403 | @code |
| 1404 | UINT64 Msr; |
| 1405 | |
| 1406 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY); |
| 1407 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr); |
| 1408 | @endcode |
| 1409 | @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM. |
| 1410 | **/ |
| 1411 | #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC |
| 1412 | |
| 1413 | |
| 1414 | /** |
| 1415 | Core. Note: C-state values are processor specific C-state code names, |
| 1416 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 |
| 1417 | Residency Counter. (R/O) Value since last reset that this core is in |
| 1418 | processor-specific C6 states. Count at the same frequency as the TSC. |
| 1419 | |
| 1420 | @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD) |
| 1421 | @param EAX Lower 32-bits of MSR value. |
| 1422 | @param EDX Upper 32-bits of MSR value. |
| 1423 | |
| 1424 | <b>Example usage</b> |
| 1425 | @code |
| 1426 | UINT64 Msr; |
| 1427 | |
| 1428 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY); |
| 1429 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr); |
| 1430 | @endcode |
| 1431 | @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. |
| 1432 | **/ |
| 1433 | #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD |
| 1434 | |
| 1435 | |
| 1436 | /** |
| 1437 | Core. Note: C-state values are processor specific C-state code names, |
| 1438 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7 |
| 1439 | Residency Counter. (R/O) Value since last reset that this core is in |
| 1440 | processor-specific C7 states. Count at the same frequency as the TSC. |
| 1441 | |
| 1442 | @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE) |
| 1443 | @param EAX Lower 32-bits of MSR value. |
| 1444 | @param EDX Upper 32-bits of MSR value. |
| 1445 | |
| 1446 | <b>Example usage</b> |
| 1447 | @code |
| 1448 | UINT64 Msr; |
| 1449 | |
| 1450 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY); |
| 1451 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr); |
| 1452 | @endcode |
| 1453 | @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM. |
| 1454 | **/ |
| 1455 | #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE |
| 1456 | |
| 1457 | |
| 1458 | /** |
| 1459 | Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". |
| 1460 | |
| 1461 | @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410) |
| 1462 | @param EAX Lower 32-bits of MSR value. |
| 1463 | Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER. |
| 1464 | @param EDX Upper 32-bits of MSR value. |
| 1465 | Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER. |
| 1466 | |
| 1467 | <b>Example usage</b> |
| 1468 | @code |
| 1469 | MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr; |
| 1470 | |
| 1471 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL); |
| 1472 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64); |
| 1473 | @endcode |
| 1474 | @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. |
| 1475 | **/ |
| 1476 | #define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410 |
| 1477 | |
| 1478 | /** |
| 1479 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL |
| 1480 | **/ |
| 1481 | typedef union { |
| 1482 | /// |
| 1483 | /// Individual bit fields |
| 1484 | /// |
| 1485 | struct { |
| 1486 | /// |
| 1487 | /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU |
| 1488 | /// hardware detected errors. |
| 1489 | /// |
| 1490 | UINT32 PCUHardwareError:1; |
| 1491 | /// |
| 1492 | /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU |
| 1493 | /// controller detected errors. |
| 1494 | /// |
| 1495 | UINT32 PCUControllerError:1; |
| 1496 | /// |
| 1497 | /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU |
| 1498 | /// firmware detected errors. |
| 1499 | /// |
| 1500 | UINT32 PCUFirmwareError:1; |
| 1501 | UINT32 Reserved1:29; |
| 1502 | UINT32 Reserved2:32; |
| 1503 | } Bits; |
| 1504 | /// |
| 1505 | /// All bit fields as a 32-bit value |
| 1506 | /// |
| 1507 | UINT32 Uint32; |
| 1508 | /// |
| 1509 | /// All bit fields as a 64-bit value |
| 1510 | /// |
| 1511 | UINT64 Uint64; |
| 1512 | } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER; |
| 1513 | |
| 1514 | |
| 1515 | /** |
| 1516 | Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2. |
| 1517 | |
| 1518 | @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C) |
| 1519 | @param EAX Lower 32-bits of MSR value. |
| 1520 | @param EDX Upper 32-bits of MSR value. |
| 1521 | |
| 1522 | <b>Example usage</b> |
| 1523 | @code |
| 1524 | UINT64 Msr; |
| 1525 | |
| 1526 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM); |
| 1527 | @endcode |
| 1528 | @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM. |
| 1529 | **/ |
| 1530 | #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C |
| 1531 | |
| 1532 | |
| 1533 | /** |
| 1534 | Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, |
| 1535 | "RAPL Interfaces.". |
| 1536 | |
| 1537 | @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606) |
| 1538 | @param EAX Lower 32-bits of MSR value. |
| 1539 | @param EDX Upper 32-bits of MSR value. |
| 1540 | |
| 1541 | <b>Example usage</b> |
| 1542 | @code |
| 1543 | UINT64 Msr; |
| 1544 | |
| 1545 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT); |
| 1546 | @endcode |
| 1547 | @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. |
| 1548 | **/ |
| 1549 | #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606 |
| 1550 | |
| 1551 | |
| 1552 | /** |
| 1553 | Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are |
| 1554 | processor specific C-state code names, unrelated to MWAIT extension C-state |
| 1555 | parameters or ACPI CStates. |
| 1556 | |
| 1557 | @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A) |
| 1558 | @param EAX Lower 32-bits of MSR value. |
| 1559 | Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER. |
| 1560 | @param EDX Upper 32-bits of MSR value. |
| 1561 | Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER. |
| 1562 | |
| 1563 | <b>Example usage</b> |
| 1564 | @code |
| 1565 | MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr; |
| 1566 | |
| 1567 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL); |
| 1568 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64); |
| 1569 | @endcode |
| 1570 | @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM. |
| 1571 | **/ |
| 1572 | #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A |
| 1573 | |
| 1574 | /** |
| 1575 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL |
| 1576 | **/ |
| 1577 | typedef union { |
| 1578 | /// |
| 1579 | /// Individual bit fields |
| 1580 | /// |
| 1581 | struct { |
| 1582 | /// |
| 1583 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit |
| 1584 | /// that should be used to decide if the package should be put into a |
| 1585 | /// package C3 state. |
| 1586 | /// |
| 1587 | UINT32 TimeLimit:10; |
| 1588 | /// |
| 1589 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time |
| 1590 | /// unit of the interrupt response time limit. The following time unit |
| 1591 | /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: |
| 1592 | /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. |
| 1593 | /// |
| 1594 | UINT32 TimeUnit:3; |
| 1595 | UINT32 Reserved1:2; |
| 1596 | /// |
| 1597 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are |
| 1598 | /// valid and can be used by the processor for package C-sate management. |
| 1599 | /// |
| 1600 | UINT32 Valid:1; |
| 1601 | UINT32 Reserved2:16; |
| 1602 | UINT32 Reserved3:32; |
| 1603 | } Bits; |
| 1604 | /// |
| 1605 | /// All bit fields as a 32-bit value |
| 1606 | /// |
| 1607 | UINT32 Uint32; |
| 1608 | /// |
| 1609 | /// All bit fields as a 64-bit value |
| 1610 | /// |
| 1611 | UINT64 Uint64; |
| 1612 | } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER; |
| 1613 | |
| 1614 | |
| 1615 | /** |
| 1616 | Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the |
| 1617 | budget allocated for the package to exit from C6 to a C0 state, where |
| 1618 | interrupt request can be delivered to the core and serviced. Additional |
| 1619 | core-exit latency amy be applicable depending on the actual C-state the core |
| 1620 | is in. Note: C-state values are processor specific C-state code names, |
| 1621 | unrelated to MWAIT extension C-state parameters or ACPI CStates. |
| 1622 | |
| 1623 | @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B) |
| 1624 | @param EAX Lower 32-bits of MSR value. |
| 1625 | Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER. |
| 1626 | @param EDX Upper 32-bits of MSR value. |
| 1627 | Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER. |
| 1628 | |
| 1629 | <b>Example usage</b> |
| 1630 | @code |
| 1631 | MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr; |
| 1632 | |
| 1633 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL); |
| 1634 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64); |
| 1635 | @endcode |
| 1636 | @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM. |
| 1637 | **/ |
| 1638 | #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B |
| 1639 | |
| 1640 | /** |
| 1641 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL |
| 1642 | **/ |
| 1643 | typedef union { |
| 1644 | /// |
| 1645 | /// Individual bit fields |
| 1646 | /// |
| 1647 | struct { |
| 1648 | /// |
| 1649 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit |
| 1650 | /// that should be used to decide if the package should be put into a |
| 1651 | /// package C6 state. |
| 1652 | /// |
| 1653 | UINT32 TimeLimit:10; |
| 1654 | /// |
| 1655 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time |
| 1656 | /// unit of the interrupt response time limit. The following time unit |
| 1657 | /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: |
| 1658 | /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. |
| 1659 | /// |
| 1660 | UINT32 TimeUnit:3; |
| 1661 | UINT32 Reserved1:2; |
| 1662 | /// |
| 1663 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are |
| 1664 | /// valid and can be used by the processor for package C-sate management. |
| 1665 | /// |
| 1666 | UINT32 Valid:1; |
| 1667 | UINT32 Reserved2:16; |
| 1668 | UINT32 Reserved3:32; |
| 1669 | } Bits; |
| 1670 | /// |
| 1671 | /// All bit fields as a 32-bit value |
| 1672 | /// |
| 1673 | UINT32 Uint32; |
| 1674 | /// |
| 1675 | /// All bit fields as a 64-bit value |
| 1676 | /// |
| 1677 | UINT64 Uint64; |
| 1678 | } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER; |
| 1679 | |
| 1680 | |
| 1681 | /** |
| 1682 | Package. Note: C-state values are processor specific C-state code names, |
| 1683 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2 |
| 1684 | Residency Counter. (R/O) Value since last reset that this package is in |
| 1685 | processor-specific C2 states. Count at the same frequency as the TSC. |
| 1686 | |
| 1687 | @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D) |
| 1688 | @param EAX Lower 32-bits of MSR value. |
| 1689 | @param EDX Upper 32-bits of MSR value. |
| 1690 | |
| 1691 | <b>Example usage</b> |
| 1692 | @code |
| 1693 | UINT64 Msr; |
| 1694 | |
| 1695 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY); |
| 1696 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr); |
| 1697 | @endcode |
| 1698 | @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. |
| 1699 | **/ |
| 1700 | #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D |
| 1701 | |
| 1702 | |
| 1703 | /** |
| 1704 | Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package |
| 1705 | RAPL Domain.". |
| 1706 | |
| 1707 | @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610) |
| 1708 | @param EAX Lower 32-bits of MSR value. |
| 1709 | @param EDX Upper 32-bits of MSR value. |
| 1710 | |
| 1711 | <b>Example usage</b> |
| 1712 | @code |
| 1713 | UINT64 Msr; |
| 1714 | |
| 1715 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT); |
| 1716 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr); |
| 1717 | @endcode |
| 1718 | @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. |
| 1719 | **/ |
| 1720 | #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610 |
| 1721 | |
| 1722 | |
| 1723 | /** |
| 1724 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.". |
| 1725 | |
| 1726 | @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611) |
| 1727 | @param EAX Lower 32-bits of MSR value. |
| 1728 | @param EDX Upper 32-bits of MSR value. |
| 1729 | |
| 1730 | <b>Example usage</b> |
| 1731 | @code |
| 1732 | UINT64 Msr; |
| 1733 | |
| 1734 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS); |
| 1735 | @endcode |
| 1736 | @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. |
| 1737 | **/ |
| 1738 | #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611 |
| 1739 | |
| 1740 | |
| 1741 | /** |
| 1742 | Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL |
| 1743 | Domain.". |
| 1744 | |
| 1745 | @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614) |
| 1746 | @param EAX Lower 32-bits of MSR value. |
| 1747 | @param EDX Upper 32-bits of MSR value. |
| 1748 | |
| 1749 | <b>Example usage</b> |
| 1750 | @code |
| 1751 | UINT64 Msr; |
| 1752 | |
| 1753 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO); |
| 1754 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr); |
| 1755 | @endcode |
| 1756 | @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. |
| 1757 | **/ |
| 1758 | #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614 |
| 1759 | |
| 1760 | |
| 1761 | /** |
| 1762 | Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 |
| 1763 | RAPL Domains.". |
| 1764 | |
| 1765 | @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638) |
| 1766 | @param EAX Lower 32-bits of MSR value. |
| 1767 | @param EDX Upper 32-bits of MSR value. |
| 1768 | |
| 1769 | <b>Example usage</b> |
| 1770 | @code |
| 1771 | UINT64 Msr; |
| 1772 | |
| 1773 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT); |
| 1774 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr); |
| 1775 | @endcode |
| 1776 | @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM. |
| 1777 | **/ |
| 1778 | #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638 |
| 1779 | |
| 1780 | |
| 1781 | /** |
| 1782 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL |
| 1783 | Domains.". |
| 1784 | |
| 1785 | @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639) |
| 1786 | @param EAX Lower 32-bits of MSR value. |
| 1787 | @param EDX Upper 32-bits of MSR value. |
| 1788 | |
| 1789 | <b>Example usage</b> |
| 1790 | @code |
| 1791 | UINT64 Msr; |
| 1792 | |
| 1793 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS); |
| 1794 | @endcode |
| 1795 | @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. |
| 1796 | **/ |
| 1797 | #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639 |
| 1798 | |
| 1799 | |
| 1800 | /** |
| 1801 | Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last |
| 1802 | branch record registers on the last branch record stack. This part of the |
| 1803 | stack contains pointers to the source instruction. See also: - Last Branch |
| 1804 | Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section |
| 1805 | 17.4.8.1. |
| 1806 | |
| 1807 | @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP |
| 1808 | @param EAX Lower 32-bits of MSR value. |
| 1809 | @param EDX Upper 32-bits of MSR value. |
| 1810 | |
| 1811 | <b>Example usage</b> |
| 1812 | @code |
| 1813 | UINT64 Msr; |
| 1814 | |
| 1815 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP); |
| 1816 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr); |
| 1817 | @endcode |
| 1818 | @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. |
| 1819 | MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. |
| 1820 | MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. |
| 1821 | MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. |
| 1822 | MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. |
| 1823 | MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. |
| 1824 | MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. |
| 1825 | MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. |
| 1826 | MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. |
| 1827 | MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. |
| 1828 | MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. |
| 1829 | MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. |
| 1830 | MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. |
| 1831 | MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. |
| 1832 | MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. |
| 1833 | MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. |
| 1834 | @{ |
| 1835 | **/ |
| 1836 | #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680 |
| 1837 | #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681 |
| 1838 | #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682 |
| 1839 | #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683 |
| 1840 | #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684 |
| 1841 | #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685 |
| 1842 | #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686 |
| 1843 | #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687 |
| 1844 | #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688 |
| 1845 | #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689 |
| 1846 | #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A |
| 1847 | #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B |
| 1848 | #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C |
| 1849 | #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D |
| 1850 | #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E |
| 1851 | #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F |
| 1852 | /// @} |
| 1853 | |
| 1854 | |
| 1855 | /** |
| 1856 | Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch |
| 1857 | record registers on the last branch record stack. This part of the stack |
| 1858 | contains pointers to the destination instruction. |
| 1859 | |
| 1860 | @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP |
| 1861 | @param EAX Lower 32-bits of MSR value. |
| 1862 | @param EDX Upper 32-bits of MSR value. |
| 1863 | |
| 1864 | <b>Example usage</b> |
| 1865 | @code |
| 1866 | UINT64 Msr; |
| 1867 | |
| 1868 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP); |
| 1869 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr); |
| 1870 | @endcode |
| 1871 | @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. |
| 1872 | MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. |
| 1873 | MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. |
| 1874 | MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. |
| 1875 | MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. |
| 1876 | MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. |
| 1877 | MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. |
| 1878 | MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. |
| 1879 | MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. |
| 1880 | MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. |
| 1881 | MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. |
| 1882 | MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. |
| 1883 | MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. |
| 1884 | MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. |
| 1885 | MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. |
| 1886 | MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. |
| 1887 | @{ |
| 1888 | **/ |
| 1889 | #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0 |
| 1890 | #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1 |
| 1891 | #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2 |
| 1892 | #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3 |
| 1893 | #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4 |
| 1894 | #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5 |
| 1895 | #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6 |
| 1896 | #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7 |
| 1897 | #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8 |
| 1898 | #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9 |
| 1899 | #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA |
| 1900 | #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB |
| 1901 | #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC |
| 1902 | #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD |
| 1903 | #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE |
| 1904 | #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF |
| 1905 | /// @} |
| 1906 | |
| 1907 | |
| 1908 | /** |
| 1909 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, |
| 1910 | RW if MSR_PLATFORM_INFO.[28] = 1. |
| 1911 | |
| 1912 | @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD) |
| 1913 | @param EAX Lower 32-bits of MSR value. |
| 1914 | Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER. |
| 1915 | @param EDX Upper 32-bits of MSR value. |
| 1916 | Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER. |
| 1917 | |
| 1918 | <b>Example usage</b> |
| 1919 | @code |
| 1920 | MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr; |
| 1921 | |
| 1922 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT); |
| 1923 | @endcode |
| 1924 | @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. |
| 1925 | **/ |
| 1926 | #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD |
| 1927 | |
| 1928 | /** |
| 1929 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT |
| 1930 | **/ |
| 1931 | typedef union { |
| 1932 | /// |
| 1933 | /// Individual bit fields |
| 1934 | /// |
| 1935 | struct { |
| 1936 | /// |
| 1937 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio |
| 1938 | /// limit of 1 core active. |
| 1939 | /// |
| 1940 | UINT32 Maximum1C:8; |
| 1941 | /// |
| 1942 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio |
| 1943 | /// limit of 2 core active. |
| 1944 | /// |
| 1945 | UINT32 Maximum2C:8; |
| 1946 | /// |
| 1947 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio |
| 1948 | /// limit of 3 core active. |
| 1949 | /// |
| 1950 | UINT32 Maximum3C:8; |
| 1951 | /// |
| 1952 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio |
| 1953 | /// limit of 4 core active. |
| 1954 | /// |
| 1955 | UINT32 Maximum4C:8; |
| 1956 | /// |
| 1957 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio |
| 1958 | /// limit of 5 core active. |
| 1959 | /// |
| 1960 | UINT32 Maximum5C:8; |
| 1961 | /// |
| 1962 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio |
| 1963 | /// limit of 6 core active. |
| 1964 | /// |
| 1965 | UINT32 Maximum6C:8; |
| 1966 | /// |
| 1967 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio |
| 1968 | /// limit of 7 core active. |
| 1969 | /// |
| 1970 | UINT32 Maximum7C:8; |
| 1971 | /// |
| 1972 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio |
| 1973 | /// limit of 8 core active. |
| 1974 | /// |
| 1975 | UINT32 Maximum8C:8; |
| 1976 | } Bits; |
| 1977 | /// |
| 1978 | /// All bit fields as a 64-bit value |
| 1979 | /// |
| 1980 | UINT64 Uint64; |
| 1981 | } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER; |
| 1982 | |
| 1983 | |
| 1984 | /** |
| 1985 | Package. Uncore PMU global control. |
| 1986 | |
| 1987 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391) |
| 1988 | @param EAX Lower 32-bits of MSR value. |
| 1989 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER. |
| 1990 | @param EDX Upper 32-bits of MSR value. |
| 1991 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER. |
| 1992 | |
| 1993 | <b>Example usage</b> |
| 1994 | @code |
| 1995 | MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; |
| 1996 | |
| 1997 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL); |
| 1998 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); |
| 1999 | @endcode |
| 2000 | @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. |
| 2001 | **/ |
| 2002 | #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391 |
| 2003 | |
| 2004 | /** |
| 2005 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL |
| 2006 | **/ |
| 2007 | typedef union { |
| 2008 | /// |
| 2009 | /// Individual bit fields |
| 2010 | /// |
| 2011 | struct { |
| 2012 | /// |
| 2013 | /// [Bit 0] Slice 0 select. |
| 2014 | /// |
| 2015 | UINT32 PMI_Sel_Slice0:1; |
| 2016 | /// |
| 2017 | /// [Bit 1] Slice 1 select. |
| 2018 | /// |
| 2019 | UINT32 PMI_Sel_Slice1:1; |
| 2020 | /// |
| 2021 | /// [Bit 2] Slice 2 select. |
| 2022 | /// |
| 2023 | UINT32 PMI_Sel_Slice2:1; |
| 2024 | /// |
| 2025 | /// [Bit 3] Slice 3 select. |
| 2026 | /// |
| 2027 | UINT32 PMI_Sel_Slice3:1; |
| 2028 | /// |
| 2029 | /// [Bit 4] Slice 4 select. |
| 2030 | /// |
| 2031 | UINT32 PMI_Sel_Slice4:1; |
| 2032 | UINT32 Reserved1:14; |
| 2033 | UINT32 Reserved2:10; |
| 2034 | /// |
| 2035 | /// [Bit 29] Enable all uncore counters. |
| 2036 | /// |
| 2037 | UINT32 EN:1; |
| 2038 | /// |
| 2039 | /// [Bit 30] Enable wake on PMI. |
| 2040 | /// |
| 2041 | UINT32 WakePMI:1; |
| 2042 | /// |
| 2043 | /// [Bit 31] Enable Freezing counter when overflow. |
| 2044 | /// |
| 2045 | UINT32 FREEZE:1; |
| 2046 | UINT32 Reserved3:32; |
| 2047 | } Bits; |
| 2048 | /// |
| 2049 | /// All bit fields as a 32-bit value |
| 2050 | /// |
| 2051 | UINT32 Uint32; |
| 2052 | /// |
| 2053 | /// All bit fields as a 64-bit value |
| 2054 | /// |
| 2055 | UINT64 Uint64; |
| 2056 | } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER; |
| 2057 | |
| 2058 | |
| 2059 | /** |
| 2060 | Package. Uncore PMU main status. |
| 2061 | |
| 2062 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392) |
| 2063 | @param EAX Lower 32-bits of MSR value. |
| 2064 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER. |
| 2065 | @param EDX Upper 32-bits of MSR value. |
| 2066 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER. |
| 2067 | |
| 2068 | <b>Example usage</b> |
| 2069 | @code |
| 2070 | MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; |
| 2071 | |
| 2072 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS); |
| 2073 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); |
| 2074 | @endcode |
| 2075 | @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. |
| 2076 | **/ |
| 2077 | #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392 |
| 2078 | |
| 2079 | /** |
| 2080 | MSR information returned for MSR index |
| 2081 | #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS |
| 2082 | **/ |
| 2083 | typedef union { |
| 2084 | /// |
| 2085 | /// Individual bit fields |
| 2086 | /// |
| 2087 | struct { |
| 2088 | /// |
| 2089 | /// [Bit 0] Fixed counter overflowed. |
| 2090 | /// |
| 2091 | UINT32 Fixed:1; |
| 2092 | /// |
| 2093 | /// [Bit 1] An ARB counter overflowed. |
| 2094 | /// |
| 2095 | UINT32 ARB:1; |
| 2096 | UINT32 Reserved1:1; |
| 2097 | /// |
| 2098 | /// [Bit 3] A CBox counter overflowed (on any slice). |
| 2099 | /// |
| 2100 | UINT32 CBox:1; |
| 2101 | UINT32 Reserved2:28; |
| 2102 | UINT32 Reserved3:32; |
| 2103 | } Bits; |
| 2104 | /// |
| 2105 | /// All bit fields as a 32-bit value |
| 2106 | /// |
| 2107 | UINT32 Uint32; |
| 2108 | /// |
| 2109 | /// All bit fields as a 64-bit value |
| 2110 | /// |
| 2111 | UINT64 Uint64; |
| 2112 | } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER; |
| 2113 | |
| 2114 | |
| 2115 | /** |
| 2116 | Package. Uncore fixed counter control (R/W). |
| 2117 | |
| 2118 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394) |
| 2119 | @param EAX Lower 32-bits of MSR value. |
| 2120 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER. |
| 2121 | @param EDX Upper 32-bits of MSR value. |
| 2122 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER. |
| 2123 | |
| 2124 | <b>Example usage</b> |
| 2125 | @code |
| 2126 | MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr; |
| 2127 | |
| 2128 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL); |
| 2129 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64); |
| 2130 | @endcode |
| 2131 | @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. |
| 2132 | **/ |
| 2133 | #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394 |
| 2134 | |
| 2135 | /** |
| 2136 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL |
| 2137 | **/ |
| 2138 | typedef union { |
| 2139 | /// |
| 2140 | /// Individual bit fields |
| 2141 | /// |
| 2142 | struct { |
| 2143 | UINT32 Reserved1:20; |
| 2144 | /// |
| 2145 | /// [Bit 20] Enable overflow propagation. |
| 2146 | /// |
| 2147 | UINT32 EnableOverflow:1; |
| 2148 | UINT32 Reserved2:1; |
| 2149 | /// |
| 2150 | /// [Bit 22] Enable counting. |
| 2151 | /// |
| 2152 | UINT32 EnableCounting:1; |
| 2153 | UINT32 Reserved3:9; |
| 2154 | UINT32 Reserved4:32; |
| 2155 | } Bits; |
| 2156 | /// |
| 2157 | /// All bit fields as a 32-bit value |
| 2158 | /// |
| 2159 | UINT32 Uint32; |
| 2160 | /// |
| 2161 | /// All bit fields as a 64-bit value |
| 2162 | /// |
| 2163 | UINT64 Uint64; |
| 2164 | } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER; |
| 2165 | |
| 2166 | |
| 2167 | /** |
| 2168 | Package. Uncore fixed counter. |
| 2169 | |
| 2170 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395) |
| 2171 | @param EAX Lower 32-bits of MSR value. |
| 2172 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER. |
| 2173 | @param EDX Upper 32-bits of MSR value. |
| 2174 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER. |
| 2175 | |
| 2176 | <b>Example usage</b> |
| 2177 | @code |
| 2178 | MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr; |
| 2179 | |
| 2180 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR); |
| 2181 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64); |
| 2182 | @endcode |
| 2183 | @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. |
| 2184 | **/ |
| 2185 | #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395 |
| 2186 | |
| 2187 | /** |
| 2188 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR |
| 2189 | **/ |
| 2190 | typedef union { |
| 2191 | /// |
| 2192 | /// Individual bit fields |
| 2193 | /// |
| 2194 | struct { |
| 2195 | /// |
| 2196 | /// [Bits 31:0] Current count. |
| 2197 | /// |
| 2198 | UINT32 CurrentCount:32; |
| 2199 | /// |
| 2200 | /// [Bits 47:32] Current count. |
| 2201 | /// |
| 2202 | UINT32 CurrentCountHi:16; |
| 2203 | UINT32 Reserved:16; |
| 2204 | } Bits; |
| 2205 | /// |
| 2206 | /// All bit fields as a 64-bit value |
| 2207 | /// |
| 2208 | UINT64 Uint64; |
| 2209 | } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER; |
| 2210 | |
| 2211 | |
| 2212 | /** |
| 2213 | Package. Uncore C-Box configuration information (R/O). |
| 2214 | |
| 2215 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396) |
| 2216 | @param EAX Lower 32-bits of MSR value. |
| 2217 | Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER. |
| 2218 | @param EDX Upper 32-bits of MSR value. |
| 2219 | Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER. |
| 2220 | |
| 2221 | <b>Example usage</b> |
| 2222 | @code |
| 2223 | MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr; |
| 2224 | |
| 2225 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG); |
| 2226 | @endcode |
| 2227 | @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. |
| 2228 | **/ |
| 2229 | #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396 |
| 2230 | |
| 2231 | /** |
| 2232 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG |
| 2233 | **/ |
| 2234 | typedef union { |
| 2235 | /// |
| 2236 | /// Individual bit fields |
| 2237 | /// |
| 2238 | struct { |
| 2239 | /// |
| 2240 | /// [Bits 3:0] Report the number of C-Box units with performance counters, |
| 2241 | /// including processor cores and processor graphics". |
| 2242 | /// |
| 2243 | UINT32 CBox:4; |
| 2244 | UINT32 Reserved1:28; |
| 2245 | UINT32 Reserved2:32; |
| 2246 | } Bits; |
| 2247 | /// |
| 2248 | /// All bit fields as a 32-bit value |
| 2249 | /// |
| 2250 | UINT32 Uint32; |
| 2251 | /// |
| 2252 | /// All bit fields as a 64-bit value |
| 2253 | /// |
| 2254 | UINT64 Uint64; |
| 2255 | } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER; |
| 2256 | |
| 2257 | |
| 2258 | /** |
| 2259 | Package. Uncore Arb unit, performance counter 0. |
| 2260 | |
| 2261 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0) |
| 2262 | @param EAX Lower 32-bits of MSR value. |
| 2263 | @param EDX Upper 32-bits of MSR value. |
| 2264 | |
| 2265 | <b>Example usage</b> |
| 2266 | @code |
| 2267 | UINT64 Msr; |
| 2268 | |
| 2269 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0); |
| 2270 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr); |
| 2271 | @endcode |
| 2272 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. |
| 2273 | **/ |
| 2274 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0 |
| 2275 | |
| 2276 | |
| 2277 | /** |
| 2278 | Package. Uncore Arb unit, performance counter 1. |
| 2279 | |
| 2280 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1) |
| 2281 | @param EAX Lower 32-bits of MSR value. |
| 2282 | @param EDX Upper 32-bits of MSR value. |
| 2283 | |
| 2284 | <b>Example usage</b> |
| 2285 | @code |
| 2286 | UINT64 Msr; |
| 2287 | |
| 2288 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1); |
| 2289 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr); |
| 2290 | @endcode |
| 2291 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. |
| 2292 | **/ |
| 2293 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1 |
| 2294 | |
| 2295 | |
| 2296 | /** |
| 2297 | Package. Uncore Arb unit, counter 0 event select MSR. |
| 2298 | |
| 2299 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2) |
| 2300 | @param EAX Lower 32-bits of MSR value. |
| 2301 | @param EDX Upper 32-bits of MSR value. |
| 2302 | |
| 2303 | <b>Example usage</b> |
| 2304 | @code |
| 2305 | UINT64 Msr; |
| 2306 | |
| 2307 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0); |
| 2308 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr); |
| 2309 | @endcode |
| 2310 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. |
| 2311 | **/ |
| 2312 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2 |
| 2313 | |
| 2314 | |
| 2315 | /** |
| 2316 | Package. Uncore Arb unit, counter 1 event select MSR. |
| 2317 | |
| 2318 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3) |
| 2319 | @param EAX Lower 32-bits of MSR value. |
| 2320 | @param EDX Upper 32-bits of MSR value. |
| 2321 | |
| 2322 | <b>Example usage</b> |
| 2323 | @code |
| 2324 | UINT64 Msr; |
| 2325 | |
| 2326 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1); |
| 2327 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr); |
| 2328 | @endcode |
| 2329 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM. |
| 2330 | **/ |
| 2331 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3 |
| 2332 | |
| 2333 | |
| 2334 | /** |
| 2335 | Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the |
| 2336 | budget allocated for the package to exit from C7 to a C0 state, where |
| 2337 | interrupt request can be delivered to the core and serviced. Additional |
| 2338 | core-exit latency amy be applicable depending on the actual C-state the core |
| 2339 | is in. Note: C-state values are processor specific C-state code names, |
| 2340 | unrelated to MWAIT extension C-state parameters or ACPI CStates. |
| 2341 | |
| 2342 | @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C) |
| 2343 | @param EAX Lower 32-bits of MSR value. |
| 2344 | Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER. |
| 2345 | @param EDX Upper 32-bits of MSR value. |
| 2346 | Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER. |
| 2347 | |
| 2348 | <b>Example usage</b> |
| 2349 | @code |
| 2350 | MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr; |
| 2351 | |
| 2352 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL); |
| 2353 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64); |
| 2354 | @endcode |
| 2355 | @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM. |
| 2356 | **/ |
| 2357 | #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C |
| 2358 | |
| 2359 | /** |
| 2360 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL |
| 2361 | **/ |
| 2362 | typedef union { |
| 2363 | /// |
| 2364 | /// Individual bit fields |
| 2365 | /// |
| 2366 | struct { |
| 2367 | /// |
| 2368 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit |
| 2369 | /// that should be used to decide if the package should be put into a |
| 2370 | /// package C7 state. |
| 2371 | /// |
| 2372 | UINT32 TimeLimit:10; |
| 2373 | /// |
| 2374 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time |
| 2375 | /// unit of the interrupt response time limit. The following time unit |
| 2376 | /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: |
| 2377 | /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. |
| 2378 | /// |
| 2379 | UINT32 TimeUnit:3; |
| 2380 | UINT32 Reserved1:2; |
| 2381 | /// |
| 2382 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are |
| 2383 | /// valid and can be used by the processor for package C-sate management. |
| 2384 | /// |
| 2385 | UINT32 Valid:1; |
| 2386 | UINT32 Reserved2:16; |
| 2387 | UINT32 Reserved3:32; |
| 2388 | } Bits; |
| 2389 | /// |
| 2390 | /// All bit fields as a 32-bit value |
| 2391 | /// |
| 2392 | UINT32 Uint32; |
| 2393 | /// |
| 2394 | /// All bit fields as a 64-bit value |
| 2395 | /// |
| 2396 | UINT64 Uint64; |
| 2397 | } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER; |
| 2398 | |
| 2399 | |
| 2400 | /** |
| 2401 | Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL |
| 2402 | Domains.". |
| 2403 | |
| 2404 | @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A) |
| 2405 | @param EAX Lower 32-bits of MSR value. |
| 2406 | @param EDX Upper 32-bits of MSR value. |
| 2407 | |
| 2408 | <b>Example usage</b> |
| 2409 | @code |
| 2410 | UINT64 Msr; |
| 2411 | |
| 2412 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY); |
| 2413 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr); |
| 2414 | @endcode |
| 2415 | @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM. |
| 2416 | **/ |
| 2417 | #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A |
| 2418 | |
| 2419 | |
| 2420 | /** |
| 2421 | Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 |
| 2422 | RAPL Domains.". |
| 2423 | |
| 2424 | @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640) |
| 2425 | @param EAX Lower 32-bits of MSR value. |
| 2426 | @param EDX Upper 32-bits of MSR value. |
| 2427 | |
| 2428 | <b>Example usage</b> |
| 2429 | @code |
| 2430 | UINT64 Msr; |
| 2431 | |
| 2432 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT); |
| 2433 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr); |
| 2434 | @endcode |
| 2435 | @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM. |
| 2436 | **/ |
| 2437 | #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640 |
| 2438 | |
| 2439 | |
| 2440 | /** |
| 2441 | Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL |
| 2442 | Domains.". |
| 2443 | |
| 2444 | @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641) |
| 2445 | @param EAX Lower 32-bits of MSR value. |
| 2446 | @param EDX Upper 32-bits of MSR value. |
| 2447 | |
| 2448 | <b>Example usage</b> |
| 2449 | @code |
| 2450 | UINT64 Msr; |
| 2451 | |
| 2452 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS); |
| 2453 | @endcode |
| 2454 | @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. |
| 2455 | **/ |
| 2456 | #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641 |
| 2457 | |
| 2458 | |
| 2459 | /** |
| 2460 | Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL |
| 2461 | Domains.". |
| 2462 | |
| 2463 | @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642) |
| 2464 | @param EAX Lower 32-bits of MSR value. |
| 2465 | @param EDX Upper 32-bits of MSR value. |
| 2466 | |
| 2467 | <b>Example usage</b> |
| 2468 | @code |
| 2469 | UINT64 Msr; |
| 2470 | |
| 2471 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY); |
| 2472 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr); |
| 2473 | @endcode |
| 2474 | @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM. |
| 2475 | **/ |
| 2476 | #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642 |
| 2477 | |
| 2478 | |
| 2479 | /** |
| 2480 | Package. Uncore C-Box 0, counter n event select MSR. |
| 2481 | |
| 2482 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn |
| 2483 | @param EAX Lower 32-bits of MSR value. |
| 2484 | @param EDX Upper 32-bits of MSR value. |
| 2485 | |
| 2486 | <b>Example usage</b> |
| 2487 | @code |
| 2488 | UINT64 Msr; |
| 2489 | |
| 2490 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0); |
| 2491 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr); |
| 2492 | @endcode |
| 2493 | @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. |
| 2494 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. |
| 2495 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM. |
| 2496 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM. |
| 2497 | @{ |
| 2498 | **/ |
| 2499 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700 |
| 2500 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701 |
| 2501 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702 |
| 2502 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703 |
| 2503 | /// @} |
| 2504 | |
| 2505 | |
| 2506 | /** |
| 2507 | Package. Uncore C-Box n, unit status for counter 0-3. |
| 2508 | |
| 2509 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS |
| 2510 | @param EAX Lower 32-bits of MSR value. |
| 2511 | @param EDX Upper 32-bits of MSR value. |
| 2512 | |
| 2513 | <b>Example usage</b> |
| 2514 | @code |
| 2515 | UINT64 Msr; |
| 2516 | |
| 2517 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS); |
| 2518 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr); |
| 2519 | @endcode |
| 2520 | @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM. |
| 2521 | MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM. |
| 2522 | MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM. |
| 2523 | MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM. |
| 2524 | MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM. |
| 2525 | @{ |
| 2526 | **/ |
| 2527 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705 |
| 2528 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715 |
| 2529 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725 |
| 2530 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735 |
| 2531 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745 |
| 2532 | /// @} |
| 2533 | |
| 2534 | |
| 2535 | /** |
| 2536 | Package. Uncore C-Box 0, performance counter n. |
| 2537 | |
| 2538 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn |
| 2539 | @param EAX Lower 32-bits of MSR value. |
| 2540 | @param EDX Upper 32-bits of MSR value. |
| 2541 | |
| 2542 | <b>Example usage</b> |
| 2543 | @code |
| 2544 | UINT64 Msr; |
| 2545 | |
| 2546 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0); |
| 2547 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr); |
| 2548 | @endcode |
| 2549 | @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. |
| 2550 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. |
| 2551 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM. |
| 2552 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM. |
| 2553 | @{ |
| 2554 | **/ |
| 2555 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706 |
| 2556 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707 |
| 2557 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708 |
| 2558 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709 |
| 2559 | /// @} |
| 2560 | |
| 2561 | |
| 2562 | /** |
| 2563 | Package. Uncore C-Box 1, counter n event select MSR. |
| 2564 | |
| 2565 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn |
| 2566 | @param EAX Lower 32-bits of MSR value. |
| 2567 | @param EDX Upper 32-bits of MSR value. |
| 2568 | |
| 2569 | <b>Example usage</b> |
| 2570 | @code |
| 2571 | UINT64 Msr; |
| 2572 | |
| 2573 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0); |
| 2574 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr); |
| 2575 | @endcode |
| 2576 | @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. |
| 2577 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. |
| 2578 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM. |
| 2579 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM. |
| 2580 | @{ |
| 2581 | **/ |
| 2582 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710 |
| 2583 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711 |
| 2584 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712 |
| 2585 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713 |
| 2586 | /// @} |
| 2587 | |
| 2588 | |
| 2589 | /** |
| 2590 | Package. Uncore C-Box 1, performance counter n. |
| 2591 | |
| 2592 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn |
| 2593 | @param EAX Lower 32-bits of MSR value. |
| 2594 | @param EDX Upper 32-bits of MSR value. |
| 2595 | |
| 2596 | <b>Example usage</b> |
| 2597 | @code |
| 2598 | UINT64 Msr; |
| 2599 | |
| 2600 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0); |
| 2601 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr); |
| 2602 | @endcode |
| 2603 | @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. |
| 2604 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. |
| 2605 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM. |
| 2606 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM. |
| 2607 | @{ |
| 2608 | **/ |
| 2609 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716 |
| 2610 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717 |
| 2611 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718 |
| 2612 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719 |
| 2613 | /// @} |
| 2614 | |
| 2615 | |
| 2616 | /** |
| 2617 | Package. Uncore C-Box 2, counter n event select MSR. |
| 2618 | |
| 2619 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn |
| 2620 | @param EAX Lower 32-bits of MSR value. |
| 2621 | @param EDX Upper 32-bits of MSR value. |
| 2622 | |
| 2623 | <b>Example usage</b> |
| 2624 | @code |
| 2625 | UINT64 Msr; |
| 2626 | |
| 2627 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0); |
| 2628 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr); |
| 2629 | @endcode |
| 2630 | @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. |
| 2631 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. |
| 2632 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM. |
| 2633 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM. |
| 2634 | @{ |
| 2635 | **/ |
| 2636 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720 |
| 2637 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721 |
| 2638 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722 |
| 2639 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723 |
| 2640 | /// @} |
| 2641 | |
| 2642 | |
| 2643 | /** |
| 2644 | Package. Uncore C-Box 2, performance counter n. |
| 2645 | |
| 2646 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn |
| 2647 | @param EAX Lower 32-bits of MSR value. |
| 2648 | @param EDX Upper 32-bits of MSR value. |
| 2649 | |
| 2650 | <b>Example usage</b> |
| 2651 | @code |
| 2652 | UINT64 Msr; |
| 2653 | |
| 2654 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0); |
| 2655 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr); |
| 2656 | @endcode |
| 2657 | @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. |
| 2658 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. |
| 2659 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM. |
| 2660 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM. |
| 2661 | @{ |
| 2662 | **/ |
| 2663 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726 |
| 2664 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727 |
| 2665 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728 |
| 2666 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729 |
| 2667 | /// @} |
| 2668 | |
| 2669 | |
| 2670 | /** |
| 2671 | Package. Uncore C-Box 3, counter n event select MSR. |
| 2672 | |
| 2673 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn |
| 2674 | @param EAX Lower 32-bits of MSR value. |
| 2675 | @param EDX Upper 32-bits of MSR value. |
| 2676 | |
| 2677 | <b>Example usage</b> |
| 2678 | @code |
| 2679 | UINT64 Msr; |
| 2680 | |
| 2681 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0); |
| 2682 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr); |
| 2683 | @endcode |
| 2684 | @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. |
| 2685 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. |
| 2686 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM. |
| 2687 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM. |
| 2688 | @{ |
| 2689 | **/ |
| 2690 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730 |
| 2691 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731 |
| 2692 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732 |
| 2693 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733 |
| 2694 | /// @} |
| 2695 | |
| 2696 | |
| 2697 | /** |
| 2698 | Package. Uncore C-Box 3, performance counter n. |
| 2699 | |
| 2700 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn |
| 2701 | @param EAX Lower 32-bits of MSR value. |
| 2702 | @param EDX Upper 32-bits of MSR value. |
| 2703 | |
| 2704 | <b>Example usage</b> |
| 2705 | @code |
| 2706 | UINT64 Msr; |
| 2707 | |
| 2708 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0); |
| 2709 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr); |
| 2710 | @endcode |
| 2711 | @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. |
| 2712 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. |
| 2713 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM. |
| 2714 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM. |
| 2715 | @{ |
| 2716 | **/ |
| 2717 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736 |
| 2718 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737 |
| 2719 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738 |
| 2720 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739 |
| 2721 | /// @} |
| 2722 | |
| 2723 | |
| 2724 | /** |
| 2725 | Package. Uncore C-Box 4, counter n event select MSR. |
| 2726 | |
| 2727 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn |
| 2728 | @param EAX Lower 32-bits of MSR value. |
| 2729 | @param EDX Upper 32-bits of MSR value. |
| 2730 | |
| 2731 | <b>Example usage</b> |
| 2732 | @code |
| 2733 | UINT64 Msr; |
| 2734 | |
| 2735 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0); |
| 2736 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr); |
| 2737 | @endcode |
| 2738 | @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM. |
| 2739 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM. |
| 2740 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM. |
| 2741 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM. |
| 2742 | @{ |
| 2743 | **/ |
| 2744 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740 |
| 2745 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741 |
| 2746 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742 |
| 2747 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743 |
| 2748 | /// @} |
| 2749 | |
| 2750 | |
| 2751 | /** |
| 2752 | Package. Uncore C-Box 4, performance counter n. |
| 2753 | |
| 2754 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn |
| 2755 | @param EAX Lower 32-bits of MSR value. |
| 2756 | @param EDX Upper 32-bits of MSR value. |
| 2757 | |
| 2758 | <b>Example usage</b> |
| 2759 | @code |
| 2760 | UINT64 Msr; |
| 2761 | |
| 2762 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0); |
| 2763 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr); |
| 2764 | @endcode |
| 2765 | @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM. |
| 2766 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM. |
| 2767 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM. |
| 2768 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM. |
| 2769 | @{ |
| 2770 | **/ |
| 2771 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746 |
| 2772 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747 |
| 2773 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748 |
| 2774 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749 |
| 2775 | /// @} |
| 2776 | |
| 2777 | |
| 2778 | /** |
| 2779 | Package. MC Bank Error Configuration (R/W). |
| 2780 | |
| 2781 | @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F) |
| 2782 | @param EAX Lower 32-bits of MSR value. |
| 2783 | Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER. |
| 2784 | @param EDX Upper 32-bits of MSR value. |
| 2785 | Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER. |
| 2786 | |
| 2787 | <b>Example usage</b> |
| 2788 | @code |
| 2789 | MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr; |
| 2790 | |
| 2791 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL); |
| 2792 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64); |
| 2793 | @endcode |
| 2794 | @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. |
| 2795 | **/ |
| 2796 | #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F |
| 2797 | |
| 2798 | /** |
| 2799 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL |
| 2800 | **/ |
| 2801 | typedef union { |
| 2802 | /// |
| 2803 | /// Individual bit fields |
| 2804 | /// |
| 2805 | struct { |
| 2806 | UINT32 Reserved1:1; |
| 2807 | /// |
| 2808 | /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank |
| 2809 | /// to log additional info in bits 36:32. |
| 2810 | /// |
| 2811 | UINT32 MemErrorLogEnable:1; |
| 2812 | UINT32 Reserved2:30; |
| 2813 | UINT32 Reserved3:32; |
| 2814 | } Bits; |
| 2815 | /// |
| 2816 | /// All bit fields as a 32-bit value |
| 2817 | /// |
| 2818 | UINT32 Uint32; |
| 2819 | /// |
| 2820 | /// All bit fields as a 64-bit value |
| 2821 | /// |
| 2822 | UINT64 Uint64; |
| 2823 | } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER; |
| 2824 | |
| 2825 | |
| 2826 | /** |
| 2827 | Package. |
| 2828 | |
| 2829 | @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C) |
| 2830 | @param EAX Lower 32-bits of MSR value. |
| 2831 | Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER. |
| 2832 | @param EDX Upper 32-bits of MSR value. |
| 2833 | Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER. |
| 2834 | |
| 2835 | <b>Example usage</b> |
| 2836 | @code |
| 2837 | MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr; |
| 2838 | |
| 2839 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT); |
| 2840 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64); |
| 2841 | @endcode |
| 2842 | @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM. |
| 2843 | **/ |
| 2844 | #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C |
| 2845 | |
| 2846 | /** |
| 2847 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT |
| 2848 | **/ |
| 2849 | typedef union { |
| 2850 | /// |
| 2851 | /// Individual bit fields |
| 2852 | /// |
| 2853 | struct { |
| 2854 | /// |
| 2855 | /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS |
| 2856 | /// counting logic for specific events requiring additional configuration, |
| 2857 | /// see Table 19-17. |
| 2858 | /// |
| 2859 | UINT32 ENABLE_PEBS_NUM_ALT:1; |
| 2860 | UINT32 Reserved1:31; |
| 2861 | UINT32 Reserved2:32; |
| 2862 | } Bits; |
| 2863 | /// |
| 2864 | /// All bit fields as a 32-bit value |
| 2865 | /// |
| 2866 | UINT32 Uint32; |
| 2867 | /// |
| 2868 | /// All bit fields as a 64-bit value |
| 2869 | /// |
| 2870 | UINT64 Uint64; |
| 2871 | } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER; |
| 2872 | |
| 2873 | |
| 2874 | /** |
| 2875 | Package. Package RAPL Perf Status (R/O). |
| 2876 | |
| 2877 | @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613) |
| 2878 | @param EAX Lower 32-bits of MSR value. |
| 2879 | @param EDX Upper 32-bits of MSR value. |
| 2880 | |
| 2881 | <b>Example usage</b> |
| 2882 | @code |
| 2883 | UINT64 Msr; |
| 2884 | |
| 2885 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS); |
| 2886 | @endcode |
| 2887 | @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. |
| 2888 | **/ |
| 2889 | #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613 |
| 2890 | |
| 2891 | |
| 2892 | /** |
| 2893 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL |
| 2894 | Domain.". |
| 2895 | |
| 2896 | @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618) |
| 2897 | @param EAX Lower 32-bits of MSR value. |
| 2898 | @param EDX Upper 32-bits of MSR value. |
| 2899 | |
| 2900 | <b>Example usage</b> |
| 2901 | @code |
| 2902 | UINT64 Msr; |
| 2903 | |
| 2904 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT); |
| 2905 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr); |
| 2906 | @endcode |
| 2907 | @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. |
| 2908 | **/ |
| 2909 | #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618 |
| 2910 | |
| 2911 | |
| 2912 | /** |
| 2913 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". |
| 2914 | |
| 2915 | @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619) |
| 2916 | @param EAX Lower 32-bits of MSR value. |
| 2917 | @param EDX Upper 32-bits of MSR value. |
| 2918 | |
| 2919 | <b>Example usage</b> |
| 2920 | @code |
| 2921 | UINT64 Msr; |
| 2922 | |
| 2923 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS); |
| 2924 | @endcode |
| 2925 | @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. |
| 2926 | **/ |
| 2927 | #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619 |
| 2928 | |
| 2929 | |
| 2930 | /** |
| 2931 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM |
| 2932 | RAPL Domain.". |
| 2933 | |
| 2934 | @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B) |
| 2935 | @param EAX Lower 32-bits of MSR value. |
| 2936 | @param EDX Upper 32-bits of MSR value. |
| 2937 | |
| 2938 | <b>Example usage</b> |
| 2939 | @code |
| 2940 | UINT64 Msr; |
| 2941 | |
| 2942 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS); |
| 2943 | @endcode |
| 2944 | @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. |
| 2945 | **/ |
| 2946 | #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B |
| 2947 | |
| 2948 | |
| 2949 | /** |
| 2950 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". |
| 2951 | |
| 2952 | @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C) |
| 2953 | @param EAX Lower 32-bits of MSR value. |
| 2954 | @param EDX Upper 32-bits of MSR value. |
| 2955 | |
| 2956 | <b>Example usage</b> |
| 2957 | @code |
| 2958 | UINT64 Msr; |
| 2959 | |
| 2960 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO); |
| 2961 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr); |
| 2962 | @endcode |
| 2963 | @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. |
| 2964 | **/ |
| 2965 | #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C |
| 2966 | |
| 2967 | |
| 2968 | /** |
| 2969 | Package. Uncore U-box UCLK fixed counter control. |
| 2970 | |
| 2971 | @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08) |
| 2972 | @param EAX Lower 32-bits of MSR value. |
| 2973 | @param EDX Upper 32-bits of MSR value. |
| 2974 | |
| 2975 | <b>Example usage</b> |
| 2976 | @code |
| 2977 | UINT64 Msr; |
| 2978 | |
| 2979 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL); |
| 2980 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr); |
| 2981 | @endcode |
| 2982 | @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM. |
| 2983 | **/ |
| 2984 | #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08 |
| 2985 | |
| 2986 | |
| 2987 | /** |
| 2988 | Package. Uncore U-box UCLK fixed counter. |
| 2989 | |
| 2990 | @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09) |
| 2991 | @param EAX Lower 32-bits of MSR value. |
| 2992 | @param EDX Upper 32-bits of MSR value. |
| 2993 | |
| 2994 | <b>Example usage</b> |
| 2995 | @code |
| 2996 | UINT64 Msr; |
| 2997 | |
| 2998 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR); |
| 2999 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr); |
| 3000 | @endcode |
| 3001 | @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM. |
| 3002 | **/ |
| 3003 | #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09 |
| 3004 | |
| 3005 | |
| 3006 | /** |
| 3007 | Package. Uncore U-box perfmon event select for U-box counter 0. |
| 3008 | |
| 3009 | @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10) |
| 3010 | @param EAX Lower 32-bits of MSR value. |
| 3011 | @param EDX Upper 32-bits of MSR value. |
| 3012 | |
| 3013 | <b>Example usage</b> |
| 3014 | @code |
| 3015 | UINT64 Msr; |
| 3016 | |
| 3017 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0); |
| 3018 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr); |
| 3019 | @endcode |
| 3020 | @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM. |
| 3021 | **/ |
| 3022 | #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10 |
| 3023 | |
| 3024 | |
| 3025 | /** |
| 3026 | Package. Uncore U-box perfmon event select for U-box counter 1. |
| 3027 | |
| 3028 | @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11) |
| 3029 | @param EAX Lower 32-bits of MSR value. |
| 3030 | @param EDX Upper 32-bits of MSR value. |
| 3031 | |
| 3032 | <b>Example usage</b> |
| 3033 | @code |
| 3034 | UINT64 Msr; |
| 3035 | |
| 3036 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1); |
| 3037 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr); |
| 3038 | @endcode |
| 3039 | @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM. |
| 3040 | **/ |
| 3041 | #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11 |
| 3042 | |
| 3043 | |
| 3044 | /** |
| 3045 | Package. Uncore U-box perfmon counter 0. |
| 3046 | |
| 3047 | @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16) |
| 3048 | @param EAX Lower 32-bits of MSR value. |
| 3049 | @param EDX Upper 32-bits of MSR value. |
| 3050 | |
| 3051 | <b>Example usage</b> |
| 3052 | @code |
| 3053 | UINT64 Msr; |
| 3054 | |
| 3055 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0); |
| 3056 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr); |
| 3057 | @endcode |
| 3058 | @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM. |
| 3059 | **/ |
| 3060 | #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16 |
| 3061 | |
| 3062 | |
| 3063 | /** |
| 3064 | Package. Uncore U-box perfmon counter 1. |
| 3065 | |
| 3066 | @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17) |
| 3067 | @param EAX Lower 32-bits of MSR value. |
| 3068 | @param EDX Upper 32-bits of MSR value. |
| 3069 | |
| 3070 | <b>Example usage</b> |
| 3071 | @code |
| 3072 | UINT64 Msr; |
| 3073 | |
| 3074 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1); |
| 3075 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr); |
| 3076 | @endcode |
| 3077 | @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM. |
| 3078 | **/ |
| 3079 | #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17 |
| 3080 | |
| 3081 | |
| 3082 | /** |
| 3083 | Package. Uncore PCU perfmon for PCU-box-wide control. |
| 3084 | |
| 3085 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24) |
| 3086 | @param EAX Lower 32-bits of MSR value. |
| 3087 | @param EDX Upper 32-bits of MSR value. |
| 3088 | |
| 3089 | <b>Example usage</b> |
| 3090 | @code |
| 3091 | UINT64 Msr; |
| 3092 | |
| 3093 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL); |
| 3094 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr); |
| 3095 | @endcode |
| 3096 | @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM. |
| 3097 | **/ |
| 3098 | #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24 |
| 3099 | |
| 3100 | |
| 3101 | /** |
| 3102 | Package. Uncore PCU perfmon event select for PCU counter 0. |
| 3103 | |
| 3104 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30) |
| 3105 | @param EAX Lower 32-bits of MSR value. |
| 3106 | @param EDX Upper 32-bits of MSR value. |
| 3107 | |
| 3108 | <b>Example usage</b> |
| 3109 | @code |
| 3110 | UINT64 Msr; |
| 3111 | |
| 3112 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0); |
| 3113 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr); |
| 3114 | @endcode |
| 3115 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM. |
| 3116 | **/ |
| 3117 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30 |
| 3118 | |
| 3119 | |
| 3120 | /** |
| 3121 | Package. Uncore PCU perfmon event select for PCU counter 1. |
| 3122 | |
| 3123 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31) |
| 3124 | @param EAX Lower 32-bits of MSR value. |
| 3125 | @param EDX Upper 32-bits of MSR value. |
| 3126 | |
| 3127 | <b>Example usage</b> |
| 3128 | @code |
| 3129 | UINT64 Msr; |
| 3130 | |
| 3131 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1); |
| 3132 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr); |
| 3133 | @endcode |
| 3134 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM. |
| 3135 | **/ |
| 3136 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31 |
| 3137 | |
| 3138 | |
| 3139 | /** |
| 3140 | Package. Uncore PCU perfmon event select for PCU counter 2. |
| 3141 | |
| 3142 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32) |
| 3143 | @param EAX Lower 32-bits of MSR value. |
| 3144 | @param EDX Upper 32-bits of MSR value. |
| 3145 | |
| 3146 | <b>Example usage</b> |
| 3147 | @code |
| 3148 | UINT64 Msr; |
| 3149 | |
| 3150 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2); |
| 3151 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr); |
| 3152 | @endcode |
| 3153 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM. |
| 3154 | **/ |
| 3155 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32 |
| 3156 | |
| 3157 | |
| 3158 | /** |
| 3159 | Package. Uncore PCU perfmon event select for PCU counter 3. |
| 3160 | |
| 3161 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33) |
| 3162 | @param EAX Lower 32-bits of MSR value. |
| 3163 | @param EDX Upper 32-bits of MSR value. |
| 3164 | |
| 3165 | <b>Example usage</b> |
| 3166 | @code |
| 3167 | UINT64 Msr; |
| 3168 | |
| 3169 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3); |
| 3170 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr); |
| 3171 | @endcode |
| 3172 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM. |
| 3173 | **/ |
| 3174 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33 |
| 3175 | |
| 3176 | |
| 3177 | /** |
| 3178 | Package. Uncore PCU perfmon box-wide filter. |
| 3179 | |
| 3180 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34) |
| 3181 | @param EAX Lower 32-bits of MSR value. |
| 3182 | @param EDX Upper 32-bits of MSR value. |
| 3183 | |
| 3184 | <b>Example usage</b> |
| 3185 | @code |
| 3186 | UINT64 Msr; |
| 3187 | |
| 3188 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER); |
| 3189 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr); |
| 3190 | @endcode |
| 3191 | @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM. |
| 3192 | **/ |
| 3193 | #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34 |
| 3194 | |
| 3195 | |
| 3196 | /** |
| 3197 | Package. Uncore PCU perfmon counter 0. |
| 3198 | |
| 3199 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36) |
| 3200 | @param EAX Lower 32-bits of MSR value. |
| 3201 | @param EDX Upper 32-bits of MSR value. |
| 3202 | |
| 3203 | <b>Example usage</b> |
| 3204 | @code |
| 3205 | UINT64 Msr; |
| 3206 | |
| 3207 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0); |
| 3208 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr); |
| 3209 | @endcode |
| 3210 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM. |
| 3211 | **/ |
| 3212 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36 |
| 3213 | |
| 3214 | |
| 3215 | /** |
| 3216 | Package. Uncore PCU perfmon counter 1. |
| 3217 | |
| 3218 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37) |
| 3219 | @param EAX Lower 32-bits of MSR value. |
| 3220 | @param EDX Upper 32-bits of MSR value. |
| 3221 | |
| 3222 | <b>Example usage</b> |
| 3223 | @code |
| 3224 | UINT64 Msr; |
| 3225 | |
| 3226 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1); |
| 3227 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr); |
| 3228 | @endcode |
| 3229 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM. |
| 3230 | **/ |
| 3231 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37 |
| 3232 | |
| 3233 | |
| 3234 | /** |
| 3235 | Package. Uncore PCU perfmon counter 2. |
| 3236 | |
| 3237 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38) |
| 3238 | @param EAX Lower 32-bits of MSR value. |
| 3239 | @param EDX Upper 32-bits of MSR value. |
| 3240 | |
| 3241 | <b>Example usage</b> |
| 3242 | @code |
| 3243 | UINT64 Msr; |
| 3244 | |
| 3245 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2); |
| 3246 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr); |
| 3247 | @endcode |
| 3248 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM. |
| 3249 | **/ |
| 3250 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38 |
| 3251 | |
| 3252 | |
| 3253 | /** |
| 3254 | Package. Uncore PCU perfmon counter 3. |
| 3255 | |
| 3256 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39) |
| 3257 | @param EAX Lower 32-bits of MSR value. |
| 3258 | @param EDX Upper 32-bits of MSR value. |
| 3259 | |
| 3260 | <b>Example usage</b> |
| 3261 | @code |
| 3262 | UINT64 Msr; |
| 3263 | |
| 3264 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3); |
| 3265 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr); |
| 3266 | @endcode |
| 3267 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM. |
| 3268 | **/ |
| 3269 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39 |
| 3270 | |
| 3271 | |
| 3272 | /** |
| 3273 | Package. Uncore C-box 0 perfmon local box wide control. |
| 3274 | |
| 3275 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04) |
| 3276 | @param EAX Lower 32-bits of MSR value. |
| 3277 | @param EDX Upper 32-bits of MSR value. |
| 3278 | |
| 3279 | <b>Example usage</b> |
| 3280 | @code |
| 3281 | UINT64 Msr; |
| 3282 | |
| 3283 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL); |
| 3284 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr); |
| 3285 | @endcode |
| 3286 | @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM. |
| 3287 | **/ |
| 3288 | #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04 |
| 3289 | |
| 3290 | |
| 3291 | /** |
| 3292 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0. |
| 3293 | |
| 3294 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10) |
| 3295 | @param EAX Lower 32-bits of MSR value. |
| 3296 | @param EDX Upper 32-bits of MSR value. |
| 3297 | |
| 3298 | <b>Example usage</b> |
| 3299 | @code |
| 3300 | UINT64 Msr; |
| 3301 | |
| 3302 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0); |
| 3303 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr); |
| 3304 | @endcode |
| 3305 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM. |
| 3306 | **/ |
| 3307 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10 |
| 3308 | |
| 3309 | |
| 3310 | /** |
| 3311 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1. |
| 3312 | |
| 3313 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11) |
| 3314 | @param EAX Lower 32-bits of MSR value. |
| 3315 | @param EDX Upper 32-bits of MSR value. |
| 3316 | |
| 3317 | <b>Example usage</b> |
| 3318 | @code |
| 3319 | UINT64 Msr; |
| 3320 | |
| 3321 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1); |
| 3322 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr); |
| 3323 | @endcode |
| 3324 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM. |
| 3325 | **/ |
| 3326 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11 |
| 3327 | |
| 3328 | |
| 3329 | /** |
| 3330 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2. |
| 3331 | |
| 3332 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12) |
| 3333 | @param EAX Lower 32-bits of MSR value. |
| 3334 | @param EDX Upper 32-bits of MSR value. |
| 3335 | |
| 3336 | <b>Example usage</b> |
| 3337 | @code |
| 3338 | UINT64 Msr; |
| 3339 | |
| 3340 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2); |
| 3341 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr); |
| 3342 | @endcode |
| 3343 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM. |
| 3344 | **/ |
| 3345 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12 |
| 3346 | |
| 3347 | |
| 3348 | /** |
| 3349 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3. |
| 3350 | |
| 3351 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13) |
| 3352 | @param EAX Lower 32-bits of MSR value. |
| 3353 | @param EDX Upper 32-bits of MSR value. |
| 3354 | |
| 3355 | <b>Example usage</b> |
| 3356 | @code |
| 3357 | UINT64 Msr; |
| 3358 | |
| 3359 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3); |
| 3360 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr); |
| 3361 | @endcode |
| 3362 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM. |
| 3363 | **/ |
| 3364 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13 |
| 3365 | |
| 3366 | |
| 3367 | /** |
| 3368 | Package. Uncore C-box 0 perfmon box wide filter. |
| 3369 | |
| 3370 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14) |
| 3371 | @param EAX Lower 32-bits of MSR value. |
| 3372 | @param EDX Upper 32-bits of MSR value. |
| 3373 | |
| 3374 | <b>Example usage</b> |
| 3375 | @code |
| 3376 | UINT64 Msr; |
| 3377 | |
| 3378 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER); |
| 3379 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr); |
| 3380 | @endcode |
| 3381 | @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM. |
| 3382 | **/ |
| 3383 | #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14 |
| 3384 | |
| 3385 | |
| 3386 | /** |
| 3387 | Package. Uncore C-box 0 perfmon counter 0. |
| 3388 | |
| 3389 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16) |
| 3390 | @param EAX Lower 32-bits of MSR value. |
| 3391 | @param EDX Upper 32-bits of MSR value. |
| 3392 | |
| 3393 | <b>Example usage</b> |
| 3394 | @code |
| 3395 | UINT64 Msr; |
| 3396 | |
| 3397 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0); |
| 3398 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr); |
| 3399 | @endcode |
| 3400 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM. |
| 3401 | **/ |
| 3402 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16 |
| 3403 | |
| 3404 | |
| 3405 | /** |
| 3406 | Package. Uncore C-box 0 perfmon counter 1. |
| 3407 | |
| 3408 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17) |
| 3409 | @param EAX Lower 32-bits of MSR value. |
| 3410 | @param EDX Upper 32-bits of MSR value. |
| 3411 | |
| 3412 | <b>Example usage</b> |
| 3413 | @code |
| 3414 | UINT64 Msr; |
| 3415 | |
| 3416 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1); |
| 3417 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr); |
| 3418 | @endcode |
| 3419 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM. |
| 3420 | **/ |
| 3421 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17 |
| 3422 | |
| 3423 | |
| 3424 | /** |
| 3425 | Package. Uncore C-box 0 perfmon counter 2. |
| 3426 | |
| 3427 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18) |
| 3428 | @param EAX Lower 32-bits of MSR value. |
| 3429 | @param EDX Upper 32-bits of MSR value. |
| 3430 | |
| 3431 | <b>Example usage</b> |
| 3432 | @code |
| 3433 | UINT64 Msr; |
| 3434 | |
| 3435 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2); |
| 3436 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr); |
| 3437 | @endcode |
| 3438 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM. |
| 3439 | **/ |
| 3440 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18 |
| 3441 | |
| 3442 | |
| 3443 | /** |
| 3444 | Package. Uncore C-box 0 perfmon counter 3. |
| 3445 | |
| 3446 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19) |
| 3447 | @param EAX Lower 32-bits of MSR value. |
| 3448 | @param EDX Upper 32-bits of MSR value. |
| 3449 | |
| 3450 | <b>Example usage</b> |
| 3451 | @code |
| 3452 | UINT64 Msr; |
| 3453 | |
| 3454 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3); |
| 3455 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr); |
| 3456 | @endcode |
| 3457 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM. |
| 3458 | **/ |
| 3459 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19 |
| 3460 | |
| 3461 | |
| 3462 | /** |
| 3463 | Package. Uncore C-box 1 perfmon local box wide control. |
| 3464 | |
| 3465 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24) |
| 3466 | @param EAX Lower 32-bits of MSR value. |
| 3467 | @param EDX Upper 32-bits of MSR value. |
| 3468 | |
| 3469 | <b>Example usage</b> |
| 3470 | @code |
| 3471 | UINT64 Msr; |
| 3472 | |
| 3473 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL); |
| 3474 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr); |
| 3475 | @endcode |
| 3476 | @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM. |
| 3477 | **/ |
| 3478 | #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24 |
| 3479 | |
| 3480 | |
| 3481 | /** |
| 3482 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0. |
| 3483 | |
| 3484 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30) |
| 3485 | @param EAX Lower 32-bits of MSR value. |
| 3486 | @param EDX Upper 32-bits of MSR value. |
| 3487 | |
| 3488 | <b>Example usage</b> |
| 3489 | @code |
| 3490 | UINT64 Msr; |
| 3491 | |
| 3492 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0); |
| 3493 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr); |
| 3494 | @endcode |
| 3495 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM. |
| 3496 | **/ |
| 3497 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30 |
| 3498 | |
| 3499 | |
| 3500 | /** |
| 3501 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1. |
| 3502 | |
| 3503 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31) |
| 3504 | @param EAX Lower 32-bits of MSR value. |
| 3505 | @param EDX Upper 32-bits of MSR value. |
| 3506 | |
| 3507 | <b>Example usage</b> |
| 3508 | @code |
| 3509 | UINT64 Msr; |
| 3510 | |
| 3511 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1); |
| 3512 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr); |
| 3513 | @endcode |
| 3514 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM. |
| 3515 | **/ |
| 3516 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31 |
| 3517 | |
| 3518 | |
| 3519 | /** |
| 3520 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2. |
| 3521 | |
| 3522 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32) |
| 3523 | @param EAX Lower 32-bits of MSR value. |
| 3524 | @param EDX Upper 32-bits of MSR value. |
| 3525 | |
| 3526 | <b>Example usage</b> |
| 3527 | @code |
| 3528 | UINT64 Msr; |
| 3529 | |
| 3530 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2); |
| 3531 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr); |
| 3532 | @endcode |
| 3533 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM. |
| 3534 | **/ |
| 3535 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32 |
| 3536 | |
| 3537 | |
| 3538 | /** |
| 3539 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3. |
| 3540 | |
| 3541 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33) |
| 3542 | @param EAX Lower 32-bits of MSR value. |
| 3543 | @param EDX Upper 32-bits of MSR value. |
| 3544 | |
| 3545 | <b>Example usage</b> |
| 3546 | @code |
| 3547 | UINT64 Msr; |
| 3548 | |
| 3549 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3); |
| 3550 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr); |
| 3551 | @endcode |
| 3552 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM. |
| 3553 | **/ |
| 3554 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33 |
| 3555 | |
| 3556 | |
| 3557 | /** |
| 3558 | Package. Uncore C-box 1 perfmon box wide filter. |
| 3559 | |
| 3560 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34) |
| 3561 | @param EAX Lower 32-bits of MSR value. |
| 3562 | @param EDX Upper 32-bits of MSR value. |
| 3563 | |
| 3564 | <b>Example usage</b> |
| 3565 | @code |
| 3566 | UINT64 Msr; |
| 3567 | |
| 3568 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER); |
| 3569 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr); |
| 3570 | @endcode |
| 3571 | @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM. |
| 3572 | **/ |
| 3573 | #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34 |
| 3574 | |
| 3575 | |
| 3576 | /** |
| 3577 | Package. Uncore C-box 1 perfmon counter 0. |
| 3578 | |
| 3579 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36) |
| 3580 | @param EAX Lower 32-bits of MSR value. |
| 3581 | @param EDX Upper 32-bits of MSR value. |
| 3582 | |
| 3583 | <b>Example usage</b> |
| 3584 | @code |
| 3585 | UINT64 Msr; |
| 3586 | |
| 3587 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0); |
| 3588 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr); |
| 3589 | @endcode |
| 3590 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM. |
| 3591 | **/ |
| 3592 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36 |
| 3593 | |
| 3594 | |
| 3595 | /** |
| 3596 | Package. Uncore C-box 1 perfmon counter 1. |
| 3597 | |
| 3598 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37) |
| 3599 | @param EAX Lower 32-bits of MSR value. |
| 3600 | @param EDX Upper 32-bits of MSR value. |
| 3601 | |
| 3602 | <b>Example usage</b> |
| 3603 | @code |
| 3604 | UINT64 Msr; |
| 3605 | |
| 3606 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1); |
| 3607 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr); |
| 3608 | @endcode |
| 3609 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM. |
| 3610 | **/ |
| 3611 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37 |
| 3612 | |
| 3613 | |
| 3614 | /** |
| 3615 | Package. Uncore C-box 1 perfmon counter 2. |
| 3616 | |
| 3617 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38) |
| 3618 | @param EAX Lower 32-bits of MSR value. |
| 3619 | @param EDX Upper 32-bits of MSR value. |
| 3620 | |
| 3621 | <b>Example usage</b> |
| 3622 | @code |
| 3623 | UINT64 Msr; |
| 3624 | |
| 3625 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2); |
| 3626 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr); |
| 3627 | @endcode |
| 3628 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM. |
| 3629 | **/ |
| 3630 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38 |
| 3631 | |
| 3632 | |
| 3633 | /** |
| 3634 | Package. Uncore C-box 1 perfmon counter 3. |
| 3635 | |
| 3636 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39) |
| 3637 | @param EAX Lower 32-bits of MSR value. |
| 3638 | @param EDX Upper 32-bits of MSR value. |
| 3639 | |
| 3640 | <b>Example usage</b> |
| 3641 | @code |
| 3642 | UINT64 Msr; |
| 3643 | |
| 3644 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3); |
| 3645 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr); |
| 3646 | @endcode |
| 3647 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM. |
| 3648 | **/ |
| 3649 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39 |
| 3650 | |
| 3651 | |
| 3652 | /** |
| 3653 | Package. Uncore C-box 2 perfmon local box wide control. |
| 3654 | |
| 3655 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44) |
| 3656 | @param EAX Lower 32-bits of MSR value. |
| 3657 | @param EDX Upper 32-bits of MSR value. |
| 3658 | |
| 3659 | <b>Example usage</b> |
| 3660 | @code |
| 3661 | UINT64 Msr; |
| 3662 | |
| 3663 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL); |
| 3664 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr); |
| 3665 | @endcode |
| 3666 | @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM. |
| 3667 | **/ |
| 3668 | #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44 |
| 3669 | |
| 3670 | |
| 3671 | /** |
| 3672 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0. |
| 3673 | |
| 3674 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50) |
| 3675 | @param EAX Lower 32-bits of MSR value. |
| 3676 | @param EDX Upper 32-bits of MSR value. |
| 3677 | |
| 3678 | <b>Example usage</b> |
| 3679 | @code |
| 3680 | UINT64 Msr; |
| 3681 | |
| 3682 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0); |
| 3683 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr); |
| 3684 | @endcode |
| 3685 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM. |
| 3686 | **/ |
| 3687 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50 |
| 3688 | |
| 3689 | |
| 3690 | /** |
| 3691 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1. |
| 3692 | |
| 3693 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51) |
| 3694 | @param EAX Lower 32-bits of MSR value. |
| 3695 | @param EDX Upper 32-bits of MSR value. |
| 3696 | |
| 3697 | <b>Example usage</b> |
| 3698 | @code |
| 3699 | UINT64 Msr; |
| 3700 | |
| 3701 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1); |
| 3702 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr); |
| 3703 | @endcode |
| 3704 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM. |
| 3705 | **/ |
| 3706 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51 |
| 3707 | |
| 3708 | |
| 3709 | /** |
| 3710 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2. |
| 3711 | |
| 3712 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52) |
| 3713 | @param EAX Lower 32-bits of MSR value. |
| 3714 | @param EDX Upper 32-bits of MSR value. |
| 3715 | |
| 3716 | <b>Example usage</b> |
| 3717 | @code |
| 3718 | UINT64 Msr; |
| 3719 | |
| 3720 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2); |
| 3721 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr); |
| 3722 | @endcode |
| 3723 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM. |
| 3724 | **/ |
| 3725 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52 |
| 3726 | |
| 3727 | |
| 3728 | /** |
| 3729 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3. |
| 3730 | |
| 3731 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53) |
| 3732 | @param EAX Lower 32-bits of MSR value. |
| 3733 | @param EDX Upper 32-bits of MSR value. |
| 3734 | |
| 3735 | <b>Example usage</b> |
| 3736 | @code |
| 3737 | UINT64 Msr; |
| 3738 | |
| 3739 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3); |
| 3740 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr); |
| 3741 | @endcode |
| 3742 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM. |
| 3743 | **/ |
| 3744 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53 |
| 3745 | |
| 3746 | |
| 3747 | /** |
| 3748 | Package. Uncore C-box 2 perfmon box wide filter. |
| 3749 | |
| 3750 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54) |
| 3751 | @param EAX Lower 32-bits of MSR value. |
| 3752 | @param EDX Upper 32-bits of MSR value. |
| 3753 | |
| 3754 | <b>Example usage</b> |
| 3755 | @code |
| 3756 | UINT64 Msr; |
| 3757 | |
| 3758 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER); |
| 3759 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr); |
| 3760 | @endcode |
| 3761 | @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM. |
| 3762 | **/ |
| 3763 | #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54 |
| 3764 | |
| 3765 | |
| 3766 | /** |
| 3767 | Package. Uncore C-box 2 perfmon counter 0. |
| 3768 | |
| 3769 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56) |
| 3770 | @param EAX Lower 32-bits of MSR value. |
| 3771 | @param EDX Upper 32-bits of MSR value. |
| 3772 | |
| 3773 | <b>Example usage</b> |
| 3774 | @code |
| 3775 | UINT64 Msr; |
| 3776 | |
| 3777 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0); |
| 3778 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr); |
| 3779 | @endcode |
| 3780 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM. |
| 3781 | **/ |
| 3782 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56 |
| 3783 | |
| 3784 | |
| 3785 | /** |
| 3786 | Package. Uncore C-box 2 perfmon counter 1. |
| 3787 | |
| 3788 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57) |
| 3789 | @param EAX Lower 32-bits of MSR value. |
| 3790 | @param EDX Upper 32-bits of MSR value. |
| 3791 | |
| 3792 | <b>Example usage</b> |
| 3793 | @code |
| 3794 | UINT64 Msr; |
| 3795 | |
| 3796 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1); |
| 3797 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr); |
| 3798 | @endcode |
| 3799 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM. |
| 3800 | **/ |
| 3801 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57 |
| 3802 | |
| 3803 | |
| 3804 | /** |
| 3805 | Package. Uncore C-box 2 perfmon counter 2. |
| 3806 | |
| 3807 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58) |
| 3808 | @param EAX Lower 32-bits of MSR value. |
| 3809 | @param EDX Upper 32-bits of MSR value. |
| 3810 | |
| 3811 | <b>Example usage</b> |
| 3812 | @code |
| 3813 | UINT64 Msr; |
| 3814 | |
| 3815 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2); |
| 3816 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr); |
| 3817 | @endcode |
| 3818 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM. |
| 3819 | **/ |
| 3820 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58 |
| 3821 | |
| 3822 | |
| 3823 | /** |
| 3824 | Package. Uncore C-box 2 perfmon counter 3. |
| 3825 | |
| 3826 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59) |
| 3827 | @param EAX Lower 32-bits of MSR value. |
| 3828 | @param EDX Upper 32-bits of MSR value. |
| 3829 | |
| 3830 | <b>Example usage</b> |
| 3831 | @code |
| 3832 | UINT64 Msr; |
| 3833 | |
| 3834 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3); |
| 3835 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr); |
| 3836 | @endcode |
| 3837 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM. |
| 3838 | **/ |
| 3839 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59 |
| 3840 | |
| 3841 | |
| 3842 | /** |
| 3843 | Package. Uncore C-box 3 perfmon local box wide control. |
| 3844 | |
| 3845 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64) |
| 3846 | @param EAX Lower 32-bits of MSR value. |
| 3847 | @param EDX Upper 32-bits of MSR value. |
| 3848 | |
| 3849 | <b>Example usage</b> |
| 3850 | @code |
| 3851 | UINT64 Msr; |
| 3852 | |
| 3853 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL); |
| 3854 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr); |
| 3855 | @endcode |
| 3856 | @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM. |
| 3857 | **/ |
| 3858 | #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64 |
| 3859 | |
| 3860 | |
| 3861 | /** |
| 3862 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0. |
| 3863 | |
| 3864 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70) |
| 3865 | @param EAX Lower 32-bits of MSR value. |
| 3866 | @param EDX Upper 32-bits of MSR value. |
| 3867 | |
| 3868 | <b>Example usage</b> |
| 3869 | @code |
| 3870 | UINT64 Msr; |
| 3871 | |
| 3872 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0); |
| 3873 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr); |
| 3874 | @endcode |
| 3875 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM. |
| 3876 | **/ |
| 3877 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70 |
| 3878 | |
| 3879 | |
| 3880 | /** |
| 3881 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1. |
| 3882 | |
| 3883 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71) |
| 3884 | @param EAX Lower 32-bits of MSR value. |
| 3885 | @param EDX Upper 32-bits of MSR value. |
| 3886 | |
| 3887 | <b>Example usage</b> |
| 3888 | @code |
| 3889 | UINT64 Msr; |
| 3890 | |
| 3891 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1); |
| 3892 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr); |
| 3893 | @endcode |
| 3894 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM. |
| 3895 | **/ |
| 3896 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71 |
| 3897 | |
| 3898 | |
| 3899 | /** |
| 3900 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2. |
| 3901 | |
| 3902 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72) |
| 3903 | @param EAX Lower 32-bits of MSR value. |
| 3904 | @param EDX Upper 32-bits of MSR value. |
| 3905 | |
| 3906 | <b>Example usage</b> |
| 3907 | @code |
| 3908 | UINT64 Msr; |
| 3909 | |
| 3910 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2); |
| 3911 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr); |
| 3912 | @endcode |
| 3913 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM. |
| 3914 | **/ |
| 3915 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72 |
| 3916 | |
| 3917 | |
| 3918 | /** |
| 3919 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3. |
| 3920 | |
| 3921 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73) |
| 3922 | @param EAX Lower 32-bits of MSR value. |
| 3923 | @param EDX Upper 32-bits of MSR value. |
| 3924 | |
| 3925 | <b>Example usage</b> |
| 3926 | @code |
| 3927 | UINT64 Msr; |
| 3928 | |
| 3929 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3); |
| 3930 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr); |
| 3931 | @endcode |
| 3932 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM. |
| 3933 | **/ |
| 3934 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73 |
| 3935 | |
| 3936 | |
| 3937 | /** |
| 3938 | Package. Uncore C-box 3 perfmon box wide filter. |
| 3939 | |
| 3940 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74) |
| 3941 | @param EAX Lower 32-bits of MSR value. |
| 3942 | @param EDX Upper 32-bits of MSR value. |
| 3943 | |
| 3944 | <b>Example usage</b> |
| 3945 | @code |
| 3946 | UINT64 Msr; |
| 3947 | |
| 3948 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER); |
| 3949 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr); |
| 3950 | @endcode |
| 3951 | @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM. |
| 3952 | **/ |
| 3953 | #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74 |
| 3954 | |
| 3955 | |
| 3956 | /** |
| 3957 | Package. Uncore C-box 3 perfmon counter 0. |
| 3958 | |
| 3959 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76) |
| 3960 | @param EAX Lower 32-bits of MSR value. |
| 3961 | @param EDX Upper 32-bits of MSR value. |
| 3962 | |
| 3963 | <b>Example usage</b> |
| 3964 | @code |
| 3965 | UINT64 Msr; |
| 3966 | |
| 3967 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0); |
| 3968 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr); |
| 3969 | @endcode |
| 3970 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM. |
| 3971 | **/ |
| 3972 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76 |
| 3973 | |
| 3974 | |
| 3975 | /** |
| 3976 | Package. Uncore C-box 3 perfmon counter 1. |
| 3977 | |
| 3978 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77) |
| 3979 | @param EAX Lower 32-bits of MSR value. |
| 3980 | @param EDX Upper 32-bits of MSR value. |
| 3981 | |
| 3982 | <b>Example usage</b> |
| 3983 | @code |
| 3984 | UINT64 Msr; |
| 3985 | |
| 3986 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1); |
| 3987 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr); |
| 3988 | @endcode |
| 3989 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM. |
| 3990 | **/ |
| 3991 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77 |
| 3992 | |
| 3993 | |
| 3994 | /** |
| 3995 | Package. Uncore C-box 3 perfmon counter 2. |
| 3996 | |
| 3997 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78) |
| 3998 | @param EAX Lower 32-bits of MSR value. |
| 3999 | @param EDX Upper 32-bits of MSR value. |
| 4000 | |
| 4001 | <b>Example usage</b> |
| 4002 | @code |
| 4003 | UINT64 Msr; |
| 4004 | |
| 4005 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2); |
| 4006 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr); |
| 4007 | @endcode |
| 4008 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM. |
| 4009 | **/ |
| 4010 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78 |
| 4011 | |
| 4012 | |
| 4013 | /** |
| 4014 | Package. Uncore C-box 3 perfmon counter 3. |
| 4015 | |
| 4016 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79) |
| 4017 | @param EAX Lower 32-bits of MSR value. |
| 4018 | @param EDX Upper 32-bits of MSR value. |
| 4019 | |
| 4020 | <b>Example usage</b> |
| 4021 | @code |
| 4022 | UINT64 Msr; |
| 4023 | |
| 4024 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3); |
| 4025 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr); |
| 4026 | @endcode |
| 4027 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM. |
| 4028 | **/ |
| 4029 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79 |
| 4030 | |
| 4031 | |
| 4032 | /** |
| 4033 | Package. Uncore C-box 4 perfmon local box wide control. |
| 4034 | |
| 4035 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84) |
| 4036 | @param EAX Lower 32-bits of MSR value. |
| 4037 | @param EDX Upper 32-bits of MSR value. |
| 4038 | |
| 4039 | <b>Example usage</b> |
| 4040 | @code |
| 4041 | UINT64 Msr; |
| 4042 | |
| 4043 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL); |
| 4044 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr); |
| 4045 | @endcode |
| 4046 | @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM. |
| 4047 | **/ |
| 4048 | #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84 |
| 4049 | |
| 4050 | |
| 4051 | /** |
| 4052 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0. |
| 4053 | |
| 4054 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90) |
| 4055 | @param EAX Lower 32-bits of MSR value. |
| 4056 | @param EDX Upper 32-bits of MSR value. |
| 4057 | |
| 4058 | <b>Example usage</b> |
| 4059 | @code |
| 4060 | UINT64 Msr; |
| 4061 | |
| 4062 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0); |
| 4063 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr); |
| 4064 | @endcode |
| 4065 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM. |
| 4066 | **/ |
| 4067 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90 |
| 4068 | |
| 4069 | |
| 4070 | /** |
| 4071 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1. |
| 4072 | |
| 4073 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91) |
| 4074 | @param EAX Lower 32-bits of MSR value. |
| 4075 | @param EDX Upper 32-bits of MSR value. |
| 4076 | |
| 4077 | <b>Example usage</b> |
| 4078 | @code |
| 4079 | UINT64 Msr; |
| 4080 | |
| 4081 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1); |
| 4082 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr); |
| 4083 | @endcode |
| 4084 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM. |
| 4085 | **/ |
| 4086 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91 |
| 4087 | |
| 4088 | |
| 4089 | /** |
| 4090 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2. |
| 4091 | |
| 4092 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92) |
| 4093 | @param EAX Lower 32-bits of MSR value. |
| 4094 | @param EDX Upper 32-bits of MSR value. |
| 4095 | |
| 4096 | <b>Example usage</b> |
| 4097 | @code |
| 4098 | UINT64 Msr; |
| 4099 | |
| 4100 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2); |
| 4101 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr); |
| 4102 | @endcode |
| 4103 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM. |
| 4104 | **/ |
| 4105 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92 |
| 4106 | |
| 4107 | |
| 4108 | /** |
| 4109 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3. |
| 4110 | |
| 4111 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93) |
| 4112 | @param EAX Lower 32-bits of MSR value. |
| 4113 | @param EDX Upper 32-bits of MSR value. |
| 4114 | |
| 4115 | <b>Example usage</b> |
| 4116 | @code |
| 4117 | UINT64 Msr; |
| 4118 | |
| 4119 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3); |
| 4120 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr); |
| 4121 | @endcode |
| 4122 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM. |
| 4123 | **/ |
| 4124 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93 |
| 4125 | |
| 4126 | |
| 4127 | /** |
| 4128 | Package. Uncore C-box 4 perfmon box wide filter. |
| 4129 | |
| 4130 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94) |
| 4131 | @param EAX Lower 32-bits of MSR value. |
| 4132 | @param EDX Upper 32-bits of MSR value. |
| 4133 | |
| 4134 | <b>Example usage</b> |
| 4135 | @code |
| 4136 | UINT64 Msr; |
| 4137 | |
| 4138 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER); |
| 4139 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr); |
| 4140 | @endcode |
| 4141 | @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM. |
| 4142 | **/ |
| 4143 | #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94 |
| 4144 | |
| 4145 | |
| 4146 | /** |
| 4147 | Package. Uncore C-box 4 perfmon counter 0. |
| 4148 | |
| 4149 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96) |
| 4150 | @param EAX Lower 32-bits of MSR value. |
| 4151 | @param EDX Upper 32-bits of MSR value. |
| 4152 | |
| 4153 | <b>Example usage</b> |
| 4154 | @code |
| 4155 | UINT64 Msr; |
| 4156 | |
| 4157 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0); |
| 4158 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr); |
| 4159 | @endcode |
| 4160 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM. |
| 4161 | **/ |
| 4162 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96 |
| 4163 | |
| 4164 | |
| 4165 | /** |
| 4166 | Package. Uncore C-box 4 perfmon counter 1. |
| 4167 | |
| 4168 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97) |
| 4169 | @param EAX Lower 32-bits of MSR value. |
| 4170 | @param EDX Upper 32-bits of MSR value. |
| 4171 | |
| 4172 | <b>Example usage</b> |
| 4173 | @code |
| 4174 | UINT64 Msr; |
| 4175 | |
| 4176 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1); |
| 4177 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr); |
| 4178 | @endcode |
| 4179 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM. |
| 4180 | **/ |
| 4181 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97 |
| 4182 | |
| 4183 | |
| 4184 | /** |
| 4185 | Package. Uncore C-box 4 perfmon counter 2. |
| 4186 | |
| 4187 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98) |
| 4188 | @param EAX Lower 32-bits of MSR value. |
| 4189 | @param EDX Upper 32-bits of MSR value. |
| 4190 | |
| 4191 | <b>Example usage</b> |
| 4192 | @code |
| 4193 | UINT64 Msr; |
| 4194 | |
| 4195 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2); |
| 4196 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr); |
| 4197 | @endcode |
| 4198 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM. |
| 4199 | **/ |
| 4200 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98 |
| 4201 | |
| 4202 | |
| 4203 | /** |
| 4204 | Package. Uncore C-box 4 perfmon counter 3. |
| 4205 | |
| 4206 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99) |
| 4207 | @param EAX Lower 32-bits of MSR value. |
| 4208 | @param EDX Upper 32-bits of MSR value. |
| 4209 | |
| 4210 | <b>Example usage</b> |
| 4211 | @code |
| 4212 | UINT64 Msr; |
| 4213 | |
| 4214 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3); |
| 4215 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr); |
| 4216 | @endcode |
| 4217 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM. |
| 4218 | **/ |
| 4219 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99 |
| 4220 | |
| 4221 | |
| 4222 | /** |
| 4223 | Package. Uncore C-box 5 perfmon local box wide control. |
| 4224 | |
| 4225 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4) |
| 4226 | @param EAX Lower 32-bits of MSR value. |
| 4227 | @param EDX Upper 32-bits of MSR value. |
| 4228 | |
| 4229 | <b>Example usage</b> |
| 4230 | @code |
| 4231 | UINT64 Msr; |
| 4232 | |
| 4233 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL); |
| 4234 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr); |
| 4235 | @endcode |
| 4236 | @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM. |
| 4237 | **/ |
| 4238 | #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4 |
| 4239 | |
| 4240 | |
| 4241 | /** |
| 4242 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0. |
| 4243 | |
| 4244 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0) |
| 4245 | @param EAX Lower 32-bits of MSR value. |
| 4246 | @param EDX Upper 32-bits of MSR value. |
| 4247 | |
| 4248 | <b>Example usage</b> |
| 4249 | @code |
| 4250 | UINT64 Msr; |
| 4251 | |
| 4252 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0); |
| 4253 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr); |
| 4254 | @endcode |
| 4255 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM. |
| 4256 | **/ |
| 4257 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0 |
| 4258 | |
| 4259 | |
| 4260 | /** |
| 4261 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1. |
| 4262 | |
| 4263 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1) |
| 4264 | @param EAX Lower 32-bits of MSR value. |
| 4265 | @param EDX Upper 32-bits of MSR value. |
| 4266 | |
| 4267 | <b>Example usage</b> |
| 4268 | @code |
| 4269 | UINT64 Msr; |
| 4270 | |
| 4271 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1); |
| 4272 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr); |
| 4273 | @endcode |
| 4274 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM. |
| 4275 | **/ |
| 4276 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1 |
| 4277 | |
| 4278 | |
| 4279 | /** |
| 4280 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2. |
| 4281 | |
| 4282 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2) |
| 4283 | @param EAX Lower 32-bits of MSR value. |
| 4284 | @param EDX Upper 32-bits of MSR value. |
| 4285 | |
| 4286 | <b>Example usage</b> |
| 4287 | @code |
| 4288 | UINT64 Msr; |
| 4289 | |
| 4290 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2); |
| 4291 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr); |
| 4292 | @endcode |
| 4293 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM. |
| 4294 | **/ |
| 4295 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2 |
| 4296 | |
| 4297 | |
| 4298 | /** |
| 4299 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3. |
| 4300 | |
| 4301 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3) |
| 4302 | @param EAX Lower 32-bits of MSR value. |
| 4303 | @param EDX Upper 32-bits of MSR value. |
| 4304 | |
| 4305 | <b>Example usage</b> |
| 4306 | @code |
| 4307 | UINT64 Msr; |
| 4308 | |
| 4309 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3); |
| 4310 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr); |
| 4311 | @endcode |
| 4312 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM. |
| 4313 | **/ |
| 4314 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3 |
| 4315 | |
| 4316 | |
| 4317 | /** |
| 4318 | Package. Uncore C-box 5 perfmon box wide filter. |
| 4319 | |
| 4320 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4) |
| 4321 | @param EAX Lower 32-bits of MSR value. |
| 4322 | @param EDX Upper 32-bits of MSR value. |
| 4323 | |
| 4324 | <b>Example usage</b> |
| 4325 | @code |
| 4326 | UINT64 Msr; |
| 4327 | |
| 4328 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER); |
| 4329 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr); |
| 4330 | @endcode |
| 4331 | @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM. |
| 4332 | **/ |
| 4333 | #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4 |
| 4334 | |
| 4335 | |
| 4336 | /** |
| 4337 | Package. Uncore C-box 5 perfmon counter 0. |
| 4338 | |
| 4339 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6) |
| 4340 | @param EAX Lower 32-bits of MSR value. |
| 4341 | @param EDX Upper 32-bits of MSR value. |
| 4342 | |
| 4343 | <b>Example usage</b> |
| 4344 | @code |
| 4345 | UINT64 Msr; |
| 4346 | |
| 4347 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0); |
| 4348 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr); |
| 4349 | @endcode |
| 4350 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM. |
| 4351 | **/ |
| 4352 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6 |
| 4353 | |
| 4354 | |
| 4355 | /** |
| 4356 | Package. Uncore C-box 5 perfmon counter 1. |
| 4357 | |
| 4358 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7) |
| 4359 | @param EAX Lower 32-bits of MSR value. |
| 4360 | @param EDX Upper 32-bits of MSR value. |
| 4361 | |
| 4362 | <b>Example usage</b> |
| 4363 | @code |
| 4364 | UINT64 Msr; |
| 4365 | |
| 4366 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1); |
| 4367 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr); |
| 4368 | @endcode |
| 4369 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM. |
| 4370 | **/ |
| 4371 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7 |
| 4372 | |
| 4373 | |
| 4374 | /** |
| 4375 | Package. Uncore C-box 5 perfmon counter 2. |
| 4376 | |
| 4377 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8) |
| 4378 | @param EAX Lower 32-bits of MSR value. |
| 4379 | @param EDX Upper 32-bits of MSR value. |
| 4380 | |
| 4381 | <b>Example usage</b> |
| 4382 | @code |
| 4383 | UINT64 Msr; |
| 4384 | |
| 4385 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2); |
| 4386 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr); |
| 4387 | @endcode |
| 4388 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM. |
| 4389 | **/ |
| 4390 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8 |
| 4391 | |
| 4392 | |
| 4393 | /** |
| 4394 | Package. Uncore C-box 5 perfmon counter 3. |
| 4395 | |
| 4396 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9) |
| 4397 | @param EAX Lower 32-bits of MSR value. |
| 4398 | @param EDX Upper 32-bits of MSR value. |
| 4399 | |
| 4400 | <b>Example usage</b> |
| 4401 | @code |
| 4402 | UINT64 Msr; |
| 4403 | |
| 4404 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3); |
| 4405 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr); |
| 4406 | @endcode |
| 4407 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM. |
| 4408 | **/ |
| 4409 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9 |
| 4410 | |
| 4411 | |
| 4412 | /** |
| 4413 | Package. Uncore C-box 6 perfmon local box wide control. |
| 4414 | |
| 4415 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4) |
| 4416 | @param EAX Lower 32-bits of MSR value. |
| 4417 | @param EDX Upper 32-bits of MSR value. |
| 4418 | |
| 4419 | <b>Example usage</b> |
| 4420 | @code |
| 4421 | UINT64 Msr; |
| 4422 | |
| 4423 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL); |
| 4424 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr); |
| 4425 | @endcode |
| 4426 | @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM. |
| 4427 | **/ |
| 4428 | #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4 |
| 4429 | |
| 4430 | |
| 4431 | /** |
| 4432 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0. |
| 4433 | |
| 4434 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0) |
| 4435 | @param EAX Lower 32-bits of MSR value. |
| 4436 | @param EDX Upper 32-bits of MSR value. |
| 4437 | |
| 4438 | <b>Example usage</b> |
| 4439 | @code |
| 4440 | UINT64 Msr; |
| 4441 | |
| 4442 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0); |
| 4443 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr); |
| 4444 | @endcode |
| 4445 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM. |
| 4446 | **/ |
| 4447 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0 |
| 4448 | |
| 4449 | |
| 4450 | /** |
| 4451 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1. |
| 4452 | |
| 4453 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1) |
| 4454 | @param EAX Lower 32-bits of MSR value. |
| 4455 | @param EDX Upper 32-bits of MSR value. |
| 4456 | |
| 4457 | <b>Example usage</b> |
| 4458 | @code |
| 4459 | UINT64 Msr; |
| 4460 | |
| 4461 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1); |
| 4462 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr); |
| 4463 | @endcode |
| 4464 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM. |
| 4465 | **/ |
| 4466 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1 |
| 4467 | |
| 4468 | |
| 4469 | /** |
| 4470 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2. |
| 4471 | |
| 4472 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2) |
| 4473 | @param EAX Lower 32-bits of MSR value. |
| 4474 | @param EDX Upper 32-bits of MSR value. |
| 4475 | |
| 4476 | <b>Example usage</b> |
| 4477 | @code |
| 4478 | UINT64 Msr; |
| 4479 | |
| 4480 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2); |
| 4481 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr); |
| 4482 | @endcode |
| 4483 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM. |
| 4484 | **/ |
| 4485 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2 |
| 4486 | |
| 4487 | |
| 4488 | /** |
| 4489 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3. |
| 4490 | |
| 4491 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3) |
| 4492 | @param EAX Lower 32-bits of MSR value. |
| 4493 | @param EDX Upper 32-bits of MSR value. |
| 4494 | |
| 4495 | <b>Example usage</b> |
| 4496 | @code |
| 4497 | UINT64 Msr; |
| 4498 | |
| 4499 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3); |
| 4500 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr); |
| 4501 | @endcode |
| 4502 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM. |
| 4503 | **/ |
| 4504 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3 |
| 4505 | |
| 4506 | |
| 4507 | /** |
| 4508 | Package. Uncore C-box 6 perfmon box wide filter. |
| 4509 | |
| 4510 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4) |
| 4511 | @param EAX Lower 32-bits of MSR value. |
| 4512 | @param EDX Upper 32-bits of MSR value. |
| 4513 | |
| 4514 | <b>Example usage</b> |
| 4515 | @code |
| 4516 | UINT64 Msr; |
| 4517 | |
| 4518 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER); |
| 4519 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr); |
| 4520 | @endcode |
| 4521 | @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM. |
| 4522 | **/ |
| 4523 | #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4 |
| 4524 | |
| 4525 | |
| 4526 | /** |
| 4527 | Package. Uncore C-box 6 perfmon counter 0. |
| 4528 | |
| 4529 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6) |
| 4530 | @param EAX Lower 32-bits of MSR value. |
| 4531 | @param EDX Upper 32-bits of MSR value. |
| 4532 | |
| 4533 | <b>Example usage</b> |
| 4534 | @code |
| 4535 | UINT64 Msr; |
| 4536 | |
| 4537 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0); |
| 4538 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr); |
| 4539 | @endcode |
| 4540 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM. |
| 4541 | **/ |
| 4542 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6 |
| 4543 | |
| 4544 | |
| 4545 | /** |
| 4546 | Package. Uncore C-box 6 perfmon counter 1. |
| 4547 | |
| 4548 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7) |
| 4549 | @param EAX Lower 32-bits of MSR value. |
| 4550 | @param EDX Upper 32-bits of MSR value. |
| 4551 | |
| 4552 | <b>Example usage</b> |
| 4553 | @code |
| 4554 | UINT64 Msr; |
| 4555 | |
| 4556 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1); |
| 4557 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr); |
| 4558 | @endcode |
| 4559 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM. |
| 4560 | **/ |
| 4561 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7 |
| 4562 | |
| 4563 | |
| 4564 | /** |
| 4565 | Package. Uncore C-box 6 perfmon counter 2. |
| 4566 | |
| 4567 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8) |
| 4568 | @param EAX Lower 32-bits of MSR value. |
| 4569 | @param EDX Upper 32-bits of MSR value. |
| 4570 | |
| 4571 | <b>Example usage</b> |
| 4572 | @code |
| 4573 | UINT64 Msr; |
| 4574 | |
| 4575 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2); |
| 4576 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr); |
| 4577 | @endcode |
| 4578 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM. |
| 4579 | **/ |
| 4580 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8 |
| 4581 | |
| 4582 | |
| 4583 | /** |
| 4584 | Package. Uncore C-box 6 perfmon counter 3. |
| 4585 | |
| 4586 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9) |
| 4587 | @param EAX Lower 32-bits of MSR value. |
| 4588 | @param EDX Upper 32-bits of MSR value. |
| 4589 | |
| 4590 | <b>Example usage</b> |
| 4591 | @code |
| 4592 | UINT64 Msr; |
| 4593 | |
| 4594 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3); |
| 4595 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr); |
| 4596 | @endcode |
| 4597 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM. |
| 4598 | **/ |
| 4599 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9 |
| 4600 | |
| 4601 | |
| 4602 | /** |
| 4603 | Package. Uncore C-box 7 perfmon local box wide control. |
| 4604 | |
| 4605 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4) |
| 4606 | @param EAX Lower 32-bits of MSR value. |
| 4607 | @param EDX Upper 32-bits of MSR value. |
| 4608 | |
| 4609 | <b>Example usage</b> |
| 4610 | @code |
| 4611 | UINT64 Msr; |
| 4612 | |
| 4613 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL); |
| 4614 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr); |
| 4615 | @endcode |
| 4616 | @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM. |
| 4617 | **/ |
| 4618 | #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4 |
| 4619 | |
| 4620 | |
| 4621 | /** |
| 4622 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0. |
| 4623 | |
| 4624 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0) |
| 4625 | @param EAX Lower 32-bits of MSR value. |
| 4626 | @param EDX Upper 32-bits of MSR value. |
| 4627 | |
| 4628 | <b>Example usage</b> |
| 4629 | @code |
| 4630 | UINT64 Msr; |
| 4631 | |
| 4632 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0); |
| 4633 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr); |
| 4634 | @endcode |
| 4635 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM. |
| 4636 | **/ |
| 4637 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0 |
| 4638 | |
| 4639 | |
| 4640 | /** |
| 4641 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1. |
| 4642 | |
| 4643 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1) |
| 4644 | @param EAX Lower 32-bits of MSR value. |
| 4645 | @param EDX Upper 32-bits of MSR value. |
| 4646 | |
| 4647 | <b>Example usage</b> |
| 4648 | @code |
| 4649 | UINT64 Msr; |
| 4650 | |
| 4651 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1); |
| 4652 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr); |
| 4653 | @endcode |
| 4654 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM. |
| 4655 | **/ |
| 4656 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1 |
| 4657 | |
| 4658 | |
| 4659 | /** |
| 4660 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2. |
| 4661 | |
| 4662 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2) |
| 4663 | @param EAX Lower 32-bits of MSR value. |
| 4664 | @param EDX Upper 32-bits of MSR value. |
| 4665 | |
| 4666 | <b>Example usage</b> |
| 4667 | @code |
| 4668 | UINT64 Msr; |
| 4669 | |
| 4670 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2); |
| 4671 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr); |
| 4672 | @endcode |
| 4673 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM. |
| 4674 | **/ |
| 4675 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2 |
| 4676 | |
| 4677 | |
| 4678 | /** |
| 4679 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3. |
| 4680 | |
| 4681 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3) |
| 4682 | @param EAX Lower 32-bits of MSR value. |
| 4683 | @param EDX Upper 32-bits of MSR value. |
| 4684 | |
| 4685 | <b>Example usage</b> |
| 4686 | @code |
| 4687 | UINT64 Msr; |
| 4688 | |
| 4689 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3); |
| 4690 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr); |
| 4691 | @endcode |
| 4692 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM. |
| 4693 | **/ |
| 4694 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3 |
| 4695 | |
| 4696 | |
| 4697 | /** |
| 4698 | Package. Uncore C-box 7 perfmon box wide filter. |
| 4699 | |
| 4700 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4) |
| 4701 | @param EAX Lower 32-bits of MSR value. |
| 4702 | @param EDX Upper 32-bits of MSR value. |
| 4703 | |
| 4704 | <b>Example usage</b> |
| 4705 | @code |
| 4706 | UINT64 Msr; |
| 4707 | |
| 4708 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER); |
| 4709 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr); |
| 4710 | @endcode |
| 4711 | @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM. |
| 4712 | **/ |
| 4713 | #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4 |
| 4714 | |
| 4715 | |
| 4716 | /** |
| 4717 | Package. Uncore C-box 7 perfmon counter 0. |
| 4718 | |
| 4719 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6) |
| 4720 | @param EAX Lower 32-bits of MSR value. |
| 4721 | @param EDX Upper 32-bits of MSR value. |
| 4722 | |
| 4723 | <b>Example usage</b> |
| 4724 | @code |
| 4725 | UINT64 Msr; |
| 4726 | |
| 4727 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0); |
| 4728 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr); |
| 4729 | @endcode |
| 4730 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM. |
| 4731 | **/ |
| 4732 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6 |
| 4733 | |
| 4734 | |
| 4735 | /** |
| 4736 | Package. Uncore C-box 7 perfmon counter 1. |
| 4737 | |
| 4738 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7) |
| 4739 | @param EAX Lower 32-bits of MSR value. |
| 4740 | @param EDX Upper 32-bits of MSR value. |
| 4741 | |
| 4742 | <b>Example usage</b> |
| 4743 | @code |
| 4744 | UINT64 Msr; |
| 4745 | |
| 4746 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1); |
| 4747 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr); |
| 4748 | @endcode |
| 4749 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM. |
| 4750 | **/ |
| 4751 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7 |
| 4752 | |
| 4753 | |
| 4754 | /** |
| 4755 | Package. Uncore C-box 7 perfmon counter 2. |
| 4756 | |
| 4757 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8) |
| 4758 | @param EAX Lower 32-bits of MSR value. |
| 4759 | @param EDX Upper 32-bits of MSR value. |
| 4760 | |
| 4761 | <b>Example usage</b> |
| 4762 | @code |
| 4763 | UINT64 Msr; |
| 4764 | |
| 4765 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2); |
| 4766 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr); |
| 4767 | @endcode |
| 4768 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM. |
| 4769 | **/ |
| 4770 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8 |
| 4771 | |
| 4772 | |
| 4773 | /** |
| 4774 | Package. Uncore C-box 7 perfmon counter 3. |
| 4775 | |
| 4776 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9) |
| 4777 | @param EAX Lower 32-bits of MSR value. |
| 4778 | @param EDX Upper 32-bits of MSR value. |
| 4779 | |
| 4780 | <b>Example usage</b> |
| 4781 | @code |
| 4782 | UINT64 Msr; |
| 4783 | |
| 4784 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3); |
| 4785 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr); |
| 4786 | @endcode |
| 4787 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM. |
| 4788 | **/ |
| 4789 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9 |
| 4790 | |
| 4791 | #endif |