Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | MSR Definitions for P6 Family Processors. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __P6_MSR_H__ |
| 19 | #define __P6_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is P6 Family Processors? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x06 && \ |
| 34 | ( \ |
| 35 | DisplayModel == 0x03 || \ |
| 36 | DisplayModel == 0x05 || \ |
| 37 | DisplayModel == 0x07 || \ |
| 38 | DisplayModel == 0x08 || \ |
| 39 | DisplayModel == 0x0A || \ |
| 40 | DisplayModel == 0x0B \ |
| 41 | ) \ |
| 42 | ) |
| 43 | |
| 44 | /** |
| 45 | See Section 2.22, "MSRs in Pentium Processors.". |
| 46 | |
| 47 | @param ECX MSR_P6_P5_MC_ADDR (0x00000000) |
| 48 | @param EAX Lower 32-bits of MSR value. |
| 49 | @param EDX Upper 32-bits of MSR value. |
| 50 | |
| 51 | <b>Example usage</b> |
| 52 | @code |
| 53 | UINT64 Msr; |
| 54 | |
| 55 | Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR); |
| 56 | AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr); |
| 57 | @endcode |
| 58 | @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. |
| 59 | **/ |
| 60 | #define MSR_P6_P5_MC_ADDR 0x00000000 |
| 61 | |
| 62 | |
| 63 | /** |
| 64 | See Section 2.22, "MSRs in Pentium Processors.". |
| 65 | |
| 66 | @param ECX MSR_P6_P5_MC_TYPE (0x00000001) |
| 67 | @param EAX Lower 32-bits of MSR value. |
| 68 | @param EDX Upper 32-bits of MSR value. |
| 69 | |
| 70 | <b>Example usage</b> |
| 71 | @code |
| 72 | UINT64 Msr; |
| 73 | |
| 74 | Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE); |
| 75 | AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr); |
| 76 | @endcode |
| 77 | @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. |
| 78 | **/ |
| 79 | #define MSR_P6_P5_MC_TYPE 0x00000001 |
| 80 | |
| 81 | |
| 82 | /** |
| 83 | See Section 17.17, "Time-Stamp Counter.". |
| 84 | |
| 85 | @param ECX MSR_P6_TSC (0x00000010) |
| 86 | @param EAX Lower 32-bits of MSR value. |
| 87 | @param EDX Upper 32-bits of MSR value. |
| 88 | |
| 89 | <b>Example usage</b> |
| 90 | @code |
| 91 | UINT64 Msr; |
| 92 | |
| 93 | Msr = AsmReadMsr64 (MSR_P6_TSC); |
| 94 | AsmWriteMsr64 (MSR_P6_TSC, Msr); |
| 95 | @endcode |
| 96 | @note MSR_P6_TSC is defined as TSC in SDM. |
| 97 | **/ |
| 98 | #define MSR_P6_TSC 0x00000010 |
| 99 | |
| 100 | |
| 101 | /** |
| 102 | Platform ID (R) The operating system can use this MSR to determine "slot" |
| 103 | information for the processor and the proper microcode update to load. |
| 104 | |
| 105 | @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017) |
| 106 | @param EAX Lower 32-bits of MSR value. |
| 107 | Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER. |
| 108 | @param EDX Upper 32-bits of MSR value. |
| 109 | Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER. |
| 110 | |
| 111 | <b>Example usage</b> |
| 112 | @code |
| 113 | MSR_P6_IA32_PLATFORM_ID_REGISTER Msr; |
| 114 | |
| 115 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID); |
| 116 | @endcode |
| 117 | @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. |
| 118 | **/ |
| 119 | #define MSR_P6_IA32_PLATFORM_ID 0x00000017 |
| 120 | |
| 121 | /** |
| 122 | MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID |
| 123 | **/ |
| 124 | typedef union { |
| 125 | /// |
| 126 | /// Individual bit fields |
| 127 | /// |
| 128 | struct { |
| 129 | UINT32 Reserved1:32; |
| 130 | UINT32 Reserved2:18; |
| 131 | /// |
| 132 | /// [Bits 52:50] Platform Id (R) Contains information concerning the |
| 133 | /// intended platform for the processor. |
| 134 | /// |
| 135 | /// 52 51 50 |
| 136 | /// 0 0 0 Processor Flag 0. |
| 137 | /// 0 0 1 Processor Flag 1 |
| 138 | /// 0 1 0 Processor Flag 2 |
| 139 | /// 0 1 1 Processor Flag 3 |
| 140 | /// 1 0 0 Processor Flag 4 |
| 141 | /// 1 0 1 Processor Flag 5 |
| 142 | /// 1 1 0 Processor Flag 6 |
| 143 | /// 1 1 1 Processor Flag 7 |
| 144 | /// |
| 145 | UINT32 PlatformId:3; |
| 146 | /// |
| 147 | /// [Bits 56:53] L2 Cache Latency Read. |
| 148 | /// |
| 149 | UINT32 L2CacheLatencyRead:4; |
| 150 | UINT32 Reserved3:3; |
| 151 | /// |
| 152 | /// [Bit 60] Clock Frequency Ratio Read. |
| 153 | /// |
| 154 | UINT32 ClockFrequencyRatioRead:1; |
| 155 | UINT32 Reserved4:3; |
| 156 | } Bits; |
| 157 | /// |
| 158 | /// All bit fields as a 64-bit value |
| 159 | /// |
| 160 | UINT64 Uint64; |
| 161 | } MSR_P6_IA32_PLATFORM_ID_REGISTER; |
| 162 | |
| 163 | |
| 164 | /** |
| 165 | Section 10.4.4, "Local APIC Status and Location.". |
| 166 | |
| 167 | @param ECX MSR_P6_APIC_BASE (0x0000001B) |
| 168 | @param EAX Lower 32-bits of MSR value. |
| 169 | Described by the type MSR_P6_APIC_BASE_REGISTER. |
| 170 | @param EDX Upper 32-bits of MSR value. |
| 171 | Described by the type MSR_P6_APIC_BASE_REGISTER. |
| 172 | |
| 173 | <b>Example usage</b> |
| 174 | @code |
| 175 | MSR_P6_APIC_BASE_REGISTER Msr; |
| 176 | |
| 177 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE); |
| 178 | AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64); |
| 179 | @endcode |
| 180 | @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM. |
| 181 | **/ |
| 182 | #define MSR_P6_APIC_BASE 0x0000001B |
| 183 | |
| 184 | /** |
| 185 | MSR information returned for MSR index #MSR_P6_APIC_BASE |
| 186 | **/ |
| 187 | typedef union { |
| 188 | /// |
| 189 | /// Individual bit fields |
| 190 | /// |
| 191 | struct { |
| 192 | UINT32 Reserved1:8; |
| 193 | /// |
| 194 | /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP. |
| 195 | /// |
| 196 | UINT32 BSP:1; |
| 197 | UINT32 Reserved2:2; |
| 198 | /// |
| 199 | /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 = |
| 200 | /// Disabled. |
| 201 | /// |
| 202 | UINT32 EN:1; |
| 203 | /// |
| 204 | /// [Bits 31:12] APIC Base Address. |
| 205 | /// |
| 206 | UINT32 ApicBase:20; |
| 207 | UINT32 Reserved3:32; |
| 208 | } Bits; |
| 209 | /// |
| 210 | /// All bit fields as a 32-bit value |
| 211 | /// |
| 212 | UINT32 Uint32; |
| 213 | /// |
| 214 | /// All bit fields as a 64-bit value |
| 215 | /// |
| 216 | UINT64 Uint64; |
| 217 | } MSR_P6_APIC_BASE_REGISTER; |
| 218 | |
| 219 | |
| 220 | /** |
| 221 | Processor Hard Power-On Configuration (R/W) Enables and disables processor |
| 222 | features; (R) indicates current processor configuration. |
| 223 | |
| 224 | @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A) |
| 225 | @param EAX Lower 32-bits of MSR value. |
| 226 | Described by the type MSR_P6_EBL_CR_POWERON_REGISTER. |
| 227 | @param EDX Upper 32-bits of MSR value. |
| 228 | Described by the type MSR_P6_EBL_CR_POWERON_REGISTER. |
| 229 | |
| 230 | <b>Example usage</b> |
| 231 | @code |
| 232 | MSR_P6_EBL_CR_POWERON_REGISTER Msr; |
| 233 | |
| 234 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON); |
| 235 | AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64); |
| 236 | @endcode |
| 237 | @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM. |
| 238 | **/ |
| 239 | #define MSR_P6_EBL_CR_POWERON 0x0000002A |
| 240 | |
| 241 | /** |
| 242 | MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON |
| 243 | **/ |
| 244 | typedef union { |
| 245 | /// |
| 246 | /// Individual bit fields |
| 247 | /// |
| 248 | struct { |
| 249 | UINT32 Reserved1:1; |
| 250 | /// |
| 251 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled. |
| 252 | /// |
| 253 | UINT32 DataErrorCheckingEnable:1; |
| 254 | /// |
| 255 | /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W) |
| 256 | /// 1 = Enabled 0 = Disabled. |
| 257 | /// |
| 258 | UINT32 ResponseErrorCheckingEnable:1; |
| 259 | /// |
| 260 | /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled. |
| 261 | /// |
| 262 | UINT32 AERR_DriveEnable:1; |
| 263 | /// |
| 264 | /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 = |
| 265 | /// Disabled. |
| 266 | /// |
| 267 | UINT32 BERR_Enable:1; |
| 268 | UINT32 Reserved2:1; |
| 269 | /// |
| 270 | /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 = |
| 271 | /// Enabled 0 = Disabled. |
| 272 | /// |
| 273 | UINT32 BERR_DriverEnable:1; |
| 274 | /// |
| 275 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled. |
| 276 | /// |
| 277 | UINT32 BINIT_DriverEnable:1; |
| 278 | /// |
| 279 | /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled. |
| 280 | /// |
| 281 | UINT32 OutputTriStateEnable:1; |
| 282 | /// |
| 283 | /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled. |
| 284 | /// |
| 285 | UINT32 ExecuteBIST:1; |
| 286 | /// |
| 287 | /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled. |
| 288 | /// |
| 289 | UINT32 AERR_ObservationEnabled:1; |
| 290 | UINT32 Reserved3:1; |
| 291 | /// |
| 292 | /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled. |
| 293 | /// |
| 294 | UINT32 BINIT_ObservationEnabled:1; |
| 295 | /// |
| 296 | /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8. |
| 297 | /// |
| 298 | UINT32 InOrderQueueDepth:1; |
| 299 | /// |
| 300 | /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes. |
| 301 | /// |
| 302 | UINT32 ResetVector:1; |
| 303 | /// |
| 304 | /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled. |
| 305 | /// |
| 306 | UINT32 FRCModeEnable:1; |
| 307 | /// |
| 308 | /// [Bits 17:16] APIC Cluster ID (R). |
| 309 | /// |
| 310 | UINT32 APICClusterID:2; |
| 311 | /// |
| 312 | /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 = |
| 313 | /// 133MHz 11 = Reserved. |
| 314 | /// |
| 315 | UINT32 SystemBusFrequency:2; |
| 316 | /// |
| 317 | /// [Bits 21:20] Symmetric Arbitration ID (R). |
| 318 | /// |
| 319 | UINT32 SymmetricArbitrationID:2; |
| 320 | /// |
| 321 | /// [Bits 25:22] Clock Frequency Ratio (R). |
| 322 | /// |
| 323 | UINT32 ClockFrequencyRatio:4; |
| 324 | /// |
| 325 | /// [Bit 26] Low Power Mode Enable (R/W). |
| 326 | /// |
| 327 | UINT32 LowPowerModeEnable:1; |
| 328 | /// |
| 329 | /// [Bit 27] Clock Frequency Ratio. |
| 330 | /// |
| 331 | UINT32 ClockFrequencyRatio1:1; |
| 332 | UINT32 Reserved4:4; |
| 333 | UINT32 Reserved5:32; |
| 334 | } Bits; |
| 335 | /// |
| 336 | /// All bit fields as a 32-bit value |
| 337 | /// |
| 338 | UINT32 Uint32; |
| 339 | /// |
| 340 | /// All bit fields as a 64-bit value |
| 341 | /// |
| 342 | UINT64 Uint64; |
| 343 | } MSR_P6_EBL_CR_POWERON_REGISTER; |
| 344 | |
| 345 | |
| 346 | /** |
| 347 | Test Control Register. |
| 348 | |
| 349 | @param ECX MSR_P6_TEST_CTL (0x00000033) |
| 350 | @param EAX Lower 32-bits of MSR value. |
| 351 | Described by the type MSR_P6_TEST_CTL_REGISTER. |
| 352 | @param EDX Upper 32-bits of MSR value. |
| 353 | Described by the type MSR_P6_TEST_CTL_REGISTER. |
| 354 | |
| 355 | <b>Example usage</b> |
| 356 | @code |
| 357 | MSR_P6_TEST_CTL_REGISTER Msr; |
| 358 | |
| 359 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL); |
| 360 | AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64); |
| 361 | @endcode |
| 362 | @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM. |
| 363 | **/ |
| 364 | #define MSR_P6_TEST_CTL 0x00000033 |
| 365 | |
| 366 | /** |
| 367 | MSR information returned for MSR index #MSR_P6_TEST_CTL |
| 368 | **/ |
| 369 | typedef union { |
| 370 | /// |
| 371 | /// Individual bit fields |
| 372 | /// |
| 373 | struct { |
| 374 | UINT32 Reserved1:30; |
| 375 | /// |
| 376 | /// [Bit 30] Streaming Buffer Disable. |
| 377 | /// |
| 378 | UINT32 StreamingBufferDisable:1; |
| 379 | /// |
| 380 | /// [Bit 31] Disable LOCK# Assertion for split locked access. |
| 381 | /// |
| 382 | UINT32 Disable_LOCK:1; |
| 383 | UINT32 Reserved2:32; |
| 384 | } Bits; |
| 385 | /// |
| 386 | /// All bit fields as a 32-bit value |
| 387 | /// |
| 388 | UINT32 Uint32; |
| 389 | /// |
| 390 | /// All bit fields as a 64-bit value |
| 391 | /// |
| 392 | UINT64 Uint64; |
| 393 | } MSR_P6_TEST_CTL_REGISTER; |
| 394 | |
| 395 | |
| 396 | /** |
| 397 | BIOS Update Trigger Register. |
| 398 | |
| 399 | @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079) |
| 400 | @param EAX Lower 32-bits of MSR value. |
| 401 | @param EDX Upper 32-bits of MSR value. |
| 402 | |
| 403 | <b>Example usage</b> |
| 404 | @code |
| 405 | UINT64 Msr; |
| 406 | |
| 407 | Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG); |
| 408 | AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr); |
| 409 | @endcode |
| 410 | @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM. |
| 411 | **/ |
| 412 | #define MSR_P6_BIOS_UPDT_TRIG 0x00000079 |
| 413 | |
| 414 | |
| 415 | /** |
| 416 | Chunk n data register D[63:0]: used to write to and read from the L2. |
| 417 | |
| 418 | @param ECX MSR_P6_BBL_CR_Dn |
| 419 | @param EAX Lower 32-bits of MSR value. |
| 420 | @param EDX Upper 32-bits of MSR value. |
| 421 | |
| 422 | <b>Example usage</b> |
| 423 | @code |
| 424 | UINT64 Msr; |
| 425 | |
| 426 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0); |
| 427 | AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr); |
| 428 | @endcode |
| 429 | @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM. |
| 430 | MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM. |
| 431 | MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM. |
| 432 | @{ |
| 433 | **/ |
| 434 | #define MSR_P6_BBL_CR_D0 0x00000088 |
| 435 | #define MSR_P6_BBL_CR_D1 0x00000089 |
| 436 | #define MSR_P6_BBL_CR_D2 0x0000008A |
| 437 | /// @} |
| 438 | |
| 439 | |
| 440 | /** |
| 441 | BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to |
| 442 | write to and read from the L2 depending on the usage model. |
| 443 | |
| 444 | @param ECX MSR_P6_BIOS_SIGN (0x0000008B) |
| 445 | @param EAX Lower 32-bits of MSR value. |
| 446 | @param EDX Upper 32-bits of MSR value. |
| 447 | |
| 448 | <b>Example usage</b> |
| 449 | @code |
| 450 | UINT64 Msr; |
| 451 | |
| 452 | Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN); |
| 453 | AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr); |
| 454 | @endcode |
| 455 | @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM. |
| 456 | **/ |
| 457 | #define MSR_P6_BIOS_SIGN 0x0000008B |
| 458 | |
| 459 | |
| 460 | /** |
| 461 | |
| 462 | |
| 463 | @param ECX MSR_P6_PERFCTR0 (0x000000C1) |
| 464 | @param EAX Lower 32-bits of MSR value. |
| 465 | @param EDX Upper 32-bits of MSR value. |
| 466 | |
| 467 | <b>Example usage</b> |
| 468 | @code |
| 469 | UINT64 Msr; |
| 470 | |
| 471 | Msr = AsmReadMsr64 (MSR_P6_PERFCTR0); |
| 472 | AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr); |
| 473 | @endcode |
| 474 | @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM. |
| 475 | MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM. |
| 476 | @{ |
| 477 | **/ |
| 478 | #define MSR_P6_PERFCTR0 0x000000C1 |
| 479 | #define MSR_P6_PERFCTR1 0x000000C2 |
| 480 | /// @} |
| 481 | |
| 482 | |
| 483 | /** |
| 484 | |
| 485 | |
| 486 | @param ECX MSR_P6_MTRRCAP (0x000000FE) |
| 487 | @param EAX Lower 32-bits of MSR value. |
| 488 | @param EDX Upper 32-bits of MSR value. |
| 489 | |
| 490 | <b>Example usage</b> |
| 491 | @code |
| 492 | UINT64 Msr; |
| 493 | |
| 494 | Msr = AsmReadMsr64 (MSR_P6_MTRRCAP); |
| 495 | AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr); |
| 496 | @endcode |
| 497 | @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM. |
| 498 | **/ |
| 499 | #define MSR_P6_MTRRCAP 0x000000FE |
| 500 | |
| 501 | |
| 502 | /** |
| 503 | Address register: used to send specified address (A31-A3) to L2 during cache |
| 504 | initialization accesses. |
| 505 | |
| 506 | @param ECX MSR_P6_BBL_CR_ADDR (0x00000116) |
| 507 | @param EAX Lower 32-bits of MSR value. |
| 508 | Described by the type MSR_P6_BBL_CR_ADDR_REGISTER. |
| 509 | @param EDX Upper 32-bits of MSR value. |
| 510 | Described by the type MSR_P6_BBL_CR_ADDR_REGISTER. |
| 511 | |
| 512 | <b>Example usage</b> |
| 513 | @code |
| 514 | MSR_P6_BBL_CR_ADDR_REGISTER Msr; |
| 515 | |
| 516 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR); |
| 517 | AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64); |
| 518 | @endcode |
| 519 | @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM. |
| 520 | **/ |
| 521 | #define MSR_P6_BBL_CR_ADDR 0x00000116 |
| 522 | |
| 523 | /** |
| 524 | MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR |
| 525 | **/ |
| 526 | typedef union { |
| 527 | /// |
| 528 | /// Individual bit fields |
| 529 | /// |
| 530 | struct { |
| 531 | UINT32 Reserved1:3; |
| 532 | /// |
| 533 | /// [Bits 31:3] Address bits |
| 534 | /// |
| 535 | UINT32 Address:29; |
| 536 | UINT32 Reserved2:32; |
| 537 | } Bits; |
| 538 | /// |
| 539 | /// All bit fields as a 32-bit value |
| 540 | /// |
| 541 | UINT32 Uint32; |
| 542 | /// |
| 543 | /// All bit fields as a 64-bit value |
| 544 | /// |
| 545 | UINT64 Uint64; |
| 546 | } MSR_P6_BBL_CR_ADDR_REGISTER; |
| 547 | |
| 548 | |
| 549 | /** |
| 550 | Data ECC register D[7:0]: used to write ECC and read ECC to/from L2. |
| 551 | |
| 552 | @param ECX MSR_P6_BBL_CR_DECC (0x00000118) |
| 553 | @param EAX Lower 32-bits of MSR value. |
| 554 | @param EDX Upper 32-bits of MSR value. |
| 555 | |
| 556 | <b>Example usage</b> |
| 557 | @code |
| 558 | UINT64 Msr; |
| 559 | |
| 560 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC); |
| 561 | AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr); |
| 562 | @endcode |
| 563 | @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM. |
| 564 | **/ |
| 565 | #define MSR_P6_BBL_CR_DECC 0x00000118 |
| 566 | |
| 567 | |
| 568 | /** |
| 569 | Control register: used to program L2 commands to be issued via cache |
| 570 | configuration accesses mechanism. Also receives L2 lookup response. |
| 571 | |
| 572 | @param ECX MSR_P6_BBL_CR_CTL (0x00000119) |
| 573 | @param EAX Lower 32-bits of MSR value. |
| 574 | Described by the type MSR_P6_BBL_CR_CTL_REGISTER. |
| 575 | @param EDX Upper 32-bits of MSR value. |
| 576 | Described by the type MSR_P6_BBL_CR_CTL_REGISTER. |
| 577 | |
| 578 | <b>Example usage</b> |
| 579 | @code |
| 580 | MSR_P6_BBL_CR_CTL_REGISTER Msr; |
| 581 | |
| 582 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL); |
| 583 | AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64); |
| 584 | @endcode |
| 585 | @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM. |
| 586 | **/ |
| 587 | #define MSR_P6_BBL_CR_CTL 0x00000119 |
| 588 | |
| 589 | /** |
| 590 | MSR information returned for MSR index #MSR_P6_BBL_CR_CTL |
| 591 | **/ |
| 592 | typedef union { |
| 593 | /// |
| 594 | /// Individual bit fields |
| 595 | /// |
| 596 | struct { |
| 597 | /// |
| 598 | /// [Bits 4:0] L2 Command |
| 599 | /// Data Read w/ LRU update (RLU) |
| 600 | /// Tag Read w/ Data Read (TRR) |
| 601 | /// Tag Inquire (TI) |
| 602 | /// L2 Control Register Read (CR) |
| 603 | /// L2 Control Register Write (CW) |
| 604 | /// Tag Write w/ Data Read (TWR) |
| 605 | /// Tag Write w/ Data Write (TWW) |
| 606 | /// Tag Write (TW). |
| 607 | /// |
| 608 | UINT32 L2Command:5; |
| 609 | /// |
| 610 | /// [Bits 6:5] State to L2 |
| 611 | /// |
| 612 | UINT32 StateToL2:2; |
| 613 | UINT32 Reserved:1; |
| 614 | /// |
| 615 | /// [Bits 9:8] Way to L2. |
| 616 | /// |
| 617 | UINT32 WayToL2:2; |
| 618 | /// |
| 619 | /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11. |
| 620 | /// |
| 621 | UINT32 Way:2; |
| 622 | /// |
| 623 | /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00. |
| 624 | /// |
| 625 | UINT32 MESI:2; |
| 626 | /// |
| 627 | /// [Bits 15:14] State from L2. |
| 628 | /// |
| 629 | UINT32 StateFromL2:2; |
| 630 | UINT32 Reserved2:1; |
| 631 | /// |
| 632 | /// [Bit 17] L2 Hit. |
| 633 | /// |
| 634 | UINT32 L2Hit:1; |
| 635 | UINT32 Reserved3:1; |
| 636 | /// |
| 637 | /// [Bits 20:19] User supplied ECC. |
| 638 | /// |
| 639 | UINT32 UserEcc:2; |
| 640 | /// |
| 641 | /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved. |
| 642 | /// |
| 643 | UINT32 ProcessorNumber:1; |
| 644 | UINT32 Reserved4:10; |
| 645 | UINT32 Reserved5:32; |
| 646 | } Bits; |
| 647 | /// |
| 648 | /// All bit fields as a 32-bit value |
| 649 | /// |
| 650 | UINT32 Uint32; |
| 651 | /// |
| 652 | /// All bit fields as a 64-bit value |
| 653 | /// |
| 654 | UINT64 Uint64; |
| 655 | } MSR_P6_BBL_CR_CTL_REGISTER; |
| 656 | |
| 657 | |
| 658 | /** |
| 659 | Trigger register: used to initiate a cache configuration accesses access, |
| 660 | Write only with Data = 0. |
| 661 | |
| 662 | @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A) |
| 663 | @param EAX Lower 32-bits of MSR value. |
| 664 | @param EDX Upper 32-bits of MSR value. |
| 665 | |
| 666 | <b>Example usage</b> |
| 667 | @code |
| 668 | UINT64 Msr; |
| 669 | |
| 670 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG); |
| 671 | AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr); |
| 672 | @endcode |
| 673 | @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM. |
| 674 | **/ |
| 675 | #define MSR_P6_BBL_CR_TRIG 0x0000011A |
| 676 | |
| 677 | |
| 678 | /** |
| 679 | Busy register: indicates when a cache configuration accesses L2 command is |
| 680 | in progress. D[0] = 1 = BUSY. |
| 681 | |
| 682 | @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B) |
| 683 | @param EAX Lower 32-bits of MSR value. |
| 684 | @param EDX Upper 32-bits of MSR value. |
| 685 | |
| 686 | <b>Example usage</b> |
| 687 | @code |
| 688 | UINT64 Msr; |
| 689 | |
| 690 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY); |
| 691 | AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr); |
| 692 | @endcode |
| 693 | @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM. |
| 694 | **/ |
| 695 | #define MSR_P6_BBL_CR_BUSY 0x0000011B |
| 696 | |
| 697 | |
| 698 | /** |
| 699 | Control register 3: used to configure the L2 Cache. |
| 700 | |
| 701 | @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E) |
| 702 | @param EAX Lower 32-bits of MSR value. |
| 703 | Described by the type MSR_P6_BBL_CR_CTL3_REGISTER. |
| 704 | @param EDX Upper 32-bits of MSR value. |
| 705 | Described by the type MSR_P6_BBL_CR_CTL3_REGISTER. |
| 706 | |
| 707 | <b>Example usage</b> |
| 708 | @code |
| 709 | MSR_P6_BBL_CR_CTL3_REGISTER Msr; |
| 710 | |
| 711 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3); |
| 712 | AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64); |
| 713 | @endcode |
| 714 | @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM. |
| 715 | **/ |
| 716 | #define MSR_P6_BBL_CR_CTL3 0x0000011E |
| 717 | |
| 718 | /** |
| 719 | MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3 |
| 720 | **/ |
| 721 | typedef union { |
| 722 | /// |
| 723 | /// Individual bit fields |
| 724 | /// |
| 725 | struct { |
| 726 | /// |
| 727 | /// [Bit 0] L2 Configured (read/write ). |
| 728 | /// |
| 729 | UINT32 L2Configured:1; |
| 730 | /// |
| 731 | /// [Bits 4:1] L2 Cache Latency (read/write). |
| 732 | /// |
| 733 | UINT32 L2CacheLatency:4; |
| 734 | /// |
| 735 | /// [Bit 5] ECC Check Enable (read/write). |
| 736 | /// |
| 737 | UINT32 ECCCheckEnable:1; |
| 738 | /// |
| 739 | /// [Bit 6] Address Parity Check Enable (read/write). |
| 740 | /// |
| 741 | UINT32 AddressParityCheckEnable:1; |
| 742 | /// |
| 743 | /// [Bit 7] CRTN Parity Check Enable (read/write). |
| 744 | /// |
| 745 | UINT32 CRTNParityCheckEnable:1; |
| 746 | /// |
| 747 | /// [Bit 8] L2 Enabled (read/write). |
| 748 | /// |
| 749 | UINT32 L2Enabled:1; |
| 750 | /// |
| 751 | /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way |
| 752 | /// Reserved. |
| 753 | /// |
| 754 | UINT32 L2Associativity:2; |
| 755 | /// |
| 756 | /// [Bits 12:11] Number of L2 banks (read only). |
| 757 | /// |
| 758 | UINT32 L2Banks:2; |
| 759 | /// |
| 760 | /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes |
| 761 | /// 1MByte 2MByte 4MBytes. |
| 762 | /// |
| 763 | UINT32 CacheSizePerBank:5; |
| 764 | /// |
| 765 | /// [Bit 18] Cache State error checking enable (read/write). |
| 766 | /// |
| 767 | UINT32 CacheStateErrorEnable:1; |
| 768 | UINT32 Reserved1:1; |
| 769 | /// |
| 770 | /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes |
| 771 | /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes. |
| 772 | /// |
| 773 | UINT32 L2AddressRange:3; |
| 774 | /// |
| 775 | /// [Bit 23] L2 Hardware Disable (read only). |
| 776 | /// |
| 777 | UINT32 L2HardwareDisable:1; |
| 778 | UINT32 Reserved2:1; |
| 779 | /// |
| 780 | /// [Bit 25] Cache bus fraction (read only). |
| 781 | /// |
| 782 | UINT32 CacheBusFraction:1; |
| 783 | UINT32 Reserved3:6; |
| 784 | UINT32 Reserved4:32; |
| 785 | } Bits; |
| 786 | /// |
| 787 | /// All bit fields as a 32-bit value |
| 788 | /// |
| 789 | UINT32 Uint32; |
| 790 | /// |
| 791 | /// All bit fields as a 64-bit value |
| 792 | /// |
| 793 | UINT64 Uint64; |
| 794 | } MSR_P6_BBL_CR_CTL3_REGISTER; |
| 795 | |
| 796 | |
| 797 | /** |
| 798 | CS register target for CPL 0 code. |
| 799 | |
| 800 | @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174) |
| 801 | @param EAX Lower 32-bits of MSR value. |
| 802 | @param EDX Upper 32-bits of MSR value. |
| 803 | |
| 804 | <b>Example usage</b> |
| 805 | @code |
| 806 | UINT64 Msr; |
| 807 | |
| 808 | Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR); |
| 809 | AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr); |
| 810 | @endcode |
| 811 | @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM. |
| 812 | **/ |
| 813 | #define MSR_P6_SYSENTER_CS_MSR 0x00000174 |
| 814 | |
| 815 | |
| 816 | /** |
| 817 | Stack pointer for CPL 0 stack. |
| 818 | |
| 819 | @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175) |
| 820 | @param EAX Lower 32-bits of MSR value. |
| 821 | @param EDX Upper 32-bits of MSR value. |
| 822 | |
| 823 | <b>Example usage</b> |
| 824 | @code |
| 825 | UINT64 Msr; |
| 826 | |
| 827 | Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR); |
| 828 | AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr); |
| 829 | @endcode |
| 830 | @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM. |
| 831 | **/ |
| 832 | #define MSR_P6_SYSENTER_ESP_MSR 0x00000175 |
| 833 | |
| 834 | |
| 835 | /** |
| 836 | CPL 0 code entry point. |
| 837 | |
| 838 | @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176) |
| 839 | @param EAX Lower 32-bits of MSR value. |
| 840 | @param EDX Upper 32-bits of MSR value. |
| 841 | |
| 842 | <b>Example usage</b> |
| 843 | @code |
| 844 | UINT64 Msr; |
| 845 | |
| 846 | Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR); |
| 847 | AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr); |
| 848 | @endcode |
| 849 | @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM. |
| 850 | **/ |
| 851 | #define MSR_P6_SYSENTER_EIP_MSR 0x00000176 |
| 852 | |
| 853 | |
| 854 | /** |
| 855 | |
| 856 | |
| 857 | @param ECX MSR_P6_MCG_CAP (0x00000179) |
| 858 | @param EAX Lower 32-bits of MSR value. |
| 859 | @param EDX Upper 32-bits of MSR value. |
| 860 | |
| 861 | <b>Example usage</b> |
| 862 | @code |
| 863 | UINT64 Msr; |
| 864 | |
| 865 | Msr = AsmReadMsr64 (MSR_P6_MCG_CAP); |
| 866 | AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr); |
| 867 | @endcode |
| 868 | @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM. |
| 869 | **/ |
| 870 | #define MSR_P6_MCG_CAP 0x00000179 |
| 871 | |
| 872 | |
| 873 | /** |
| 874 | |
| 875 | |
| 876 | @param ECX MSR_P6_MCG_STATUS (0x0000017A) |
| 877 | @param EAX Lower 32-bits of MSR value. |
| 878 | @param EDX Upper 32-bits of MSR value. |
| 879 | |
| 880 | <b>Example usage</b> |
| 881 | @code |
| 882 | UINT64 Msr; |
| 883 | |
| 884 | Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS); |
| 885 | AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr); |
| 886 | @endcode |
| 887 | @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM. |
| 888 | **/ |
| 889 | #define MSR_P6_MCG_STATUS 0x0000017A |
| 890 | |
| 891 | |
| 892 | /** |
| 893 | |
| 894 | |
| 895 | @param ECX MSR_P6_MCG_CTL (0x0000017B) |
| 896 | @param EAX Lower 32-bits of MSR value. |
| 897 | @param EDX Upper 32-bits of MSR value. |
| 898 | |
| 899 | <b>Example usage</b> |
| 900 | @code |
| 901 | UINT64 Msr; |
| 902 | |
| 903 | Msr = AsmReadMsr64 (MSR_P6_MCG_CTL); |
| 904 | AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr); |
| 905 | @endcode |
| 906 | @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM. |
| 907 | **/ |
| 908 | #define MSR_P6_MCG_CTL 0x0000017B |
| 909 | |
| 910 | |
| 911 | /** |
| 912 | |
| 913 | |
| 914 | @param ECX MSR_P6_PERFEVTSELn |
| 915 | @param EAX Lower 32-bits of MSR value. |
| 916 | Described by the type MSR_P6_PERFEVTSEL_REGISTER. |
| 917 | @param EDX Upper 32-bits of MSR value. |
| 918 | Described by the type MSR_P6_PERFEVTSEL_REGISTER. |
| 919 | |
| 920 | <b>Example usage</b> |
| 921 | @code |
| 922 | MSR_P6_PERFEVTSEL_REGISTER Msr; |
| 923 | |
| 924 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0); |
| 925 | AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64); |
| 926 | @endcode |
| 927 | @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM. |
| 928 | MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM. |
| 929 | @{ |
| 930 | **/ |
| 931 | #define MSR_P6_PERFEVTSEL0 0x00000186 |
| 932 | #define MSR_P6_PERFEVTSEL1 0x00000187 |
| 933 | /// @} |
| 934 | |
| 935 | /** |
| 936 | MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and |
| 937 | #MSR_P6_PERFEVTSEL1. |
| 938 | **/ |
| 939 | typedef union { |
| 940 | /// |
| 941 | /// Individual bit fields |
| 942 | /// |
| 943 | struct { |
| 944 | /// |
| 945 | /// [Bits 7:0] Event Select Refer to Performance Counter section for a |
| 946 | /// list of event encodings. |
| 947 | /// |
| 948 | UINT32 EventSelect:8; |
| 949 | /// |
| 950 | /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable |
| 951 | /// all count options. |
| 952 | /// |
| 953 | UINT32 UMASK:8; |
| 954 | /// |
| 955 | /// [Bit 16] USER Controls the counting of events at Privilege levels of |
| 956 | /// 1, 2, and 3. |
| 957 | /// |
| 958 | UINT32 USR:1; |
| 959 | /// |
| 960 | /// [Bit 17] OS Controls the counting of events at Privilege level of 0. |
| 961 | /// |
| 962 | UINT32 OS:1; |
| 963 | /// |
| 964 | /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration. |
| 965 | /// |
| 966 | UINT32 E:1; |
| 967 | /// |
| 968 | /// [Bit 19] PC Enabled the signaling of performance counter overflow via |
| 969 | /// BP0 pin. |
| 970 | /// |
| 971 | UINT32 PC:1; |
| 972 | /// |
| 973 | /// [Bit 20] INT Enables the signaling of counter overflow via input to |
| 974 | /// APIC 1 = Enable 0 = Disable. |
| 975 | /// |
| 976 | UINT32 INT:1; |
| 977 | UINT32 Reserved1:1; |
| 978 | /// |
| 979 | /// [Bit 22] ENABLE Enables the counting of performance events in both |
| 980 | /// counters 1 = Enable 0 = Disable. |
| 981 | /// |
| 982 | UINT32 EN:1; |
| 983 | /// |
| 984 | /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0 |
| 985 | /// = Non-Inverted. |
| 986 | /// |
| 987 | UINT32 INV:1; |
| 988 | /// |
| 989 | /// [Bits 31:24] CMASK (Counter Mask). |
| 990 | /// |
| 991 | UINT32 CMASK:8; |
| 992 | UINT32 Reserved2:32; |
| 993 | } Bits; |
| 994 | /// |
| 995 | /// All bit fields as a 32-bit value |
| 996 | /// |
| 997 | UINT32 Uint32; |
| 998 | /// |
| 999 | /// All bit fields as a 64-bit value |
| 1000 | /// |
| 1001 | UINT64 Uint64; |
| 1002 | } MSR_P6_PERFEVTSEL_REGISTER; |
| 1003 | |
| 1004 | |
| 1005 | /** |
| 1006 | |
| 1007 | |
| 1008 | @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9) |
| 1009 | @param EAX Lower 32-bits of MSR value. |
| 1010 | Described by the type MSR_P6_DEBUGCTLMSR_REGISTER. |
| 1011 | @param EDX Upper 32-bits of MSR value. |
| 1012 | Described by the type MSR_P6_DEBUGCTLMSR_REGISTER. |
| 1013 | |
| 1014 | <b>Example usage</b> |
| 1015 | @code |
| 1016 | MSR_P6_DEBUGCTLMSR_REGISTER Msr; |
| 1017 | |
| 1018 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR); |
| 1019 | AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64); |
| 1020 | @endcode |
| 1021 | @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM. |
| 1022 | **/ |
| 1023 | #define MSR_P6_DEBUGCTLMSR 0x000001D9 |
| 1024 | |
| 1025 | /** |
| 1026 | MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR |
| 1027 | **/ |
| 1028 | typedef union { |
| 1029 | /// |
| 1030 | /// Individual bit fields |
| 1031 | /// |
| 1032 | struct { |
| 1033 | /// |
| 1034 | /// [Bit 0] Enable/Disable Last Branch Records. |
| 1035 | /// |
| 1036 | UINT32 LBR:1; |
| 1037 | /// |
| 1038 | /// [Bit 1] Branch Trap Flag. |
| 1039 | /// |
| 1040 | UINT32 BTF:1; |
| 1041 | /// |
| 1042 | /// [Bit 2] Performance Monitoring/Break Point Pins. |
| 1043 | /// |
| 1044 | UINT32 PB0:1; |
| 1045 | /// |
| 1046 | /// [Bit 3] Performance Monitoring/Break Point Pins. |
| 1047 | /// |
| 1048 | UINT32 PB1:1; |
| 1049 | /// |
| 1050 | /// [Bit 4] Performance Monitoring/Break Point Pins. |
| 1051 | /// |
| 1052 | UINT32 PB2:1; |
| 1053 | /// |
| 1054 | /// [Bit 5] Performance Monitoring/Break Point Pins. |
| 1055 | /// |
| 1056 | UINT32 PB3:1; |
| 1057 | /// |
| 1058 | /// [Bit 6] Enable/Disable Execution Trace Messages. |
| 1059 | /// |
| 1060 | UINT32 TR:1; |
| 1061 | UINT32 Reserved1:25; |
| 1062 | UINT32 Reserved2:32; |
| 1063 | } Bits; |
| 1064 | /// |
| 1065 | /// All bit fields as a 32-bit value |
| 1066 | /// |
| 1067 | UINT32 Uint32; |
| 1068 | /// |
| 1069 | /// All bit fields as a 64-bit value |
| 1070 | /// |
| 1071 | UINT64 Uint64; |
| 1072 | } MSR_P6_DEBUGCTLMSR_REGISTER; |
| 1073 | |
| 1074 | |
| 1075 | /** |
| 1076 | |
| 1077 | |
| 1078 | @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB) |
| 1079 | @param EAX Lower 32-bits of MSR value. |
| 1080 | @param EDX Upper 32-bits of MSR value. |
| 1081 | |
| 1082 | <b>Example usage</b> |
| 1083 | @code |
| 1084 | UINT64 Msr; |
| 1085 | |
| 1086 | Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP); |
| 1087 | AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr); |
| 1088 | @endcode |
| 1089 | @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM. |
| 1090 | **/ |
| 1091 | #define MSR_P6_LASTBRANCHFROMIP 0x000001DB |
| 1092 | |
| 1093 | |
| 1094 | /** |
| 1095 | |
| 1096 | |
| 1097 | @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC) |
| 1098 | @param EAX Lower 32-bits of MSR value. |
| 1099 | @param EDX Upper 32-bits of MSR value. |
| 1100 | |
| 1101 | <b>Example usage</b> |
| 1102 | @code |
| 1103 | UINT64 Msr; |
| 1104 | |
| 1105 | Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP); |
| 1106 | AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr); |
| 1107 | @endcode |
| 1108 | @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM. |
| 1109 | **/ |
| 1110 | #define MSR_P6_LASTBRANCHTOIP 0x000001DC |
| 1111 | |
| 1112 | |
| 1113 | /** |
| 1114 | |
| 1115 | |
| 1116 | @param ECX MSR_P6_LASTINTFROMIP (0x000001DD) |
| 1117 | @param EAX Lower 32-bits of MSR value. |
| 1118 | @param EDX Upper 32-bits of MSR value. |
| 1119 | |
| 1120 | <b>Example usage</b> |
| 1121 | @code |
| 1122 | UINT64 Msr; |
| 1123 | |
| 1124 | Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP); |
| 1125 | AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr); |
| 1126 | @endcode |
| 1127 | @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM. |
| 1128 | **/ |
| 1129 | #define MSR_P6_LASTINTFROMIP 0x000001DD |
| 1130 | |
| 1131 | |
| 1132 | /** |
| 1133 | |
| 1134 | |
| 1135 | @param ECX MSR_P6_LASTINTTOIP (0x000001DE) |
| 1136 | @param EAX Lower 32-bits of MSR value. |
| 1137 | @param EDX Upper 32-bits of MSR value. |
| 1138 | |
| 1139 | <b>Example usage</b> |
| 1140 | @code |
| 1141 | UINT64 Msr; |
| 1142 | |
| 1143 | Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP); |
| 1144 | AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr); |
| 1145 | @endcode |
| 1146 | @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM. |
| 1147 | **/ |
| 1148 | #define MSR_P6_LASTINTTOIP 0x000001DE |
| 1149 | |
| 1150 | /** |
| 1151 | |
| 1152 | |
| 1153 | @param ECX MSR_P6_MTRRPHYSBASEn |
| 1154 | @param EAX Lower 32-bits of MSR value. |
| 1155 | @param EDX Upper 32-bits of MSR value. |
| 1156 | |
| 1157 | <b>Example usage</b> |
| 1158 | @code |
| 1159 | UINT64 Msr; |
| 1160 | |
| 1161 | Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0); |
| 1162 | AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr); |
| 1163 | @endcode |
| 1164 | @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. |
| 1165 | MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. |
| 1166 | MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. |
| 1167 | MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. |
| 1168 | MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. |
| 1169 | MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. |
| 1170 | MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. |
| 1171 | MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM. |
| 1172 | @{ |
| 1173 | **/ |
| 1174 | #define MSR_P6_MTRRPHYSBASE0 0x00000200 |
| 1175 | #define MSR_P6_MTRRPHYSBASE1 0x00000202 |
| 1176 | #define MSR_P6_MTRRPHYSBASE2 0x00000204 |
| 1177 | #define MSR_P6_MTRRPHYSBASE3 0x00000206 |
| 1178 | #define MSR_P6_MTRRPHYSBASE4 0x00000208 |
| 1179 | #define MSR_P6_MTRRPHYSBASE5 0x0000020A |
| 1180 | #define MSR_P6_MTRRPHYSBASE6 0x0000020C |
| 1181 | #define MSR_P6_MTRRPHYSBASE7 0x0000020E |
| 1182 | /// @} |
| 1183 | |
| 1184 | |
| 1185 | /** |
| 1186 | |
| 1187 | |
| 1188 | @param ECX MSR_P6_MTRRPHYSMASKn |
| 1189 | @param EAX Lower 32-bits of MSR value. |
| 1190 | @param EDX Upper 32-bits of MSR value. |
| 1191 | |
| 1192 | <b>Example usage</b> |
| 1193 | @code |
| 1194 | UINT64 Msr; |
| 1195 | |
| 1196 | Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0); |
| 1197 | AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr); |
| 1198 | @endcode |
| 1199 | @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. |
| 1200 | MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. |
| 1201 | MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. |
| 1202 | MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. |
| 1203 | MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. |
| 1204 | MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. |
| 1205 | MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. |
| 1206 | MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM. |
| 1207 | @{ |
| 1208 | **/ |
| 1209 | #define MSR_P6_MTRRPHYSMASK0 0x00000201 |
| 1210 | #define MSR_P6_MTRRPHYSMASK1 0x00000203 |
| 1211 | #define MSR_P6_MTRRPHYSMASK2 0x00000205 |
| 1212 | #define MSR_P6_MTRRPHYSMASK3 0x00000207 |
| 1213 | #define MSR_P6_MTRRPHYSMASK4 0x00000209 |
| 1214 | #define MSR_P6_MTRRPHYSMASK5 0x0000020B |
| 1215 | #define MSR_P6_MTRRPHYSMASK6 0x0000020D |
| 1216 | #define MSR_P6_MTRRPHYSMASK7 0x0000020F |
| 1217 | /// @} |
| 1218 | |
| 1219 | |
| 1220 | /** |
| 1221 | |
| 1222 | |
| 1223 | @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250) |
| 1224 | @param EAX Lower 32-bits of MSR value. |
| 1225 | @param EDX Upper 32-bits of MSR value. |
| 1226 | |
| 1227 | <b>Example usage</b> |
| 1228 | @code |
| 1229 | UINT64 Msr; |
| 1230 | |
| 1231 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000); |
| 1232 | AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr); |
| 1233 | @endcode |
| 1234 | @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM. |
| 1235 | **/ |
| 1236 | #define MSR_P6_MTRRFIX64K_00000 0x00000250 |
| 1237 | |
| 1238 | |
| 1239 | /** |
| 1240 | |
| 1241 | |
| 1242 | @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258) |
| 1243 | @param EAX Lower 32-bits of MSR value. |
| 1244 | @param EDX Upper 32-bits of MSR value. |
| 1245 | |
| 1246 | <b>Example usage</b> |
| 1247 | @code |
| 1248 | UINT64 Msr; |
| 1249 | |
| 1250 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000); |
| 1251 | AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr); |
| 1252 | @endcode |
| 1253 | @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM. |
| 1254 | **/ |
| 1255 | #define MSR_P6_MTRRFIX16K_80000 0x00000258 |
| 1256 | |
| 1257 | |
| 1258 | /** |
| 1259 | |
| 1260 | |
| 1261 | @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259) |
| 1262 | @param EAX Lower 32-bits of MSR value. |
| 1263 | @param EDX Upper 32-bits of MSR value. |
| 1264 | |
| 1265 | <b>Example usage</b> |
| 1266 | @code |
| 1267 | UINT64 Msr; |
| 1268 | |
| 1269 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000); |
| 1270 | AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr); |
| 1271 | @endcode |
| 1272 | @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM. |
| 1273 | **/ |
| 1274 | #define MSR_P6_MTRRFIX16K_A0000 0x00000259 |
| 1275 | |
| 1276 | |
| 1277 | /** |
| 1278 | |
| 1279 | |
| 1280 | @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268) |
| 1281 | @param EAX Lower 32-bits of MSR value. |
| 1282 | @param EDX Upper 32-bits of MSR value. |
| 1283 | |
| 1284 | <b>Example usage</b> |
| 1285 | @code |
| 1286 | UINT64 Msr; |
| 1287 | |
| 1288 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000); |
| 1289 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr); |
| 1290 | @endcode |
| 1291 | @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM. |
| 1292 | **/ |
| 1293 | #define MSR_P6_MTRRFIX4K_C0000 0x00000268 |
| 1294 | |
| 1295 | |
| 1296 | /** |
| 1297 | |
| 1298 | |
| 1299 | @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269) |
| 1300 | @param EAX Lower 32-bits of MSR value. |
| 1301 | @param EDX Upper 32-bits of MSR value. |
| 1302 | |
| 1303 | <b>Example usage</b> |
| 1304 | @code |
| 1305 | UINT64 Msr; |
| 1306 | |
| 1307 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000); |
| 1308 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr); |
| 1309 | @endcode |
| 1310 | @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM. |
| 1311 | **/ |
| 1312 | #define MSR_P6_MTRRFIX4K_C8000 0x00000269 |
| 1313 | |
| 1314 | |
| 1315 | /** |
| 1316 | |
| 1317 | |
| 1318 | @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A) |
| 1319 | @param EAX Lower 32-bits of MSR value. |
| 1320 | @param EDX Upper 32-bits of MSR value. |
| 1321 | |
| 1322 | <b>Example usage</b> |
| 1323 | @code |
| 1324 | UINT64 Msr; |
| 1325 | |
| 1326 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000); |
| 1327 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr); |
| 1328 | @endcode |
| 1329 | @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM. |
| 1330 | **/ |
| 1331 | #define MSR_P6_MTRRFIX4K_D0000 0x0000026A |
| 1332 | |
| 1333 | |
| 1334 | /** |
| 1335 | |
| 1336 | |
| 1337 | @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B) |
| 1338 | @param EAX Lower 32-bits of MSR value. |
| 1339 | @param EDX Upper 32-bits of MSR value. |
| 1340 | |
| 1341 | <b>Example usage</b> |
| 1342 | @code |
| 1343 | UINT64 Msr; |
| 1344 | |
| 1345 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000); |
| 1346 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr); |
| 1347 | @endcode |
| 1348 | @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM. |
| 1349 | **/ |
| 1350 | #define MSR_P6_MTRRFIX4K_D8000 0x0000026B |
| 1351 | |
| 1352 | |
| 1353 | /** |
| 1354 | |
| 1355 | |
| 1356 | @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C) |
| 1357 | @param EAX Lower 32-bits of MSR value. |
| 1358 | @param EDX Upper 32-bits of MSR value. |
| 1359 | |
| 1360 | <b>Example usage</b> |
| 1361 | @code |
| 1362 | UINT64 Msr; |
| 1363 | |
| 1364 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000); |
| 1365 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr); |
| 1366 | @endcode |
| 1367 | @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM. |
| 1368 | **/ |
| 1369 | #define MSR_P6_MTRRFIX4K_E0000 0x0000026C |
| 1370 | |
| 1371 | |
| 1372 | /** |
| 1373 | |
| 1374 | |
| 1375 | @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D) |
| 1376 | @param EAX Lower 32-bits of MSR value. |
| 1377 | @param EDX Upper 32-bits of MSR value. |
| 1378 | |
| 1379 | <b>Example usage</b> |
| 1380 | @code |
| 1381 | UINT64 Msr; |
| 1382 | |
| 1383 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000); |
| 1384 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr); |
| 1385 | @endcode |
| 1386 | @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM. |
| 1387 | **/ |
| 1388 | #define MSR_P6_MTRRFIX4K_E8000 0x0000026D |
| 1389 | |
| 1390 | |
| 1391 | /** |
| 1392 | |
| 1393 | |
| 1394 | @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E) |
| 1395 | @param EAX Lower 32-bits of MSR value. |
| 1396 | @param EDX Upper 32-bits of MSR value. |
| 1397 | |
| 1398 | <b>Example usage</b> |
| 1399 | @code |
| 1400 | UINT64 Msr; |
| 1401 | |
| 1402 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000); |
| 1403 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr); |
| 1404 | @endcode |
| 1405 | @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM. |
| 1406 | **/ |
| 1407 | #define MSR_P6_MTRRFIX4K_F0000 0x0000026E |
| 1408 | |
| 1409 | |
| 1410 | /** |
| 1411 | |
| 1412 | |
| 1413 | @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F) |
| 1414 | @param EAX Lower 32-bits of MSR value. |
| 1415 | @param EDX Upper 32-bits of MSR value. |
| 1416 | |
| 1417 | <b>Example usage</b> |
| 1418 | @code |
| 1419 | UINT64 Msr; |
| 1420 | |
| 1421 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000); |
| 1422 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr); |
| 1423 | @endcode |
| 1424 | @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM. |
| 1425 | **/ |
| 1426 | #define MSR_P6_MTRRFIX4K_F8000 0x0000026F |
| 1427 | |
| 1428 | |
| 1429 | /** |
| 1430 | |
| 1431 | |
| 1432 | @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF) |
| 1433 | @param EAX Lower 32-bits of MSR value. |
| 1434 | Described by the type MSR_P6_MTRRDEFTYPE_REGISTER. |
| 1435 | @param EDX Upper 32-bits of MSR value. |
| 1436 | Described by the type MSR_P6_MTRRDEFTYPE_REGISTER. |
| 1437 | |
| 1438 | <b>Example usage</b> |
| 1439 | @code |
| 1440 | MSR_P6_MTRRDEFTYPE_REGISTER Msr; |
| 1441 | |
| 1442 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE); |
| 1443 | AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64); |
| 1444 | @endcode |
| 1445 | @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM. |
| 1446 | **/ |
| 1447 | #define MSR_P6_MTRRDEFTYPE 0x000002FF |
| 1448 | |
| 1449 | /** |
| 1450 | MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE |
| 1451 | **/ |
| 1452 | typedef union { |
| 1453 | /// |
| 1454 | /// Individual bit fields |
| 1455 | /// |
| 1456 | struct { |
| 1457 | /// |
| 1458 | /// [Bits 2:0] Default memory type. |
| 1459 | /// |
| 1460 | UINT32 Type:3; |
| 1461 | UINT32 Reserved1:7; |
| 1462 | /// |
| 1463 | /// [Bit 10] Fixed MTRR enable. |
| 1464 | /// |
| 1465 | UINT32 FE:1; |
| 1466 | /// |
| 1467 | /// [Bit 11] MTRR Enable. |
| 1468 | /// |
| 1469 | UINT32 E:1; |
| 1470 | UINT32 Reserved2:20; |
| 1471 | UINT32 Reserved3:32; |
| 1472 | } Bits; |
| 1473 | /// |
| 1474 | /// All bit fields as a 32-bit value |
| 1475 | /// |
| 1476 | UINT32 Uint32; |
| 1477 | /// |
| 1478 | /// All bit fields as a 64-bit value |
| 1479 | /// |
| 1480 | UINT64 Uint64; |
| 1481 | } MSR_P6_MTRRDEFTYPE_REGISTER; |
| 1482 | |
| 1483 | |
| 1484 | /** |
| 1485 | |
| 1486 | |
| 1487 | @param ECX MSR_P6_MC0_CTL (0x00000400) |
| 1488 | @param EAX Lower 32-bits of MSR value. |
| 1489 | @param EDX Upper 32-bits of MSR value. |
| 1490 | |
| 1491 | <b>Example usage</b> |
| 1492 | @code |
| 1493 | UINT64 Msr; |
| 1494 | |
| 1495 | Msr = AsmReadMsr64 (MSR_P6_MC0_CTL); |
| 1496 | AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr); |
| 1497 | @endcode |
| 1498 | @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. |
| 1499 | MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. |
| 1500 | MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. |
| 1501 | MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. |
| 1502 | MSR_P6_MC4_CTL is defined as MC4_CTL in SDM. |
| 1503 | @{ |
| 1504 | **/ |
| 1505 | #define MSR_P6_MC0_CTL 0x00000400 |
| 1506 | #define MSR_P6_MC1_CTL 0x00000404 |
| 1507 | #define MSR_P6_MC2_CTL 0x00000408 |
| 1508 | #define MSR_P6_MC3_CTL 0x00000410 |
| 1509 | #define MSR_P6_MC4_CTL 0x0000040C |
| 1510 | /// @} |
| 1511 | |
| 1512 | |
| 1513 | /** |
| 1514 | |
| 1515 | Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, |
| 1516 | except bits 0, 4, 57, and 61 are hardcoded to 1. |
| 1517 | |
| 1518 | @param ECX MSR_P6_MCn_STATUS |
| 1519 | @param EAX Lower 32-bits of MSR value. |
| 1520 | Described by the type MSR_P6_MC_STATUS_REGISTER. |
| 1521 | @param EDX Upper 32-bits of MSR value. |
| 1522 | Described by the type MSR_P6_MC_STATUS_REGISTER. |
| 1523 | |
| 1524 | <b>Example usage</b> |
| 1525 | @code |
| 1526 | MSR_P6_MC_STATUS_REGISTER Msr; |
| 1527 | |
| 1528 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS); |
| 1529 | AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64); |
| 1530 | @endcode |
| 1531 | @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. |
| 1532 | MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. |
| 1533 | MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. |
| 1534 | MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. |
| 1535 | MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM. |
| 1536 | @{ |
| 1537 | **/ |
| 1538 | #define MSR_P6_MC0_STATUS 0x00000401 |
| 1539 | #define MSR_P6_MC1_STATUS 0x00000405 |
| 1540 | #define MSR_P6_MC2_STATUS 0x00000409 |
| 1541 | #define MSR_P6_MC3_STATUS 0x00000411 |
| 1542 | #define MSR_P6_MC4_STATUS 0x0000040D |
| 1543 | /// @} |
| 1544 | |
| 1545 | /** |
| 1546 | MSR information returned for MSR index #MSR_P6_MC0_STATUS to |
| 1547 | #MSR_P6_MC4_STATUS |
| 1548 | **/ |
| 1549 | typedef union { |
| 1550 | /// |
| 1551 | /// Individual bit fields |
| 1552 | /// |
| 1553 | struct { |
| 1554 | /// |
| 1555 | /// [Bits 15:0] MC_STATUS_MCACOD. |
| 1556 | /// |
| 1557 | UINT32 MC_STATUS_MCACOD:16; |
| 1558 | /// |
| 1559 | /// [Bits 31:16] MC_STATUS_MSCOD. |
| 1560 | /// |
| 1561 | UINT32 MC_STATUS_MSCOD:16; |
| 1562 | UINT32 Reserved:25; |
| 1563 | /// |
| 1564 | /// [Bit 57] MC_STATUS_DAM. |
| 1565 | /// |
| 1566 | UINT32 MC_STATUS_DAM:1; |
| 1567 | /// |
| 1568 | /// [Bit 58] MC_STATUS_ADDRV. |
| 1569 | /// |
| 1570 | UINT32 MC_STATUS_ADDRV:1; |
| 1571 | /// |
| 1572 | /// [Bit 59] MC_STATUS_MISCV. |
| 1573 | /// |
| 1574 | UINT32 MC_STATUS_MISCV:1; |
| 1575 | /// |
| 1576 | /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is |
| 1577 | /// hardcoded to 1.). |
| 1578 | /// |
| 1579 | UINT32 MC_STATUS_EN:1; |
| 1580 | /// |
| 1581 | /// [Bit 61] MC_STATUS_UC. |
| 1582 | /// |
| 1583 | UINT32 MC_STATUS_UC:1; |
| 1584 | /// |
| 1585 | /// [Bit 62] MC_STATUS_O. |
| 1586 | /// |
| 1587 | UINT32 MC_STATUS_O:1; |
| 1588 | /// |
| 1589 | /// [Bit 63] MC_STATUS_V. |
| 1590 | /// |
| 1591 | UINT32 MC_STATUS_V:1; |
| 1592 | } Bits; |
| 1593 | /// |
| 1594 | /// All bit fields as a 64-bit value |
| 1595 | /// |
| 1596 | UINT64 Uint64; |
| 1597 | } MSR_P6_MC_STATUS_REGISTER; |
| 1598 | |
| 1599 | |
| 1600 | /** |
| 1601 | |
| 1602 | MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors. |
| 1603 | |
| 1604 | @param ECX MSR_P6_MC0_ADDR (0x00000402) |
| 1605 | @param EAX Lower 32-bits of MSR value. |
| 1606 | @param EDX Upper 32-bits of MSR value. |
| 1607 | |
| 1608 | <b>Example usage</b> |
| 1609 | @code |
| 1610 | UINT64 Msr; |
| 1611 | |
| 1612 | Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR); |
| 1613 | AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr); |
| 1614 | @endcode |
| 1615 | @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. |
| 1616 | MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. |
| 1617 | MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. |
| 1618 | MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. |
| 1619 | MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM. |
| 1620 | @{ |
| 1621 | **/ |
| 1622 | #define MSR_P6_MC0_ADDR 0x00000402 |
| 1623 | #define MSR_P6_MC1_ADDR 0x00000406 |
| 1624 | #define MSR_P6_MC2_ADDR 0x0000040A |
| 1625 | #define MSR_P6_MC3_ADDR 0x00000412 |
| 1626 | #define MSR_P6_MC4_ADDR 0x0000040E |
| 1627 | /// @} |
| 1628 | |
| 1629 | |
| 1630 | /** |
| 1631 | Defined in MCA architecture but not implemented in the P6 family processors. |
| 1632 | |
| 1633 | @param ECX MSR_P6_MC0_MISC (0x00000403) |
| 1634 | @param EAX Lower 32-bits of MSR value. |
| 1635 | @param EDX Upper 32-bits of MSR value. |
| 1636 | |
| 1637 | <b>Example usage</b> |
| 1638 | @code |
| 1639 | UINT64 Msr; |
| 1640 | |
| 1641 | Msr = AsmReadMsr64 (MSR_P6_MC0_MISC); |
| 1642 | AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr); |
| 1643 | @endcode |
| 1644 | @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. |
| 1645 | MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. |
| 1646 | MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. |
| 1647 | MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. |
| 1648 | MSR_P6_MC4_MISC is defined as MC4_MISC in SDM. |
| 1649 | @{ |
| 1650 | **/ |
| 1651 | #define MSR_P6_MC0_MISC 0x00000403 |
| 1652 | #define MSR_P6_MC1_MISC 0x00000407 |
| 1653 | #define MSR_P6_MC2_MISC 0x0000040B |
| 1654 | #define MSR_P6_MC3_MISC 0x00000413 |
| 1655 | #define MSR_P6_MC4_MISC 0x0000040F |
| 1656 | /// @} |
| 1657 | |
| 1658 | #endif |