Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | MSR Definitions for the Intel(R) Atom(TM) Processor Family. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __ATOM_MSR_H__ |
| 19 | #define __ATOM_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is Intel(R) Atom(TM) Processor Family? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x06 && \ |
| 34 | ( \ |
| 35 | DisplayModel == 0x1C || \ |
| 36 | DisplayModel == 0x26 || \ |
| 37 | DisplayModel == 0x27 || \ |
| 38 | DisplayModel == 0x35 || \ |
| 39 | DisplayModel == 0x36 \ |
| 40 | ) \ |
| 41 | ) |
| 42 | |
| 43 | /** |
| 44 | Shared. Model Specific Platform ID (R). |
| 45 | |
| 46 | @param ECX MSR_ATOM_PLATFORM_ID (0x00000017) |
| 47 | @param EAX Lower 32-bits of MSR value. |
| 48 | Described by the type MSR_ATOM_PLATFORM_ID_REGISTER. |
| 49 | @param EDX Upper 32-bits of MSR value. |
| 50 | Described by the type MSR_ATOM_PLATFORM_ID_REGISTER. |
| 51 | |
| 52 | <b>Example usage</b> |
| 53 | @code |
| 54 | MSR_ATOM_PLATFORM_ID_REGISTER Msr; |
| 55 | |
| 56 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID); |
| 57 | @endcode |
| 58 | @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. |
| 59 | **/ |
| 60 | #define MSR_ATOM_PLATFORM_ID 0x00000017 |
| 61 | |
| 62 | /** |
| 63 | MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID |
| 64 | **/ |
| 65 | typedef union { |
| 66 | /// |
| 67 | /// Individual bit fields |
| 68 | /// |
| 69 | struct { |
| 70 | UINT32 Reserved1:8; |
| 71 | /// |
| 72 | /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio. |
| 73 | /// |
| 74 | UINT32 MaximumQualifiedRatio:5; |
| 75 | UINT32 Reserved2:19; |
| 76 | UINT32 Reserved3:32; |
| 77 | } Bits; |
| 78 | /// |
| 79 | /// All bit fields as a 32-bit value |
| 80 | /// |
| 81 | UINT32 Uint32; |
| 82 | /// |
| 83 | /// All bit fields as a 64-bit value |
| 84 | /// |
| 85 | UINT64 Uint64; |
| 86 | } MSR_ATOM_PLATFORM_ID_REGISTER; |
| 87 | |
| 88 | |
| 89 | /** |
| 90 | Shared. Processor Hard Power-On Configuration (R/W) Enables and disables |
| 91 | processor features; (R) indicates current processor configuration. |
| 92 | |
| 93 | @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A) |
| 94 | @param EAX Lower 32-bits of MSR value. |
| 95 | Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER. |
| 96 | @param EDX Upper 32-bits of MSR value. |
| 97 | Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER. |
| 98 | |
| 99 | <b>Example usage</b> |
| 100 | @code |
| 101 | MSR_ATOM_EBL_CR_POWERON_REGISTER Msr; |
| 102 | |
| 103 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON); |
| 104 | AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64); |
| 105 | @endcode |
| 106 | @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. |
| 107 | **/ |
| 108 | #define MSR_ATOM_EBL_CR_POWERON 0x0000002A |
| 109 | |
| 110 | /** |
| 111 | MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON |
| 112 | **/ |
| 113 | typedef union { |
| 114 | /// |
| 115 | /// Individual bit fields |
| 116 | /// |
| 117 | struct { |
| 118 | UINT32 Reserved1:1; |
| 119 | /// |
| 120 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled |
| 121 | /// Always 0. |
| 122 | /// |
| 123 | UINT32 DataErrorCheckingEnable:1; |
| 124 | /// |
| 125 | /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled |
| 126 | /// Always 0. |
| 127 | /// |
| 128 | UINT32 ResponseErrorCheckingEnable:1; |
| 129 | /// |
| 130 | /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. |
| 131 | /// |
| 132 | UINT32 AERR_DriveEnable:1; |
| 133 | /// |
| 134 | /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 = |
| 135 | /// Disabled Always 0. |
| 136 | /// |
| 137 | UINT32 BERR_Enable:1; |
| 138 | UINT32 Reserved2:1; |
| 139 | UINT32 Reserved3:1; |
| 140 | /// |
| 141 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. |
| 142 | /// |
| 143 | UINT32 BINIT_DriverEnable:1; |
| 144 | UINT32 Reserved4:1; |
| 145 | /// |
| 146 | /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled. |
| 147 | /// |
| 148 | UINT32 ExecuteBIST:1; |
| 149 | /// |
| 150 | /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled |
| 151 | /// Always 0. |
| 152 | /// |
| 153 | UINT32 AERR_ObservationEnabled:1; |
| 154 | UINT32 Reserved5:1; |
| 155 | /// |
| 156 | /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled |
| 157 | /// Always 0. |
| 158 | /// |
| 159 | UINT32 BINIT_ObservationEnabled:1; |
| 160 | UINT32 Reserved6:1; |
| 161 | /// |
| 162 | /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes. |
| 163 | /// |
| 164 | UINT32 ResetVector:1; |
| 165 | UINT32 Reserved7:1; |
| 166 | /// |
| 167 | /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B. |
| 168 | /// |
| 169 | UINT32 APICClusterID:2; |
| 170 | UINT32 Reserved8:2; |
| 171 | /// |
| 172 | /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B. |
| 173 | /// |
| 174 | UINT32 SymmetricArbitrationID:2; |
| 175 | /// |
| 176 | /// [Bits 26:22] Integer Bus Frequency Ratio (R/O). |
| 177 | /// |
| 178 | UINT32 IntegerBusFrequencyRatio:5; |
| 179 | UINT32 Reserved9:5; |
| 180 | UINT32 Reserved10:32; |
| 181 | } Bits; |
| 182 | /// |
| 183 | /// All bit fields as a 32-bit value |
| 184 | /// |
| 185 | UINT32 Uint32; |
| 186 | /// |
| 187 | /// All bit fields as a 64-bit value |
| 188 | /// |
| 189 | UINT64 Uint64; |
| 190 | } MSR_ATOM_EBL_CR_POWERON_REGISTER; |
| 191 | |
| 192 | |
| 193 | /** |
| 194 | Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch |
| 195 | record registers on the last branch record stack. The From_IP part of the |
| 196 | stack contains pointers to the source instruction . See also: - Last Branch |
| 197 | Record Stack TOS at 1C9H - Section 17.5. |
| 198 | |
| 199 | @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP |
| 200 | @param EAX Lower 32-bits of MSR value. |
| 201 | @param EDX Upper 32-bits of MSR value. |
| 202 | |
| 203 | <b>Example usage</b> |
| 204 | @code |
| 205 | UINT64 Msr; |
| 206 | |
| 207 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP); |
| 208 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr); |
| 209 | @endcode |
| 210 | @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. |
| 211 | MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. |
| 212 | MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. |
| 213 | MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. |
| 214 | MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. |
| 215 | MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. |
| 216 | MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. |
| 217 | MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. |
| 218 | @{ |
| 219 | **/ |
| 220 | #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040 |
| 221 | #define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041 |
| 222 | #define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042 |
| 223 | #define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043 |
| 224 | #define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044 |
| 225 | #define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045 |
| 226 | #define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046 |
| 227 | #define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047 |
| 228 | /// @} |
| 229 | |
| 230 | |
| 231 | /** |
| 232 | Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch |
| 233 | record registers on the last branch record stack. The To_IP part of the |
| 234 | stack contains pointers to the destination instruction. |
| 235 | |
| 236 | @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP |
| 237 | @param EAX Lower 32-bits of MSR value. |
| 238 | @param EDX Upper 32-bits of MSR value. |
| 239 | |
| 240 | <b>Example usage</b> |
| 241 | @code |
| 242 | UINT64 Msr; |
| 243 | |
| 244 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP); |
| 245 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr); |
| 246 | @endcode |
| 247 | @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. |
| 248 | MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. |
| 249 | MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. |
| 250 | MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. |
| 251 | MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. |
| 252 | MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. |
| 253 | MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. |
| 254 | MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. |
| 255 | @{ |
| 256 | **/ |
| 257 | #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060 |
| 258 | #define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061 |
| 259 | #define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062 |
| 260 | #define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063 |
| 261 | #define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064 |
| 262 | #define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065 |
| 263 | #define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066 |
| 264 | #define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067 |
| 265 | /// @} |
| 266 | |
| 267 | |
| 268 | /** |
| 269 | Shared. Scalable Bus Speed(RO) This field indicates the intended scalable |
| 270 | bus clock speed for processors based on Intel Atom microarchitecture:. |
| 271 | |
| 272 | @param ECX MSR_ATOM_FSB_FREQ (0x000000CD) |
| 273 | @param EAX Lower 32-bits of MSR value. |
| 274 | Described by the type MSR_ATOM_FSB_FREQ_REGISTER. |
| 275 | @param EDX Upper 32-bits of MSR value. |
| 276 | Described by the type MSR_ATOM_FSB_FREQ_REGISTER. |
| 277 | |
| 278 | <b>Example usage</b> |
| 279 | @code |
| 280 | MSR_ATOM_FSB_FREQ_REGISTER Msr; |
| 281 | |
| 282 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ); |
| 283 | @endcode |
| 284 | @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM. |
| 285 | **/ |
| 286 | #define MSR_ATOM_FSB_FREQ 0x000000CD |
| 287 | |
| 288 | /** |
| 289 | MSR information returned for MSR index #MSR_ATOM_FSB_FREQ |
| 290 | **/ |
| 291 | typedef union { |
| 292 | /// |
| 293 | /// Individual bit fields |
| 294 | /// |
| 295 | struct { |
| 296 | /// |
| 297 | /// [Bits 2:0] - Scalable Bus Speed |
| 298 | /// |
| 299 | /// Atom Processor Family |
| 300 | /// --------------------- |
| 301 | /// 111B: 083 MHz (FSB 333) |
| 302 | /// 101B: 100 MHz (FSB 400) |
| 303 | /// 001B: 133 MHz (FSB 533) |
| 304 | /// 011B: 167 MHz (FSB 667) |
| 305 | /// |
| 306 | /// 133.33 MHz should be utilized if performing calculation with |
| 307 | /// System Bus Speed when encoding is 001B. |
| 308 | /// 166.67 MHz should be utilized if performing calculation with |
| 309 | /// System Bus Speed when |
| 310 | /// encoding is 011B. |
| 311 | /// |
| 312 | UINT32 ScalableBusSpeed:3; |
| 313 | UINT32 Reserved1:29; |
| 314 | UINT32 Reserved2:32; |
| 315 | } Bits; |
| 316 | /// |
| 317 | /// All bit fields as a 32-bit value |
| 318 | /// |
| 319 | UINT32 Uint32; |
| 320 | /// |
| 321 | /// All bit fields as a 64-bit value |
| 322 | /// |
| 323 | UINT64 Uint64; |
| 324 | } MSR_ATOM_FSB_FREQ_REGISTER; |
| 325 | |
| 326 | |
| 327 | /** |
| 328 | Shared. |
| 329 | |
| 330 | @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E) |
| 331 | @param EAX Lower 32-bits of MSR value. |
| 332 | Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER. |
| 333 | @param EDX Upper 32-bits of MSR value. |
| 334 | Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER. |
| 335 | |
| 336 | <b>Example usage</b> |
| 337 | @code |
| 338 | MSR_ATOM_BBL_CR_CTL3_REGISTER Msr; |
| 339 | |
| 340 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3); |
| 341 | AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64); |
| 342 | @endcode |
| 343 | @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. |
| 344 | **/ |
| 345 | #define MSR_ATOM_BBL_CR_CTL3 0x0000011E |
| 346 | |
| 347 | /** |
| 348 | MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3 |
| 349 | **/ |
| 350 | typedef union { |
| 351 | /// |
| 352 | /// Individual bit fields |
| 353 | /// |
| 354 | struct { |
| 355 | /// |
| 356 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = |
| 357 | /// Indicates if the L2 is hardware-disabled. |
| 358 | /// |
| 359 | UINT32 L2HardwareEnabled:1; |
| 360 | UINT32 Reserved1:7; |
| 361 | /// |
| 362 | /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 = |
| 363 | /// Disabled (default) Until this bit is set the processor will not |
| 364 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input. |
| 365 | /// |
| 366 | UINT32 L2Enabled:1; |
| 367 | UINT32 Reserved2:14; |
| 368 | /// |
| 369 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. |
| 370 | /// |
| 371 | UINT32 L2NotPresent:1; |
| 372 | UINT32 Reserved3:8; |
| 373 | UINT32 Reserved4:32; |
| 374 | } Bits; |
| 375 | /// |
| 376 | /// All bit fields as a 32-bit value |
| 377 | /// |
| 378 | UINT32 Uint32; |
| 379 | /// |
| 380 | /// All bit fields as a 64-bit value |
| 381 | /// |
| 382 | UINT64 Uint64; |
| 383 | } MSR_ATOM_BBL_CR_CTL3_REGISTER; |
| 384 | |
| 385 | |
| 386 | /** |
| 387 | Shared. |
| 388 | |
| 389 | @param ECX MSR_ATOM_PERF_STATUS (0x00000198) |
| 390 | @param EAX Lower 32-bits of MSR value. |
| 391 | Described by the type MSR_ATOM_PERF_STATUS_REGISTER. |
| 392 | @param EDX Upper 32-bits of MSR value. |
| 393 | Described by the type MSR_ATOM_PERF_STATUS_REGISTER. |
| 394 | |
| 395 | <b>Example usage</b> |
| 396 | @code |
| 397 | MSR_ATOM_PERF_STATUS_REGISTER Msr; |
| 398 | |
| 399 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS); |
| 400 | AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64); |
| 401 | @endcode |
| 402 | @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM. |
| 403 | **/ |
| 404 | #define MSR_ATOM_PERF_STATUS 0x00000198 |
| 405 | |
| 406 | /** |
| 407 | MSR information returned for MSR index #MSR_ATOM_PERF_STATUS |
| 408 | **/ |
| 409 | typedef union { |
| 410 | /// |
| 411 | /// Individual bit fields |
| 412 | /// |
| 413 | struct { |
| 414 | /// |
| 415 | /// [Bits 15:0] Current Performance State Value. |
| 416 | /// |
| 417 | UINT32 CurrentPerformanceStateValue:16; |
| 418 | UINT32 Reserved1:16; |
| 419 | UINT32 Reserved2:8; |
| 420 | /// |
| 421 | /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio |
| 422 | /// configured for the processor. |
| 423 | /// |
| 424 | UINT32 MaximumBusRatio:5; |
| 425 | UINT32 Reserved3:19; |
| 426 | } Bits; |
| 427 | /// |
| 428 | /// All bit fields as a 64-bit value |
| 429 | /// |
| 430 | UINT64 Uint64; |
| 431 | } MSR_ATOM_PERF_STATUS_REGISTER; |
| 432 | |
| 433 | |
| 434 | /** |
| 435 | Shared. |
| 436 | |
| 437 | @param ECX MSR_ATOM_THERM2_CTL (0x0000019D) |
| 438 | @param EAX Lower 32-bits of MSR value. |
| 439 | Described by the type MSR_ATOM_THERM2_CTL_REGISTER. |
| 440 | @param EDX Upper 32-bits of MSR value. |
| 441 | Described by the type MSR_ATOM_THERM2_CTL_REGISTER. |
| 442 | |
| 443 | <b>Example usage</b> |
| 444 | @code |
| 445 | MSR_ATOM_THERM2_CTL_REGISTER Msr; |
| 446 | |
| 447 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL); |
| 448 | AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64); |
| 449 | @endcode |
| 450 | @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. |
| 451 | **/ |
| 452 | #define MSR_ATOM_THERM2_CTL 0x0000019D |
| 453 | |
| 454 | /** |
| 455 | MSR information returned for MSR index #MSR_ATOM_THERM2_CTL |
| 456 | **/ |
| 457 | typedef union { |
| 458 | /// |
| 459 | /// Individual bit fields |
| 460 | /// |
| 461 | struct { |
| 462 | UINT32 Reserved1:16; |
| 463 | /// |
| 464 | /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = |
| 465 | /// Thermal Monitor 1 (thermally-initiated on-die modulation of the |
| 466 | /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated |
| 467 | /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is |
| 468 | /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled. |
| 469 | /// |
| 470 | UINT32 TM_SELECT:1; |
| 471 | UINT32 Reserved2:15; |
| 472 | UINT32 Reserved3:32; |
| 473 | } Bits; |
| 474 | /// |
| 475 | /// All bit fields as a 32-bit value |
| 476 | /// |
| 477 | UINT32 Uint32; |
| 478 | /// |
| 479 | /// All bit fields as a 64-bit value |
| 480 | /// |
| 481 | UINT64 Uint64; |
| 482 | } MSR_ATOM_THERM2_CTL_REGISTER; |
| 483 | |
| 484 | |
| 485 | /** |
| 486 | Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor |
| 487 | functions to be enabled and disabled. |
| 488 | |
| 489 | @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0) |
| 490 | @param EAX Lower 32-bits of MSR value. |
| 491 | Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER. |
| 492 | @param EDX Upper 32-bits of MSR value. |
| 493 | Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER. |
| 494 | |
| 495 | <b>Example usage</b> |
| 496 | @code |
| 497 | MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr; |
| 498 | |
| 499 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE); |
| 500 | AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64); |
| 501 | @endcode |
| 502 | @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. |
| 503 | **/ |
| 504 | #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0 |
| 505 | |
| 506 | /** |
| 507 | MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE |
| 508 | **/ |
| 509 | typedef union { |
| 510 | /// |
| 511 | /// Individual bit fields |
| 512 | /// |
| 513 | struct { |
| 514 | /// |
| 515 | /// [Bit 0] Fast-Strings Enable See Table 2-2. |
| 516 | /// |
| 517 | UINT32 FastStrings:1; |
| 518 | UINT32 Reserved1:2; |
| 519 | /// |
| 520 | /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See |
| 521 | /// Table 2-2. Default value is 0. |
| 522 | /// |
| 523 | UINT32 AutomaticThermalControlCircuit:1; |
| 524 | UINT32 Reserved2:3; |
| 525 | /// |
| 526 | /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2. |
| 527 | /// |
| 528 | UINT32 PerformanceMonitoring:1; |
| 529 | UINT32 Reserved3:1; |
| 530 | UINT32 Reserved4:1; |
| 531 | /// |
| 532 | /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by |
| 533 | /// the processor to indicate a pending break event within the processor 0 |
| 534 | /// = Indicates compatible FERR# signaling behavior This bit must be set |
| 535 | /// to 1 to support XAPIC interrupt model usage. |
| 536 | /// |
| 537 | UINT32 FERR:1; |
| 538 | /// |
| 539 | /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2. |
| 540 | /// |
| 541 | UINT32 BTS:1; |
| 542 | /// |
| 543 | /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See |
| 544 | /// Table 2-2. |
| 545 | /// |
| 546 | UINT32 PEBS:1; |
| 547 | /// |
| 548 | /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the |
| 549 | /// thermal sensor indicates that the die temperature is at the |
| 550 | /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. |
| 551 | /// TM2 will reduce the bus to core ratio and voltage according to the |
| 552 | /// value last written to MSR_THERM2_CTL bits 15:0. |
| 553 | /// When this bit is clear (0, default), the processor does not change |
| 554 | /// the VID signals or the bus to core ratio when the processor enters a |
| 555 | /// thermally managed state. The BIOS must enable this feature if the |
| 556 | /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is |
| 557 | /// not set, this feature is not supported and BIOS must not alter the |
| 558 | /// contents of the TM2 bit location. The processor is operating out of |
| 559 | /// specification if both this bit and the TM1 bit are set to 0. |
| 560 | /// |
| 561 | UINT32 TM2:1; |
| 562 | UINT32 Reserved5:2; |
| 563 | /// |
| 564 | /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See |
| 565 | /// Table 2-2. |
| 566 | /// |
| 567 | UINT32 EIST:1; |
| 568 | UINT32 Reserved6:1; |
| 569 | /// |
| 570 | /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2. |
| 571 | /// |
| 572 | UINT32 MONITOR:1; |
| 573 | UINT32 Reserved7:1; |
| 574 | /// |
| 575 | /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock |
| 576 | /// (R/WO) When set, this bit causes the following bits to become |
| 577 | /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this |
| 578 | /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must |
| 579 | /// be set before an Enhanced Intel SpeedStep Technology transition is |
| 580 | /// requested. This bit is cleared on reset. |
| 581 | /// |
| 582 | UINT32 EISTLock:1; |
| 583 | UINT32 Reserved8:1; |
| 584 | /// |
| 585 | /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2. |
| 586 | /// |
| 587 | UINT32 LimitCpuidMaxval:1; |
| 588 | /// |
| 589 | /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2. |
| 590 | /// |
| 591 | UINT32 xTPR_Message_Disable:1; |
| 592 | UINT32 Reserved9:8; |
| 593 | UINT32 Reserved10:2; |
| 594 | /// |
| 595 | /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2. |
| 596 | /// |
| 597 | UINT32 XD:1; |
| 598 | UINT32 Reserved11:29; |
| 599 | } Bits; |
| 600 | /// |
| 601 | /// All bit fields as a 64-bit value |
| 602 | /// |
| 603 | UINT64 Uint64; |
| 604 | } MSR_ATOM_IA32_MISC_ENABLE_REGISTER; |
| 605 | |
| 606 | |
| 607 | /** |
| 608 | Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) |
| 609 | that points to the MSR containing the most recent branch record. See |
| 610 | MSR_LASTBRANCH_0_FROM_IP (at 40H). |
| 611 | |
| 612 | @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9) |
| 613 | @param EAX Lower 32-bits of MSR value. |
| 614 | @param EDX Upper 32-bits of MSR value. |
| 615 | |
| 616 | <b>Example usage</b> |
| 617 | @code |
| 618 | UINT64 Msr; |
| 619 | |
| 620 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS); |
| 621 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr); |
| 622 | @endcode |
| 623 | @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. |
| 624 | **/ |
| 625 | #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9 |
| 626 | |
| 627 | |
| 628 | /** |
| 629 | Unique. Last Exception Record From Linear IP (R) Contains a pointer to the |
| 630 | last branch instruction that the processor executed prior to the last |
| 631 | exception that was generated or the last interrupt that was handled. |
| 632 | |
| 633 | @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD) |
| 634 | @param EAX Lower 32-bits of MSR value. |
| 635 | @param EDX Upper 32-bits of MSR value. |
| 636 | |
| 637 | <b>Example usage</b> |
| 638 | @code |
| 639 | UINT64 Msr; |
| 640 | |
| 641 | Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP); |
| 642 | @endcode |
| 643 | @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. |
| 644 | **/ |
| 645 | #define MSR_ATOM_LER_FROM_LIP 0x000001DD |
| 646 | |
| 647 | |
| 648 | /** |
| 649 | Unique. Last Exception Record To Linear IP (R) This area contains a pointer |
| 650 | to the target of the last branch instruction that the processor executed |
| 651 | prior to the last exception that was generated or the last interrupt that |
| 652 | was handled. |
| 653 | |
| 654 | @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE) |
| 655 | @param EAX Lower 32-bits of MSR value. |
| 656 | @param EDX Upper 32-bits of MSR value. |
| 657 | |
| 658 | <b>Example usage</b> |
| 659 | @code |
| 660 | UINT64 Msr; |
| 661 | |
| 662 | Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP); |
| 663 | @endcode |
| 664 | @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. |
| 665 | **/ |
| 666 | #define MSR_ATOM_LER_TO_LIP 0x000001DE |
| 667 | |
| 668 | |
| 669 | /** |
| 670 | Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling |
| 671 | (PEBS).". |
| 672 | |
| 673 | @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1) |
| 674 | @param EAX Lower 32-bits of MSR value. |
| 675 | Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER. |
| 676 | @param EDX Upper 32-bits of MSR value. |
| 677 | Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER. |
| 678 | |
| 679 | <b>Example usage</b> |
| 680 | @code |
| 681 | MSR_ATOM_PEBS_ENABLE_REGISTER Msr; |
| 682 | |
| 683 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE); |
| 684 | AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64); |
| 685 | @endcode |
| 686 | @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. |
| 687 | **/ |
| 688 | #define MSR_ATOM_PEBS_ENABLE 0x000003F1 |
| 689 | |
| 690 | /** |
| 691 | MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE |
| 692 | **/ |
| 693 | typedef union { |
| 694 | /// |
| 695 | /// Individual bit fields |
| 696 | /// |
| 697 | struct { |
| 698 | /// |
| 699 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). |
| 700 | /// |
| 701 | UINT32 Enable:1; |
| 702 | UINT32 Reserved1:31; |
| 703 | UINT32 Reserved2:32; |
| 704 | } Bits; |
| 705 | /// |
| 706 | /// All bit fields as a 32-bit value |
| 707 | /// |
| 708 | UINT32 Uint32; |
| 709 | /// |
| 710 | /// All bit fields as a 64-bit value |
| 711 | /// |
| 712 | UINT64 Uint64; |
| 713 | } MSR_ATOM_PEBS_ENABLE_REGISTER; |
| 714 | |
| 715 | |
| 716 | /** |
| 717 | Package. Package C2 Residency Note: C-state values are processor specific |
| 718 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI |
| 719 | C-States. Package. Package C2 Residency Counter. (R/O) Time that this |
| 720 | package is in processor-specific C2 states since last reset. Counts at 1 Mhz |
| 721 | frequency. |
| 722 | |
| 723 | @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8) |
| 724 | @param EAX Lower 32-bits of MSR value. |
| 725 | @param EDX Upper 32-bits of MSR value. |
| 726 | |
| 727 | <b>Example usage</b> |
| 728 | @code |
| 729 | UINT64 Msr; |
| 730 | |
| 731 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY); |
| 732 | AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr); |
| 733 | @endcode |
| 734 | @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. |
| 735 | **/ |
| 736 | #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8 |
| 737 | |
| 738 | |
| 739 | /** |
| 740 | Package. Package C4 Residency Note: C-state values are processor specific |
| 741 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI |
| 742 | C-States. Package. Package C4 Residency Counter. (R/O) Time that this |
| 743 | package is in processor-specific C4 states since last reset. Counts at 1 Mhz |
| 744 | frequency. |
| 745 | |
| 746 | @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9) |
| 747 | @param EAX Lower 32-bits of MSR value. |
| 748 | @param EDX Upper 32-bits of MSR value. |
| 749 | |
| 750 | <b>Example usage</b> |
| 751 | @code |
| 752 | UINT64 Msr; |
| 753 | |
| 754 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY); |
| 755 | AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr); |
| 756 | @endcode |
| 757 | @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM. |
| 758 | **/ |
| 759 | #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9 |
| 760 | |
| 761 | |
| 762 | /** |
| 763 | Package. Package C6 Residency Note: C-state values are processor specific |
| 764 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI |
| 765 | C-States. Package. Package C6 Residency Counter. (R/O) Time that this |
| 766 | package is in processor-specific C6 states since last reset. Counts at 1 Mhz |
| 767 | frequency. |
| 768 | |
| 769 | @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA) |
| 770 | @param EAX Lower 32-bits of MSR value. |
| 771 | @param EDX Upper 32-bits of MSR value. |
| 772 | |
| 773 | <b>Example usage</b> |
| 774 | @code |
| 775 | UINT64 Msr; |
| 776 | |
| 777 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY); |
| 778 | AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr); |
| 779 | @endcode |
| 780 | @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. |
| 781 | **/ |
| 782 | #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA |
| 783 | |
| 784 | #endif |