Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | IA32 Local APIC Definitions. |
| 3 | |
| 4 | Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR> |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 6 | |
| 7 | **/ |
| 8 | |
| 9 | #ifndef __INTEL_LOCAL_APIC_H__ |
| 10 | #define __INTEL_LOCAL_APIC_H__ |
| 11 | |
| 12 | // |
| 13 | // Definition for Local APIC registers and related values |
| 14 | // |
| 15 | #define XAPIC_ID_OFFSET 0x20 |
| 16 | #define XAPIC_VERSION_OFFSET 0x30 |
| 17 | #define XAPIC_EOI_OFFSET 0x0b0 |
| 18 | #define XAPIC_ICR_DFR_OFFSET 0x0e0 |
| 19 | #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0 |
| 20 | #define XAPIC_ICR_LOW_OFFSET 0x300 |
| 21 | #define XAPIC_ICR_HIGH_OFFSET 0x310 |
| 22 | #define XAPIC_LVT_TIMER_OFFSET 0x320 |
| 23 | #define XAPIC_LVT_LINT0_OFFSET 0x350 |
| 24 | #define XAPIC_LVT_LINT1_OFFSET 0x360 |
| 25 | #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380 |
| 26 | #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390 |
| 27 | #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0 |
| 28 | |
| 29 | #define X2APIC_MSR_BASE_ADDRESS 0x800 |
| 30 | #define X2APIC_MSR_ICR_ADDRESS 0x830 |
| 31 | |
| 32 | #define LOCAL_APIC_DELIVERY_MODE_FIXED 0 |
| 33 | #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1 |
| 34 | #define LOCAL_APIC_DELIVERY_MODE_SMI 2 |
| 35 | #define LOCAL_APIC_DELIVERY_MODE_NMI 4 |
| 36 | #define LOCAL_APIC_DELIVERY_MODE_INIT 5 |
| 37 | #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6 |
| 38 | #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7 |
| 39 | |
| 40 | #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0 |
| 41 | #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1 |
| 42 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2 |
| 43 | #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3 |
| 44 | |
| 45 | // |
| 46 | // Local APIC Version Register. |
| 47 | // |
| 48 | typedef union { |
| 49 | struct { |
| 50 | UINT32 Version:8; ///< The version numbers of the local APIC. |
| 51 | UINT32 Reserved0:8; ///< Reserved. |
| 52 | UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1. |
| 53 | UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported. |
| 54 | UINT32 Reserved1:7; ///< Reserved. |
| 55 | } Bits; |
| 56 | UINT32 Uint32; |
| 57 | } LOCAL_APIC_VERSION; |
| 58 | |
| 59 | // |
| 60 | // Low half of Interrupt Command Register (ICR). |
| 61 | // |
| 62 | typedef union { |
| 63 | struct { |
| 64 | UINT32 Vector:8; ///< The vector number of the interrupt being sent. |
| 65 | UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent. |
| 66 | UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode. |
| 67 | UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode. |
| 68 | UINT32 Reserved0:1; ///< Reserved. |
| 69 | UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1. |
| 70 | UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode. |
| 71 | UINT32 Reserved1:2; ///< Reserved. |
| 72 | UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt. |
| 73 | UINT32 Reserved2:12; ///< Reserved. |
| 74 | } Bits; |
| 75 | UINT32 Uint32; |
| 76 | } LOCAL_APIC_ICR_LOW; |
| 77 | |
| 78 | // |
| 79 | // High half of Interrupt Command Register (ICR) |
| 80 | // |
| 81 | typedef union { |
| 82 | struct { |
| 83 | UINT32 Reserved0:24; ///< Reserved. |
| 84 | UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode. |
| 85 | } Bits; |
| 86 | UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode. |
| 87 | } LOCAL_APIC_ICR_HIGH; |
| 88 | |
| 89 | // |
| 90 | // Spurious-Interrupt Vector Register (SVR) |
| 91 | // |
| 92 | typedef union { |
| 93 | struct { |
| 94 | UINT32 SpuriousVector:8; ///< Spurious Vector. |
| 95 | UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable. |
| 96 | UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking. |
| 97 | UINT32 Reserved0:2; ///< Reserved. |
| 98 | UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression. |
| 99 | UINT32 Reserved1:19; ///< Reserved. |
| 100 | } Bits; |
| 101 | UINT32 Uint32; |
| 102 | } LOCAL_APIC_SVR; |
| 103 | |
| 104 | // |
| 105 | // Divide Configuration Register (DCR) |
| 106 | // |
| 107 | typedef union { |
| 108 | struct { |
| 109 | UINT32 DivideValue1:2; ///< Low 2 bits of the divide value. |
| 110 | UINT32 Reserved0:1; ///< Always 0. |
| 111 | UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value. |
| 112 | UINT32 Reserved1:28; ///< Reserved. |
| 113 | } Bits; |
| 114 | UINT32 Uint32; |
| 115 | } LOCAL_APIC_DCR; |
| 116 | |
| 117 | // |
| 118 | // LVT Timer Register |
| 119 | // |
| 120 | typedef union { |
| 121 | struct { |
| 122 | UINT32 Vector:8; ///< The vector number of the interrupt being sent. |
| 123 | UINT32 Reserved0:4; ///< Reserved. |
| 124 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending. |
| 125 | UINT32 Reserved1:3; ///< Reserved. |
| 126 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked. |
| 127 | UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic. |
| 128 | UINT32 Reserved2:14; ///< Reserved. |
| 129 | } Bits; |
| 130 | UINT32 Uint32; |
| 131 | } LOCAL_APIC_LVT_TIMER; |
| 132 | |
| 133 | // |
| 134 | // LVT LINT0/LINT1 Register |
| 135 | // |
| 136 | typedef union { |
| 137 | struct { |
| 138 | UINT32 Vector:8; ///< The vector number of the interrupt being sent. |
| 139 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent. |
| 140 | UINT32 Reserved0:1; ///< Reserved. |
| 141 | UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending. |
| 142 | UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity. |
| 143 | UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received. |
| 144 | UINT32 TriggerMode:1; ///< 0:edge, 1:level. |
| 145 | UINT32 Mask:1; ///< 0: Not masked, 1: Masked. |
| 146 | UINT32 Reserved1:15; ///< Reserved. |
| 147 | } Bits; |
| 148 | UINT32 Uint32; |
| 149 | } LOCAL_APIC_LVT_LINT; |
| 150 | |
| 151 | // |
| 152 | // MSI Address Register |
| 153 | // |
| 154 | typedef union { |
| 155 | struct { |
| 156 | UINT32 Reserved0:2; ///< Reserved |
| 157 | UINT32 DestinationMode:1; ///< Specifies the Destination Mode. |
| 158 | UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint. |
| 159 | UINT32 Reserved1:8; ///< Reserved. |
| 160 | UINT32 DestinationId:8; ///< Specifies the Destination ID. |
| 161 | UINT32 BaseAddress:12; ///< Must be 0FEEH |
| 162 | } Bits; |
| 163 | UINT32 Uint32; |
| 164 | } LOCAL_APIC_MSI_ADDRESS; |
| 165 | |
| 166 | // |
| 167 | // MSI Address Register |
| 168 | // |
| 169 | typedef union { |
| 170 | struct { |
| 171 | UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH |
| 172 | UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent. |
| 173 | UINT32 Reserved0:3; ///< Reserved. |
| 174 | UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts. |
| 175 | UINT32 TriggerMode:1; ///< 0:Edge, 1:Level. |
| 176 | UINT32 Reserved1:16; ///< Reserved. |
| 177 | UINT32 Reserved2:32; ///< Reserved. |
| 178 | } Bits; |
| 179 | UINT64 Uint64; |
| 180 | } LOCAL_APIC_MSI_DATA; |
| 181 | |
| 182 | #endif |
| 183 | |