Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame] | 1 | /** @file |
| 2 | Intel CPUID leaf definitions. |
| 3 | |
| 4 | Provides defines for CPUID leaf indexes. Data structures are provided for |
| 5 | registers returned by a CPUID leaf that contain one or more bit fields. |
| 6 | If a register returned is a single 32-bit value, then a data structure is |
| 7 | not provided for that register. |
| 8 | |
| 9 | Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, |
| 14 | November 2018, CPUID instruction. |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __INTEL_CPUID_H__ |
| 19 | #define __INTEL_CPUID_H__ |
| 20 | |
| 21 | /** |
| 22 | CPUID Signature Information |
| 23 | |
| 24 | @param EAX CPUID_SIGNATURE (0x00) |
| 25 | |
| 26 | @retval EAX Returns the highest value the CPUID instruction recognizes for |
| 27 | returning basic processor information. The value is returned is |
| 28 | processor specific. |
| 29 | @retval EBX First 4 characters of a vendor identification string. |
| 30 | @retval ECX Last 4 characters of a vendor identification string. |
| 31 | @retval EDX Middle 4 characters of a vendor identification string. |
| 32 | |
| 33 | <b>Example usage</b> |
| 34 | @code |
| 35 | UINT32 Eax; |
| 36 | UINT32 Ebx; |
| 37 | UINT32 Ecx; |
| 38 | UINT32 Edx; |
| 39 | |
| 40 | AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx); |
| 41 | @endcode |
| 42 | **/ |
| 43 | #define CPUID_SIGNATURE 0x00 |
| 44 | |
| 45 | /// |
| 46 | /// @{ CPUID signature values returned by Intel processors |
| 47 | /// |
| 48 | #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u') |
| 49 | #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I') |
| 50 | #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l') |
| 51 | /// |
| 52 | /// @} |
| 53 | /// |
| 54 | |
| 55 | |
| 56 | /** |
| 57 | CPUID Version Information |
| 58 | |
| 59 | @param EAX CPUID_VERSION_INFO (0x01) |
| 60 | |
| 61 | @retval EAX Returns Model, Family, Stepping Information described by the |
| 62 | type CPUID_VERSION_INFO_EAX. |
| 63 | @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by |
| 64 | the type CPUID_VERSION_INFO_EBX. |
| 65 | @retval ECX CPU Feature Information described by the type |
| 66 | CPUID_VERSION_INFO_ECX. |
| 67 | @retval EDX CPU Feature Information described by the type |
| 68 | CPUID_VERSION_INFO_EDX. |
| 69 | |
| 70 | <b>Example usage</b> |
| 71 | @code |
| 72 | CPUID_VERSION_INFO_EAX Eax; |
| 73 | CPUID_VERSION_INFO_EBX Ebx; |
| 74 | CPUID_VERSION_INFO_ECX Ecx; |
| 75 | CPUID_VERSION_INFO_EDX Edx; |
| 76 | |
| 77 | AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); |
| 78 | @endcode |
| 79 | **/ |
| 80 | #define CPUID_VERSION_INFO 0x01 |
| 81 | |
| 82 | /** |
| 83 | CPUID Version Information returned in EAX for CPUID leaf |
| 84 | #CPUID_VERSION_INFO. |
| 85 | **/ |
| 86 | typedef union { |
| 87 | /// |
| 88 | /// Individual bit fields |
| 89 | /// |
| 90 | struct { |
| 91 | UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID |
| 92 | UINT32 Model:4; ///< [Bits 7:4] Model |
| 93 | UINT32 FamilyId:4; ///< [Bits 11:8] Family |
| 94 | UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type |
| 95 | UINT32 Reserved1:2; ///< [Bits 15:14] Reserved |
| 96 | UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID |
| 97 | UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID |
| 98 | UINT32 Reserved2:4; ///< Reserved |
| 99 | } Bits; |
| 100 | /// |
| 101 | /// All bit fields as a 32-bit value |
| 102 | /// |
| 103 | UINT32 Uint32; |
| 104 | } CPUID_VERSION_INFO_EAX; |
| 105 | |
| 106 | /// |
| 107 | /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType |
| 108 | /// |
| 109 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00 |
| 110 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01 |
| 111 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02 |
| 112 | /// |
| 113 | /// @} |
| 114 | /// |
| 115 | |
| 116 | /** |
| 117 | CPUID Version Information returned in EBX for CPUID leaf |
| 118 | #CPUID_VERSION_INFO. |
| 119 | **/ |
| 120 | typedef union { |
| 121 | /// |
| 122 | /// Individual bit fields |
| 123 | /// |
| 124 | struct { |
| 125 | /// |
| 126 | /// [Bits 7:0] Provides an entry into a brand string table that contains |
| 127 | /// brand strings for IA-32 processors. |
| 128 | /// |
| 129 | UINT32 BrandIndex:8; |
| 130 | /// |
| 131 | /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH |
| 132 | /// and CLFLUSHOPT instructions in 8-byte increments. This field was |
| 133 | /// introduced in the Pentium 4 processor. |
| 134 | /// |
| 135 | UINT32 CacheLineSize:8; |
| 136 | /// |
| 137 | /// [Bits 23:16] Maximum number of addressable IDs for logical processors |
| 138 | /// in this physical package. |
| 139 | /// |
| 140 | /// @note |
| 141 | /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is |
| 142 | /// the number of unique initial APICIDs reserved for addressing different |
| 143 | /// logical processors in a physical package. This field is only valid if |
| 144 | /// CPUID.1.EDX.HTT[bit 28]= 1. |
| 145 | /// |
| 146 | UINT32 MaximumAddressableIdsForLogicalProcessors:8; |
| 147 | /// |
| 148 | /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the |
| 149 | /// processor during power up. This field was introduced in the Pentium 4 |
| 150 | /// processor. |
| 151 | /// |
| 152 | UINT32 InitialLocalApicId:8; |
| 153 | } Bits; |
| 154 | /// |
| 155 | /// All bit fields as a 32-bit value |
| 156 | /// |
| 157 | UINT32 Uint32; |
| 158 | } CPUID_VERSION_INFO_EBX; |
| 159 | |
| 160 | /** |
| 161 | CPUID Version Information returned in ECX for CPUID leaf |
| 162 | #CPUID_VERSION_INFO. |
| 163 | **/ |
| 164 | typedef union { |
| 165 | /// |
| 166 | /// Individual bit fields |
| 167 | /// |
| 168 | struct { |
| 169 | /// |
| 170 | /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the |
| 171 | /// processor supports this technology |
| 172 | /// |
| 173 | UINT32 SSE3:1; |
| 174 | /// |
| 175 | /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ |
| 176 | /// instruction. Carryless Multiplication |
| 177 | /// |
| 178 | UINT32 PCLMULQDQ:1; |
| 179 | /// |
| 180 | /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports |
| 181 | /// DS area using 64-bit layout. |
| 182 | /// |
| 183 | UINT32 DTES64:1; |
| 184 | /// |
| 185 | /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports |
| 186 | /// this feature. |
| 187 | /// |
| 188 | UINT32 MONITOR:1; |
| 189 | /// |
| 190 | /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor |
| 191 | /// supports the extensions to the Debug Store feature to allow for branch |
| 192 | /// message storage qualified by CPL |
| 193 | /// |
| 194 | UINT32 DS_CPL:1; |
| 195 | /// |
| 196 | /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the |
| 197 | /// processor supports this technology. |
| 198 | /// |
| 199 | UINT32 VMX:1; |
| 200 | /// |
| 201 | /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor |
| 202 | /// supports this technology |
| 203 | /// |
| 204 | UINT32 SMX:1; |
| 205 | /// |
| 206 | /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates |
| 207 | /// that the processor supports this technology |
| 208 | /// |
| 209 | UINT32 EIST:1; |
| 210 | /// |
| 211 | /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor |
| 212 | /// supports this technology |
| 213 | /// |
| 214 | UINT32 TM2:1; |
| 215 | /// |
| 216 | /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming |
| 217 | /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction |
| 218 | /// extensions are not present in the processor. |
| 219 | /// |
| 220 | UINT32 SSSE3:1; |
| 221 | /// |
| 222 | /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode |
| 223 | /// can be set to either adaptive mode or shared mode. A value of 0 indicates |
| 224 | /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR |
| 225 | /// Bit 24 (L1 Data Cache Context Mode) for details |
| 226 | /// |
| 227 | UINT32 CNXT_ID:1; |
| 228 | /// |
| 229 | /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE |
| 230 | /// MSR for silicon debug |
| 231 | /// |
| 232 | UINT32 SDBG:1; |
| 233 | /// |
| 234 | /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple |
| 235 | /// Add) extensions using YMM state. |
| 236 | /// |
| 237 | UINT32 FMA:1; |
| 238 | /// |
| 239 | /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature |
| 240 | /// is available. |
| 241 | /// |
| 242 | UINT32 CMPXCHG16B:1; |
| 243 | /// |
| 244 | /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor |
| 245 | /// supports changing IA32_MISC_ENABLE[Bit 23]. |
| 246 | /// |
| 247 | UINT32 xTPR_Update_Control:1; |
| 248 | /// |
| 249 | /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the |
| 250 | /// processor supports the performance and debug feature indication MSR |
| 251 | /// IA32_PERF_CAPABILITIES. |
| 252 | /// |
| 253 | UINT32 PDCM:1; |
| 254 | UINT32 Reserved:1; |
| 255 | /// |
| 256 | /// [Bit 17] Process-context identifiers. A value of 1 indicates that the |
| 257 | /// processor supports PCIDs and that software may set CR4.PCIDE to 1. |
| 258 | /// |
| 259 | UINT32 PCID:1; |
| 260 | /// |
| 261 | /// [Bit 18] A value of 1 indicates the processor supports the ability to |
| 262 | /// prefetch data from a memory mapped device. Direct Cache Access. |
| 263 | /// |
| 264 | UINT32 DCA:1; |
| 265 | /// |
| 266 | /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1. |
| 267 | /// |
| 268 | UINT32 SSE4_1:1; |
| 269 | /// |
| 270 | /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2. |
| 271 | /// |
| 272 | UINT32 SSE4_2:1; |
| 273 | /// |
| 274 | /// [Bit 21] A value of 1 indicates that the processor supports x2APIC |
| 275 | /// feature. |
| 276 | /// |
| 277 | UINT32 x2APIC:1; |
| 278 | /// |
| 279 | /// [Bit 22] A value of 1 indicates that the processor supports MOVBE |
| 280 | /// instruction. |
| 281 | /// |
| 282 | UINT32 MOVBE:1; |
| 283 | /// |
| 284 | /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT |
| 285 | /// instruction. |
| 286 | /// |
| 287 | UINT32 POPCNT:1; |
| 288 | /// |
| 289 | /// [Bit 24] A value of 1 indicates that the processor's local APIC timer |
| 290 | /// supports one-shot operation using a TSC deadline value. |
| 291 | /// |
| 292 | UINT32 TSC_Deadline:1; |
| 293 | /// |
| 294 | /// [Bit 25] A value of 1 indicates that the processor supports the AESNI |
| 295 | /// instruction extensions. |
| 296 | /// |
| 297 | UINT32 AESNI:1; |
| 298 | /// |
| 299 | /// [Bit 26] A value of 1 indicates that the processor supports the |
| 300 | /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV |
| 301 | /// instructions, and XCR0. |
| 302 | /// |
| 303 | UINT32 XSAVE:1; |
| 304 | /// |
| 305 | /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18] |
| 306 | /// to enable XSETBV/XGETBV instructions to access XCR0 and to support |
| 307 | /// processor extended state management using XSAVE/XRSTOR. |
| 308 | /// |
| 309 | UINT32 OSXSAVE:1; |
| 310 | /// |
| 311 | /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction |
| 312 | /// extensions. |
| 313 | /// |
| 314 | UINT32 AVX:1; |
| 315 | /// |
| 316 | /// [Bit 29] A value of 1 indicates that processor supports 16-bit |
| 317 | /// floating-point conversion instructions. |
| 318 | /// |
| 319 | UINT32 F16C:1; |
| 320 | /// |
| 321 | /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction. |
| 322 | /// |
| 323 | UINT32 RDRAND:1; |
| 324 | /// |
| 325 | /// [Bit 31] Always returns 0. |
| 326 | /// |
| 327 | UINT32 NotUsed:1; |
| 328 | } Bits; |
| 329 | /// |
| 330 | /// All bit fields as a 32-bit value |
| 331 | /// |
| 332 | UINT32 Uint32; |
| 333 | } CPUID_VERSION_INFO_ECX; |
| 334 | |
| 335 | /** |
| 336 | CPUID Version Information returned in EDX for CPUID leaf |
| 337 | #CPUID_VERSION_INFO. |
| 338 | **/ |
| 339 | typedef union { |
| 340 | /// |
| 341 | /// Individual bit fields |
| 342 | /// |
| 343 | struct { |
| 344 | /// |
| 345 | /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU. |
| 346 | /// |
| 347 | UINT32 FPU:1; |
| 348 | /// |
| 349 | /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, |
| 350 | /// including CR4.VME for controlling the feature, CR4.PVI for protected |
| 351 | /// mode virtual interrupts, software interrupt indirection, expansion of |
| 352 | /// the TSS with the software indirection bitmap, and EFLAGS.VIF and |
| 353 | /// EFLAGS.VIP flags. |
| 354 | /// |
| 355 | UINT32 VME:1; |
| 356 | /// |
| 357 | /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including |
| 358 | /// CR4.DE for controlling the feature, and optional trapping of accesses to |
| 359 | /// DR4 and DR5. |
| 360 | /// |
| 361 | UINT32 DE:1; |
| 362 | /// |
| 363 | /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported, |
| 364 | /// including CR4.PSE for controlling the feature, the defined dirty bit in |
| 365 | /// PDE (Page Directory Entries), optional reserved bit trapping in CR3, |
| 366 | /// PDEs, and PTEs. |
| 367 | /// |
| 368 | UINT32 PSE:1; |
| 369 | /// |
| 370 | /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported, |
| 371 | /// including CR4.TSD for controlling privilege. |
| 372 | /// |
| 373 | UINT32 TSC:1; |
| 374 | /// |
| 375 | /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The |
| 376 | /// RDMSR and WRMSR instructions are supported. Some of the MSRs are |
| 377 | /// implementation dependent. |
| 378 | /// |
| 379 | UINT32 MSR:1; |
| 380 | /// |
| 381 | /// [Bit 6] Physical Address Extension. Physical addresses greater than 32 |
| 382 | /// bits are supported: extended page table entry formats, an extra level in |
| 383 | /// the page translation tables is defined, 2-MByte pages are supported |
| 384 | /// instead of 4 Mbyte pages if PAE bit is 1. |
| 385 | /// |
| 386 | UINT32 PAE:1; |
| 387 | /// |
| 388 | /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine |
| 389 | /// Checks, including CR4.MCE for controlling the feature. This feature does |
| 390 | /// not define the model-specific implementations of machine-check error |
| 391 | /// logging, reporting, and processor shutdowns. Machine Check exception |
| 392 | /// handlers may have to depend on processor version to do model specific |
| 393 | /// processing of the exception, or test for the presence of the Machine |
| 394 | /// Check feature. |
| 395 | /// |
| 396 | UINT32 MCE:1; |
| 397 | /// |
| 398 | /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits) |
| 399 | /// instruction is supported (implicitly locked and atomic). |
| 400 | /// |
| 401 | UINT32 CX8:1; |
| 402 | /// |
| 403 | /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable |
| 404 | /// Interrupt Controller (APIC), responding to memory mapped commands in the |
| 405 | /// physical address range FFFE0000H to FFFE0FFFH (by default - some |
| 406 | /// processors permit the APIC to be relocated). |
| 407 | /// |
| 408 | UINT32 APIC:1; |
| 409 | UINT32 Reserved1:1; |
| 410 | /// |
| 411 | /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT |
| 412 | /// and associated MSRs are supported. |
| 413 | /// |
| 414 | UINT32 SEP:1; |
| 415 | /// |
| 416 | /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap |
| 417 | /// MSR contains feature bits that describe what memory types are supported, |
| 418 | /// how many variable MTRRs are supported, and whether fixed MTRRs are |
| 419 | /// supported. |
| 420 | /// |
| 421 | UINT32 MTRR:1; |
| 422 | /// |
| 423 | /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure |
| 424 | /// entries that map a page, indicating TLB entries that are common to |
| 425 | /// different processes and need not be flushed. The CR4.PGE bit controls |
| 426 | /// this feature. |
| 427 | /// |
| 428 | UINT32 PGE:1; |
| 429 | /// |
| 430 | /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine |
| 431 | /// Check Architecture of reporting machine errors is supported. The MCG_CAP |
| 432 | /// MSR contains feature bits describing how many banks of error reporting |
| 433 | /// MSRs are supported. |
| 434 | /// |
| 435 | UINT32 MCA:1; |
| 436 | /// |
| 437 | /// [Bit 15] Conditional Move Instructions. The conditional move instruction |
| 438 | /// CMOV is supported. In addition, if x87 FPU is present as indicated by the |
| 439 | /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported. |
| 440 | /// |
| 441 | UINT32 CMOV:1; |
| 442 | /// |
| 443 | /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This |
| 444 | /// feature augments the Memory Type Range Registers (MTRRs), allowing an |
| 445 | /// operating system to specify attributes of memory accessed through a |
| 446 | /// linear address on a 4KB granularity. |
| 447 | /// |
| 448 | UINT32 PAT:1; |
| 449 | /// |
| 450 | /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical |
| 451 | /// memory beyond 4 GBytes are supported with 32-bit paging. This feature |
| 452 | /// indicates that upper bits of the physical address of a 4-MByte page are |
| 453 | /// encoded in bits 20:13 of the page-directory entry. Such physical |
| 454 | /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size. |
| 455 | /// |
| 456 | UINT32 PSE_36:1; |
| 457 | /// |
| 458 | /// [Bit 18] Processor Serial Number. The processor supports the 96-bit |
| 459 | /// processor identification number feature and the feature is enabled. |
| 460 | /// |
| 461 | UINT32 PSN:1; |
| 462 | /// |
| 463 | /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported. |
| 464 | /// |
| 465 | UINT32 CLFSH:1; |
| 466 | UINT32 Reserved2:1; |
| 467 | /// |
| 468 | /// [Bit 21] Debug Store. The processor supports the ability to write debug |
| 469 | /// information into a memory resident buffer. This feature is used by the |
| 470 | /// branch trace store (BTS) and precise event-based sampling (PEBS) |
| 471 | /// facilities. |
| 472 | /// |
| 473 | UINT32 DS:1; |
| 474 | /// |
| 475 | /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The |
| 476 | /// processor implements internal MSRs that allow processor temperature to |
| 477 | /// be monitored and processor performance to be modulated in predefined |
| 478 | /// duty cycles under software control. |
| 479 | /// |
| 480 | UINT32 ACPI:1; |
| 481 | /// |
| 482 | /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX |
| 483 | /// technology. |
| 484 | /// |
| 485 | UINT32 MMX:1; |
| 486 | /// |
| 487 | /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR |
| 488 | /// instructions are supported for fast save and restore of the floating |
| 489 | /// point context. Presence of this bit also indicates that CR4.OSFXSR is |
| 490 | /// available for an operating system to indicate that it supports the |
| 491 | /// FXSAVE and FXRSTOR instructions. |
| 492 | /// |
| 493 | UINT32 FXSR:1; |
| 494 | /// |
| 495 | /// [Bit 25] SSE. The processor supports the SSE extensions. |
| 496 | /// |
| 497 | UINT32 SSE:1; |
| 498 | /// |
| 499 | /// [Bit 26] SSE2. The processor supports the SSE2 extensions. |
| 500 | /// |
| 501 | UINT32 SSE2:1; |
| 502 | /// |
| 503 | /// [Bit 27] Self Snoop. The processor supports the management of |
| 504 | /// conflicting memory types by performing a snoop of its own cache |
| 505 | /// structure for transactions issued to the bus. |
| 506 | /// |
| 507 | UINT32 SS:1; |
| 508 | /// |
| 509 | /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT |
| 510 | /// indicates there is only a single logical processor in the package and |
| 511 | /// software should assume only a single APIC ID is reserved. A value of 1 |
| 512 | /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of |
| 513 | /// addressable IDs for logical processors in this package) is valid for the |
| 514 | /// package. |
| 515 | /// |
| 516 | UINT32 HTT:1; |
| 517 | /// |
| 518 | /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor |
| 519 | /// automatic thermal control circuitry (TCC). |
| 520 | /// |
| 521 | UINT32 TM:1; |
| 522 | UINT32 Reserved3:1; |
| 523 | /// |
| 524 | /// [Bit 31] Pending Break Enable. The processor supports the use of the |
| 525 | /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is |
| 526 | /// asserted) to signal the processor that an interrupt is pending and that |
| 527 | /// the processor should return to normal operation to handle the interrupt. |
| 528 | /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability. |
| 529 | /// |
| 530 | UINT32 PBE:1; |
| 531 | } Bits; |
| 532 | /// |
| 533 | /// All bit fields as a 32-bit value |
| 534 | /// |
| 535 | UINT32 Uint32; |
| 536 | } CPUID_VERSION_INFO_EDX; |
| 537 | |
| 538 | |
| 539 | /** |
| 540 | CPUID Cache and TLB Information |
| 541 | |
| 542 | @param EAX CPUID_CACHE_INFO (0x02) |
| 543 | |
| 544 | @retval EAX Cache and TLB Information described by the type |
| 545 | CPUID_CACHE_INFO_CACHE_TLB. |
| 546 | CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns |
| 547 | 0x01 and must be ignored. Only valid if |
| 548 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. |
| 549 | @retval EBX Cache and TLB Information described by the type |
| 550 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if |
| 551 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. |
| 552 | @retval ECX Cache and TLB Information described by the type |
| 553 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if |
| 554 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. |
| 555 | @retval EDX Cache and TLB Information described by the type |
| 556 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if |
| 557 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. |
| 558 | |
| 559 | <b>Example usage</b> |
| 560 | @code |
| 561 | CPUID_CACHE_INFO_CACHE_TLB Eax; |
| 562 | CPUID_CACHE_INFO_CACHE_TLB Ebx; |
| 563 | CPUID_CACHE_INFO_CACHE_TLB Ecx; |
| 564 | CPUID_CACHE_INFO_CACHE_TLB Edx; |
| 565 | |
| 566 | AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); |
| 567 | @endcode |
| 568 | |
| 569 | <b>Cache Descriptor values</b> |
| 570 | <table> |
| 571 | <tr><th>Value </th><th> Type </th><th> Description </th></tr> |
| 572 | <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr> |
| 573 | <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr> |
| 574 | <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr> |
| 575 | <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr> |
| 576 | <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr> |
| 577 | <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr> |
| 578 | <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative, |
| 579 | 32 byte line size</td></tr> |
| 580 | <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative, |
| 581 | 32 byte line size</td></tr> |
| 582 | <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative, |
| 583 | 64 byte line size</td></tr> |
| 584 | <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr> |
| 585 | <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr> |
| 586 | <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr> |
| 587 | <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr> |
| 588 | <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr> |
| 589 | <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr> |
| 590 | <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr> |
| 591 | <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, |
| 592 | 2 lines per sector</td></tr> |
| 593 | <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, |
| 594 | 2 lines per sector</td></tr> |
| 595 | <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr> |
| 596 | <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, |
| 597 | 2 lines per sector</td></tr> |
| 598 | <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, |
| 599 | 2 lines per sector</td></tr> |
| 600 | <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative, |
| 601 | 64 byte line size</td></tr> |
| 602 | <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative, |
| 603 | 64 byte line size</td></tr> |
| 604 | <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache, |
| 605 | no 3rd-level cache</td></tr> |
| 606 | <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr> |
| 607 | <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr> |
| 608 | <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr> |
| 609 | <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr> |
| 610 | <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr> |
| 611 | <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr> |
| 612 | <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr> |
| 613 | <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr> |
| 614 | <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size |
| 615 | (Intel Xeon processor MP, Family 0FH, Model 06H)<BR> |
| 616 | 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr> |
| 617 | <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr> |
| 618 | <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr> |
| 619 | <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr> |
| 620 | <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr> |
| 621 | <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr> |
| 622 | <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr> |
| 623 | <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr> |
| 624 | <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr> |
| 625 | <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr> |
| 626 | <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr> |
| 627 | <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr> |
| 628 | <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr> |
| 629 | <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr> |
| 630 | <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr> |
| 631 | <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr> |
| 632 | <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr> |
| 633 | <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr> |
| 634 | <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr> |
| 635 | <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr> |
| 636 | <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, |
| 637 | 32 entries and a separate array with 1 GByte pages, 4-way set associative, |
| 638 | 4 entries</td></tr> |
| 639 | <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr> |
| 640 | <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr> |
| 641 | <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr> |
| 642 | <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr> |
| 643 | <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr> |
| 644 | <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr> |
| 645 | <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr> |
| 646 | <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr> |
| 647 | <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr> |
| 648 | <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr> |
| 649 | <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr> |
| 650 | <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr> |
| 651 | <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr> |
| 652 | <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, |
| 653 | 2 lines per sector</td></tr> |
| 654 | <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, |
| 655 | 2 lines per sector</td></tr> |
| 656 | <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, |
| 657 | 2 lines per sector</td></tr> |
| 658 | <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, |
| 659 | 2 lines per sector</td></tr> |
| 660 | <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr> |
| 661 | <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr> |
| 662 | <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr> |
| 663 | <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr> |
| 664 | <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr> |
| 665 | <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr> |
| 666 | <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr> |
| 667 | <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr> |
| 668 | <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr> |
| 669 | <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr> |
| 670 | <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr> |
| 671 | <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr> |
| 672 | <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr> |
| 673 | <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr> |
| 674 | <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr> |
| 675 | <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr> |
| 676 | <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, |
| 677 | 128 entries</td></tr> |
| 678 | <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr> |
| 679 | <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr> |
| 680 | <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, |
| 681 | 1024 entries</td></tr> |
| 682 | <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr> |
| 683 | <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, |
| 684 | 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr> |
| 685 | <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr> |
| 686 | <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr> |
| 687 | <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr> |
| 688 | <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr> |
| 689 | <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr> |
| 690 | <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr> |
| 691 | <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr> |
| 692 | <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr> |
| 693 | <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr> |
| 694 | <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr> |
| 695 | <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr> |
| 696 | <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr> |
| 697 | <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr> |
| 698 | <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr> |
| 699 | <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr> |
| 700 | <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr> |
| 701 | <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr> |
| 702 | <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr> |
| 703 | <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr> |
| 704 | <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID |
| 705 | leaf 18H to query TLB and other address translation parameters.</td></tr> |
| 706 | <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information, |
| 707 | use CPUID leaf 4 to query cache parameters</td></tr> |
| 708 | </table> |
| 709 | **/ |
| 710 | #define CPUID_CACHE_INFO 0x02 |
| 711 | |
| 712 | /** |
| 713 | CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID |
| 714 | leaf #CPUID_CACHE_INFO. |
| 715 | **/ |
| 716 | typedef union { |
| 717 | /// |
| 718 | /// Individual bit fields |
| 719 | /// |
| 720 | struct { |
| 721 | UINT32 Reserved:31; |
| 722 | /// |
| 723 | /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid. |
| 724 | /// if 1, then none of the cache descriptor bytes in the register are valid. |
| 725 | /// |
| 726 | UINT32 NotValid:1; |
| 727 | } Bits; |
| 728 | /// |
| 729 | /// Array of Cache and TLB descriptor bytes |
| 730 | /// |
| 731 | UINT8 CacheDescriptor[4]; |
| 732 | /// |
| 733 | /// All bit fields as a 32-bit value |
| 734 | /// |
| 735 | UINT32 Uint32; |
| 736 | } CPUID_CACHE_INFO_CACHE_TLB; |
| 737 | |
| 738 | |
| 739 | /** |
| 740 | CPUID Processor Serial Number |
| 741 | |
| 742 | Processor serial number (PSN) is not supported in the Pentium 4 processor |
| 743 | or later. On all models, use the PSN flag (returned using CPUID) to check |
| 744 | for PSN support before accessing the feature. |
| 745 | |
| 746 | @param EAX CPUID_SERIAL_NUMBER (0x03) |
| 747 | |
| 748 | @retval EAX Reserved. |
| 749 | @retval EBX Reserved. |
| 750 | @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in |
| 751 | Pentium III processor only; otherwise, the value in this |
| 752 | register is reserved.) |
| 753 | @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in |
| 754 | Pentium III processor only; otherwise, the value in this |
| 755 | register is reserved.) |
| 756 | |
| 757 | <b>Example usage</b> |
| 758 | @code |
| 759 | UINT32 Ecx; |
| 760 | UINT32 Edx; |
| 761 | |
| 762 | AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx); |
| 763 | @endcode |
| 764 | **/ |
| 765 | #define CPUID_SERIAL_NUMBER 0x03 |
| 766 | |
| 767 | |
| 768 | /** |
| 769 | CPUID Cache Parameters |
| 770 | |
| 771 | @param EAX CPUID_CACHE_PARAMS (0x04) |
| 772 | @param ECX Cache Level. Valid values start at 0. Software can enumerate |
| 773 | the deterministic cache parameters for each level of the cache |
| 774 | hierarchy starting with an index value of 0, until the |
| 775 | parameters report the value associated with the CacheType |
| 776 | field in CPUID_CACHE_PARAMS_EAX is 0. |
| 777 | |
| 778 | @retval EAX Returns cache type information described by the type |
| 779 | CPUID_CACHE_PARAMS_EAX. |
| 780 | @retval EBX Returns cache line and associativity information described by |
| 781 | the type CPUID_CACHE_PARAMS_EBX. |
| 782 | @retval ECX Returns the number of sets in the cache. |
| 783 | @retval EDX Returns cache WINVD/INVD behavior described by the type |
| 784 | CPUID_CACHE_PARAMS_EDX. |
| 785 | |
| 786 | <b>Example usage</b> |
| 787 | @code |
| 788 | UINT32 CacheLevel; |
| 789 | CPUID_CACHE_PARAMS_EAX Eax; |
| 790 | CPUID_CACHE_PARAMS_EBX Ebx; |
| 791 | UINT32 Ecx; |
| 792 | CPUID_CACHE_PARAMS_EDX Edx; |
| 793 | |
| 794 | CacheLevel = 0; |
| 795 | do { |
| 796 | AsmCpuidEx ( |
| 797 | CPUID_CACHE_PARAMS, CacheLevel, |
| 798 | &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32 |
| 799 | ); |
| 800 | CacheLevel++; |
| 801 | } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL); |
| 802 | @endcode |
| 803 | **/ |
| 804 | #define CPUID_CACHE_PARAMS 0x04 |
| 805 | |
| 806 | /** |
| 807 | CPUID Cache Parameters Information returned in EAX for CPUID leaf |
| 808 | #CPUID_CACHE_PARAMS. |
| 809 | **/ |
| 810 | typedef union { |
| 811 | /// |
| 812 | /// Individual bit fields |
| 813 | /// |
| 814 | struct { |
| 815 | /// |
| 816 | /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL, |
| 817 | /// then there is no information for the requested cache level. |
| 818 | /// |
| 819 | UINT32 CacheType:5; |
| 820 | /// |
| 821 | /// [Bits 7:5] Cache level (Starts at 1). |
| 822 | /// |
| 823 | UINT32 CacheLevel:3; |
| 824 | /// |
| 825 | /// [Bit 8] Self Initializing cache level (does not need SW initialization). |
| 826 | /// |
| 827 | UINT32 SelfInitializingCache:1; |
| 828 | /// |
| 829 | /// [Bit 9] Fully Associative cache. |
| 830 | /// |
| 831 | UINT32 FullyAssociativeCache:1; |
| 832 | /// |
| 833 | /// [Bits 13:10] Reserved. |
| 834 | /// |
| 835 | UINT32 Reserved:4; |
| 836 | /// |
| 837 | /// [Bits 25:14] Maximum number of addressable IDs for logical processors |
| 838 | /// sharing this cache. |
| 839 | /// |
| 840 | /// Add one to the return value to get the result. |
| 841 | /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) |
| 842 | /// is the number of unique initial APIC IDs reserved for addressing |
| 843 | /// different logical processors sharing this cache. |
| 844 | /// |
| 845 | UINT32 MaximumAddressableIdsForLogicalProcessors:12; |
| 846 | /// |
| 847 | /// [Bits 31:26] Maximum number of addressable IDs for processor cores in |
| 848 | /// the physical package. |
| 849 | /// |
| 850 | /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) |
| 851 | /// is the number of unique Core_IDs reserved for addressing different |
| 852 | /// processor cores in a physical package. Core ID is a subset of bits of |
| 853 | /// the initial APIC ID. |
| 854 | /// The returned value is constant for valid initial values in ECX. Valid |
| 855 | /// ECX values start from 0. |
| 856 | /// |
| 857 | UINT32 MaximumAddressableIdsForProcessorCores:6; |
| 858 | } Bits; |
| 859 | /// |
| 860 | /// All bit fields as a 32-bit value |
| 861 | /// |
| 862 | UINT32 Uint32; |
| 863 | } CPUID_CACHE_PARAMS_EAX; |
| 864 | |
| 865 | /// |
| 866 | /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType |
| 867 | /// |
| 868 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00 |
| 869 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01 |
| 870 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02 |
| 871 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03 |
| 872 | /// |
| 873 | /// @} |
| 874 | /// |
| 875 | |
| 876 | /** |
| 877 | CPUID Cache Parameters Information returned in EBX for CPUID leaf |
| 878 | #CPUID_CACHE_PARAMS. |
| 879 | **/ |
| 880 | typedef union { |
| 881 | /// |
| 882 | /// Individual bit fields |
| 883 | /// |
| 884 | struct { |
| 885 | /// |
| 886 | /// [Bits 11:0] System Coherency Line Size. Add one to the return value to |
| 887 | /// get the result. |
| 888 | /// |
| 889 | UINT32 LineSize:12; |
| 890 | /// |
| 891 | /// [Bits 21:12] Physical Line Partitions. Add one to the return value to |
| 892 | /// get the result. |
| 893 | /// |
| 894 | UINT32 LinePartitions:10; |
| 895 | /// |
| 896 | /// [Bits 31:22] Ways of associativity. Add one to the return value to get |
| 897 | /// the result. |
| 898 | /// |
| 899 | UINT32 Ways:10; |
| 900 | } Bits; |
| 901 | /// |
| 902 | /// All bit fields as a 32-bit value |
| 903 | /// |
| 904 | UINT32 Uint32; |
| 905 | } CPUID_CACHE_PARAMS_EBX; |
| 906 | |
| 907 | /** |
| 908 | CPUID Cache Parameters Information returned in EDX for CPUID leaf |
| 909 | #CPUID_CACHE_PARAMS. |
| 910 | **/ |
| 911 | typedef union { |
| 912 | /// |
| 913 | /// Individual bit fields |
| 914 | /// |
| 915 | struct { |
| 916 | /// |
| 917 | /// [Bit 0] Write-Back Invalidate/Invalidate. |
| 918 | /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level |
| 919 | /// caches for threads sharing this cache. |
| 920 | /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of |
| 921 | /// non-originating threads sharing this cache. |
| 922 | /// |
| 923 | UINT32 Invalidate:1; |
| 924 | /// |
| 925 | /// [Bit 1] Cache Inclusiveness. |
| 926 | /// 0 = Cache is not inclusive of lower cache levels. |
| 927 | /// 1 = Cache is inclusive of lower cache levels. |
| 928 | /// |
| 929 | UINT32 CacheInclusiveness:1; |
| 930 | /// |
| 931 | /// [Bit 2] Complex Cache Indexing. |
| 932 | /// 0 = Direct mapped cache. |
| 933 | /// 1 = A complex function is used to index the cache, potentially using all |
| 934 | /// address bits. |
| 935 | /// |
| 936 | UINT32 ComplexCacheIndexing:1; |
| 937 | UINT32 Reserved:29; |
| 938 | } Bits; |
| 939 | /// |
| 940 | /// All bit fields as a 32-bit value |
| 941 | /// |
| 942 | UINT32 Uint32; |
| 943 | } CPUID_CACHE_PARAMS_EDX; |
| 944 | |
| 945 | |
| 946 | /** |
| 947 | CPUID MONITOR/MWAIT Information |
| 948 | |
| 949 | @param EAX CPUID_MONITOR_MWAIT (0x05) |
| 950 | |
| 951 | @retval EAX Smallest monitor-line size in bytes described by the type |
| 952 | CPUID_MONITOR_MWAIT_EAX. |
| 953 | @retval EBX Largest monitor-line size in bytes described by the type |
| 954 | CPUID_MONITOR_MWAIT_EBX. |
| 955 | @retval ECX Enumeration of Monitor-Mwait extensions support described by |
| 956 | the type CPUID_MONITOR_MWAIT_ECX. |
| 957 | @retval EDX Sub C-states supported described by the type |
| 958 | CPUID_MONITOR_MWAIT_EDX. |
| 959 | |
| 960 | <b>Example usage</b> |
| 961 | @code |
| 962 | CPUID_MONITOR_MWAIT_EAX Eax; |
| 963 | CPUID_MONITOR_MWAIT_EBX Ebx; |
| 964 | CPUID_MONITOR_MWAIT_ECX Ecx; |
| 965 | CPUID_MONITOR_MWAIT_EDX Edx; |
| 966 | |
| 967 | AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); |
| 968 | @endcode |
| 969 | **/ |
| 970 | #define CPUID_MONITOR_MWAIT 0x05 |
| 971 | |
| 972 | /** |
| 973 | CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf |
| 974 | #CPUID_MONITOR_MWAIT. |
| 975 | **/ |
| 976 | typedef union { |
| 977 | /// |
| 978 | /// Individual bit fields |
| 979 | /// |
| 980 | struct { |
| 981 | /// |
| 982 | /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's |
| 983 | /// monitor granularity). |
| 984 | /// |
| 985 | UINT32 SmallestMonitorLineSize:16; |
| 986 | UINT32 Reserved:16; |
| 987 | } Bits; |
| 988 | /// |
| 989 | /// All bit fields as a 32-bit value |
| 990 | /// |
| 991 | UINT32 Uint32; |
| 992 | } CPUID_MONITOR_MWAIT_EAX; |
| 993 | |
| 994 | /** |
| 995 | CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf |
| 996 | #CPUID_MONITOR_MWAIT. |
| 997 | **/ |
| 998 | typedef union { |
| 999 | /// |
| 1000 | /// Individual bit fields |
| 1001 | /// |
| 1002 | struct { |
| 1003 | /// |
| 1004 | /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's |
| 1005 | /// monitor granularity). |
| 1006 | /// |
| 1007 | UINT32 LargestMonitorLineSize:16; |
| 1008 | UINT32 Reserved:16; |
| 1009 | } Bits; |
| 1010 | /// |
| 1011 | /// All bit fields as a 32-bit value |
| 1012 | /// |
| 1013 | UINT32 Uint32; |
| 1014 | } CPUID_MONITOR_MWAIT_EBX; |
| 1015 | |
| 1016 | /** |
| 1017 | CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf |
| 1018 | #CPUID_MONITOR_MWAIT. |
| 1019 | **/ |
| 1020 | typedef union { |
| 1021 | /// |
| 1022 | /// Individual bit fields |
| 1023 | /// |
| 1024 | struct { |
| 1025 | /// |
| 1026 | /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX, |
| 1027 | /// and EDX are valid. |
| 1028 | /// |
| 1029 | UINT32 ExtensionsSupported:1; |
| 1030 | /// |
| 1031 | /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when |
| 1032 | /// interrupts disabled. |
| 1033 | /// |
| 1034 | UINT32 InterruptAsBreak:1; |
| 1035 | UINT32 Reserved:30; |
| 1036 | } Bits; |
| 1037 | /// |
| 1038 | /// All bit fields as a 32-bit value |
| 1039 | /// |
| 1040 | UINT32 Uint32; |
| 1041 | } CPUID_MONITOR_MWAIT_ECX; |
| 1042 | |
| 1043 | /** |
| 1044 | CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf |
| 1045 | #CPUID_MONITOR_MWAIT. |
| 1046 | |
| 1047 | @note |
| 1048 | The definition of C0 through C7 states for MWAIT extension are |
| 1049 | processor-specific C-states, not ACPI C-states. |
| 1050 | **/ |
| 1051 | typedef union { |
| 1052 | /// |
| 1053 | /// Individual bit fields |
| 1054 | /// |
| 1055 | struct { |
| 1056 | /// |
| 1057 | /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT. |
| 1058 | /// |
| 1059 | UINT32 C0States:4; |
| 1060 | /// |
| 1061 | /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT. |
| 1062 | /// |
| 1063 | UINT32 C1States:4; |
| 1064 | /// |
| 1065 | /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT. |
| 1066 | /// |
| 1067 | UINT32 C2States:4; |
| 1068 | /// |
| 1069 | /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT. |
| 1070 | /// |
| 1071 | UINT32 C3States:4; |
| 1072 | /// |
| 1073 | /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT. |
| 1074 | /// |
| 1075 | UINT32 C4States:4; |
| 1076 | /// |
| 1077 | /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT. |
| 1078 | /// |
| 1079 | UINT32 C5States:4; |
| 1080 | /// |
| 1081 | /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT. |
| 1082 | /// |
| 1083 | UINT32 C6States:4; |
| 1084 | /// |
| 1085 | /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT. |
| 1086 | /// |
| 1087 | UINT32 C7States:4; |
| 1088 | } Bits; |
| 1089 | /// |
| 1090 | /// All bit fields as a 32-bit value |
| 1091 | /// |
| 1092 | UINT32 Uint32; |
| 1093 | } CPUID_MONITOR_MWAIT_EDX; |
| 1094 | |
| 1095 | |
| 1096 | /** |
| 1097 | CPUID Thermal and Power Management |
| 1098 | |
| 1099 | @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06) |
| 1100 | |
| 1101 | @retval EAX Thermal and power management features described by the type |
| 1102 | CPUID_THERMAL_POWER_MANAGEMENT_EAX. |
| 1103 | @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor |
| 1104 | described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX. |
| 1105 | @retval ECX Performance features described by the type |
| 1106 | CPUID_THERMAL_POWER_MANAGEMENT_ECX. |
| 1107 | @retval EDX Reserved. |
| 1108 | |
| 1109 | <b>Example usage</b> |
| 1110 | @code |
| 1111 | CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax; |
| 1112 | CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx; |
| 1113 | CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx; |
| 1114 | |
| 1115 | AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); |
| 1116 | @endcode |
| 1117 | **/ |
| 1118 | #define CPUID_THERMAL_POWER_MANAGEMENT 0x06 |
| 1119 | |
| 1120 | /** |
| 1121 | CPUID Thermal and Power Management Information returned in EAX for CPUID leaf |
| 1122 | #CPUID_THERMAL_POWER_MANAGEMENT. |
| 1123 | **/ |
| 1124 | typedef union { |
| 1125 | /// |
| 1126 | /// Individual bit fields |
| 1127 | /// |
| 1128 | struct { |
| 1129 | /// |
| 1130 | /// [Bit 0] Digital temperature sensor is supported if set. |
| 1131 | /// |
| 1132 | UINT32 DigitalTemperatureSensor:1; |
| 1133 | /// |
| 1134 | /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]). |
| 1135 | /// |
| 1136 | UINT32 TurboBoostTechnology:1; |
| 1137 | /// |
| 1138 | /// [Bit 2] APIC-Timer-always-running feature is supported if set. |
| 1139 | /// |
| 1140 | UINT32 ARAT:1; |
| 1141 | UINT32 Reserved1:1; |
| 1142 | /// |
| 1143 | /// [Bit 4] Power limit notification controls are supported if set. |
| 1144 | /// |
| 1145 | UINT32 PLN:1; |
| 1146 | /// |
| 1147 | /// [Bit 5] Clock modulation duty cycle extension is supported if set. |
| 1148 | /// |
| 1149 | UINT32 ECMD:1; |
| 1150 | /// |
| 1151 | /// [Bit 6] Package thermal management is supported if set. |
| 1152 | /// |
| 1153 | UINT32 PTM:1; |
| 1154 | /// |
| 1155 | /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES, |
| 1156 | /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set. |
| 1157 | /// |
| 1158 | UINT32 HWP:1; |
| 1159 | /// |
| 1160 | /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set. |
| 1161 | /// |
| 1162 | UINT32 HWP_Notification:1; |
| 1163 | /// |
| 1164 | /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set. |
| 1165 | /// |
| 1166 | UINT32 HWP_Activity_Window:1; |
| 1167 | /// |
| 1168 | /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set. |
| 1169 | /// |
| 1170 | UINT32 HWP_Energy_Performance_Preference:1; |
| 1171 | /// |
| 1172 | /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set. |
| 1173 | /// |
| 1174 | UINT32 HWP_Package_Level_Request:1; |
| 1175 | UINT32 Reserved2:1; |
| 1176 | /// |
| 1177 | /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, |
| 1178 | /// IA32_THREAD_STALL MSRs are supported if set. |
| 1179 | /// |
| 1180 | UINT32 HDC:1; |
| 1181 | /// |
| 1182 | /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available. |
| 1183 | /// |
| 1184 | UINT32 TurboBoostMaxTechnology30:1; |
| 1185 | /// |
| 1186 | /// [Bit 15] HWP Capabilities. |
| 1187 | /// Highest Performance change is supported if set. |
| 1188 | /// |
| 1189 | UINT32 HWPCapabilities:1; |
| 1190 | /// |
| 1191 | /// [Bit 16] HWP PECI override is supported if set. |
| 1192 | /// |
| 1193 | UINT32 HWPPECIOverride:1; |
| 1194 | /// |
| 1195 | /// [Bit 17] Flexible HWP is supported if set. |
| 1196 | /// |
| 1197 | UINT32 FlexibleHWP:1; |
| 1198 | /// |
| 1199 | /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set. |
| 1200 | /// |
| 1201 | UINT32 FastAccessMode:1; |
| 1202 | UINT32 Reserved4:1; |
| 1203 | /// |
| 1204 | /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set. |
| 1205 | /// |
| 1206 | UINT32 IgnoringIdleLogicalProcessorHWPRequest:1; |
| 1207 | UINT32 Reserved5:11; |
| 1208 | } Bits; |
| 1209 | /// |
| 1210 | /// All bit fields as a 32-bit value |
| 1211 | /// |
| 1212 | UINT32 Uint32; |
| 1213 | } CPUID_THERMAL_POWER_MANAGEMENT_EAX; |
| 1214 | |
| 1215 | /** |
| 1216 | CPUID Thermal and Power Management Information returned in EBX for CPUID leaf |
| 1217 | #CPUID_THERMAL_POWER_MANAGEMENT. |
| 1218 | **/ |
| 1219 | typedef union { |
| 1220 | /// |
| 1221 | /// Individual bit fields |
| 1222 | /// |
| 1223 | struct { |
| 1224 | /// |
| 1225 | /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor. |
| 1226 | /// |
| 1227 | UINT32 InterruptThresholds:4; |
| 1228 | UINT32 Reserved:28; |
| 1229 | } Bits; |
| 1230 | /// |
| 1231 | /// All bit fields as a 32-bit value |
| 1232 | /// |
| 1233 | UINT32 Uint32; |
| 1234 | } CPUID_THERMAL_POWER_MANAGEMENT_EBX; |
| 1235 | |
| 1236 | /** |
| 1237 | CPUID Thermal and Power Management Information returned in ECX for CPUID leaf |
| 1238 | #CPUID_THERMAL_POWER_MANAGEMENT. |
| 1239 | **/ |
| 1240 | typedef union { |
| 1241 | /// |
| 1242 | /// Individual bit fields |
| 1243 | /// |
| 1244 | struct { |
| 1245 | /// |
| 1246 | /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF |
| 1247 | /// and IA32_APERF). The capability to provide a measure of delivered |
| 1248 | /// processor performance (since last reset of the counters), as a percentage |
| 1249 | /// of the expected processor performance when running at the TSC frequency. |
| 1250 | /// |
| 1251 | UINT32 HardwareCoordinationFeedback:1; |
| 1252 | UINT32 Reserved1:2; |
| 1253 | /// |
| 1254 | /// [Bit 3] If this bit is set, then the processor supports performance-energy |
| 1255 | /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS |
| 1256 | /// (1B0H). |
| 1257 | /// |
| 1258 | UINT32 PerformanceEnergyBias:1; |
| 1259 | UINT32 Reserved2:28; |
| 1260 | } Bits; |
| 1261 | /// |
| 1262 | /// All bit fields as a 32-bit value |
| 1263 | /// |
| 1264 | UINT32 Uint32; |
| 1265 | } CPUID_THERMAL_POWER_MANAGEMENT_ECX; |
| 1266 | |
| 1267 | |
| 1268 | /** |
| 1269 | CPUID Structured Extended Feature Flags Enumeration |
| 1270 | |
| 1271 | @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) |
| 1272 | @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00). |
| 1273 | |
| 1274 | @note |
| 1275 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf |
| 1276 | index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. |
| 1277 | |
| 1278 | @retval EAX The maximum input value for ECX to retrieve sub-leaf information. |
| 1279 | @retval EBX Structured Extended Feature Flags described by the type |
| 1280 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX. |
| 1281 | @retval ECX Structured Extended Feature Flags described by the type |
| 1282 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX. |
| 1283 | @retval EDX Reserved. |
| 1284 | |
| 1285 | <b>Example usage</b> |
| 1286 | @code |
| 1287 | UINT32 Eax; |
| 1288 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; |
| 1289 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx; |
| 1290 | UINT32 SubLeaf; |
| 1291 | |
| 1292 | AsmCpuidEx ( |
| 1293 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, |
| 1294 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, |
| 1295 | &Eax, NULL, NULL, NULL |
| 1296 | ); |
| 1297 | for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) { |
| 1298 | AsmCpuidEx ( |
| 1299 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, |
| 1300 | SubLeaf, |
| 1301 | NULL, &Ebx.Uint32, &Ecx.Uint32, NULL |
| 1302 | ); |
| 1303 | } |
| 1304 | @endcode |
| 1305 | **/ |
| 1306 | #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 |
| 1307 | |
| 1308 | /// |
| 1309 | /// CPUID Structured Extended Feature Flags Enumeration sub-leaf |
| 1310 | /// |
| 1311 | #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00 |
| 1312 | |
| 1313 | /** |
| 1314 | CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf |
| 1315 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf |
| 1316 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. |
| 1317 | **/ |
| 1318 | typedef union { |
| 1319 | /// |
| 1320 | /// Individual bit fields |
| 1321 | /// |
| 1322 | struct { |
| 1323 | /// |
| 1324 | /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. |
| 1325 | /// |
| 1326 | UINT32 FSGSBASE:1; |
| 1327 | /// |
| 1328 | /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1. |
| 1329 | /// |
| 1330 | UINT32 IA32_TSC_ADJUST:1; |
| 1331 | /// |
| 1332 | /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT |
| 1333 | /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS". |
| 1334 | /// |
| 1335 | UINT32 SGX:1; |
| 1336 | /// |
| 1337 | /// [Bit 3] If 1 indicates the processor supports the first group of advanced |
| 1338 | /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT) |
| 1339 | /// |
| 1340 | UINT32 BMI1:1; |
| 1341 | /// |
| 1342 | /// [Bit 4] Hardware Lock Elision |
| 1343 | /// |
| 1344 | UINT32 HLE:1; |
| 1345 | /// |
| 1346 | /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions. |
| 1347 | /// |
| 1348 | UINT32 AVX2:1; |
| 1349 | /// |
| 1350 | /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1. |
| 1351 | /// |
| 1352 | UINT32 FDP_EXCPTN_ONLY:1; |
| 1353 | /// |
| 1354 | /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1. |
| 1355 | /// |
| 1356 | UINT32 SMEP:1; |
| 1357 | /// |
| 1358 | /// [Bit 8] If 1 indicates the processor supports the second group of |
| 1359 | /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, |
| 1360 | /// SARX, SHLX, SHRX) |
| 1361 | /// |
| 1362 | UINT32 BMI2:1; |
| 1363 | /// |
| 1364 | /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1. |
| 1365 | /// |
| 1366 | UINT32 EnhancedRepMovsbStosb:1; |
| 1367 | /// |
| 1368 | /// [Bit 10] If 1, supports INVPCID instruction for system software that |
| 1369 | /// manages process-context identifiers. |
| 1370 | /// |
| 1371 | UINT32 INVPCID:1; |
| 1372 | /// |
| 1373 | /// [Bit 11] Restricted Transactional Memory |
| 1374 | /// |
| 1375 | UINT32 RTM:1; |
| 1376 | /// |
| 1377 | /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT) |
| 1378 | /// Monitoring capability if 1. |
| 1379 | /// |
| 1380 | UINT32 RDT_M:1; |
| 1381 | /// |
| 1382 | /// [Bit 13] Deprecates FPU CS and FPU DS values if 1. |
| 1383 | /// |
| 1384 | UINT32 DeprecateFpuCsDs:1; |
| 1385 | /// |
| 1386 | /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1. |
| 1387 | /// |
| 1388 | UINT32 MPX:1; |
| 1389 | /// |
| 1390 | /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT) |
| 1391 | /// Allocation capability if 1. |
| 1392 | /// |
| 1393 | UINT32 RDT_A:1; |
| 1394 | /// |
| 1395 | /// [Bit 16] AVX512F. |
| 1396 | /// |
| 1397 | UINT32 AVX512F:1; |
| 1398 | /// |
| 1399 | /// [Bit 17] AVX512DQ. |
| 1400 | /// |
| 1401 | UINT32 AVX512DQ:1; |
| 1402 | /// |
| 1403 | /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction. |
| 1404 | /// |
| 1405 | UINT32 RDSEED:1; |
| 1406 | /// |
| 1407 | /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX |
| 1408 | /// instructions. |
| 1409 | /// |
| 1410 | UINT32 ADX:1; |
| 1411 | /// |
| 1412 | /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC |
| 1413 | /// instructions) if 1. |
| 1414 | /// |
| 1415 | UINT32 SMAP:1; |
| 1416 | /// |
| 1417 | /// [Bit 21] AVX512_IFMA. |
| 1418 | /// |
| 1419 | UINT32 AVX512_IFMA:1; |
| 1420 | UINT32 Reserved6:1; |
| 1421 | /// |
| 1422 | /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction. |
| 1423 | /// |
| 1424 | UINT32 CLFLUSHOPT:1; |
| 1425 | /// |
| 1426 | /// [Bit 24] If 1 indicates the processor supports the CLWB instruction. |
| 1427 | /// |
| 1428 | UINT32 CLWB:1; |
| 1429 | /// |
| 1430 | /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace |
| 1431 | /// extensions. |
| 1432 | /// |
| 1433 | UINT32 IntelProcessorTrace:1; |
| 1434 | /// |
| 1435 | /// [Bit 26] AVX512PF. (Intel Xeon Phi only.). |
| 1436 | /// |
| 1437 | UINT32 AVX512PF:1; |
| 1438 | /// |
| 1439 | /// [Bit 27] AVX512ER. (Intel Xeon Phi only.). |
| 1440 | /// |
| 1441 | UINT32 AVX512ER:1; |
| 1442 | /// |
| 1443 | /// [Bit 28] AVX512CD. |
| 1444 | /// |
| 1445 | UINT32 AVX512CD:1; |
| 1446 | /// |
| 1447 | /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R) |
| 1448 | /// SHA Extensions) if 1. |
| 1449 | /// |
| 1450 | UINT32 SHA:1; |
| 1451 | /// |
| 1452 | /// [Bit 30] AVX512BW. |
| 1453 | /// |
| 1454 | UINT32 AVX512BW:1; |
| 1455 | /// |
| 1456 | /// [Bit 31] AVX512VL. |
| 1457 | /// |
| 1458 | UINT32 AVX512VL:1; |
| 1459 | } Bits; |
| 1460 | /// |
| 1461 | /// All bit fields as a 32-bit value |
| 1462 | /// |
| 1463 | UINT32 Uint32; |
| 1464 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX; |
| 1465 | |
| 1466 | /** |
| 1467 | CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf |
| 1468 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf |
| 1469 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. |
| 1470 | **/ |
| 1471 | typedef union { |
| 1472 | /// |
| 1473 | /// Individual bit fields |
| 1474 | /// |
| 1475 | struct { |
| 1476 | /// |
| 1477 | /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction. |
| 1478 | /// (Intel Xeon Phi only.) |
| 1479 | /// |
| 1480 | UINT32 PREFETCHWT1:1; |
| 1481 | /// |
| 1482 | /// [Bit 1] AVX512_VBMI. |
| 1483 | /// |
| 1484 | UINT32 AVX512_VBMI:1; |
| 1485 | /// |
| 1486 | /// [Bit 2] Supports user-mode instruction prevention if 1. |
| 1487 | /// |
| 1488 | UINT32 UMIP:1; |
| 1489 | /// |
| 1490 | /// [Bit 3] Supports protection keys for user-mode pages if 1. |
| 1491 | /// |
| 1492 | UINT32 PKU:1; |
| 1493 | /// |
| 1494 | /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the |
| 1495 | /// RDPKRU/WRPKRU instructions). |
| 1496 | /// |
| 1497 | UINT32 OSPKE:1; |
| 1498 | UINT32 Reserved5:9; |
| 1499 | /// |
| 1500 | /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.). |
| 1501 | /// |
| 1502 | UINT32 AVX512_VPOPCNTDQ:1; |
| 1503 | UINT32 Reserved7:1; |
| 1504 | /// |
| 1505 | /// [Bits 16] Supports 5-level paging if 1. |
| 1506 | /// |
| 1507 | UINT32 FiveLevelPage:1; |
| 1508 | /// |
| 1509 | /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions |
| 1510 | /// in 64-bit mode. |
| 1511 | /// |
| 1512 | UINT32 MAWAU:5; |
| 1513 | /// |
| 1514 | /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1. |
| 1515 | /// |
| 1516 | UINT32 RDPID:1; |
| 1517 | UINT32 Reserved3:7; |
| 1518 | /// |
| 1519 | /// [Bit 30] Supports SGX Launch Configuration if 1. |
| 1520 | /// |
| 1521 | UINT32 SGX_LC:1; |
| 1522 | UINT32 Reserved4:1; |
| 1523 | } Bits; |
| 1524 | /// |
| 1525 | /// All bit fields as a 32-bit value |
| 1526 | /// |
| 1527 | UINT32 Uint32; |
| 1528 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX; |
| 1529 | |
| 1530 | /** |
| 1531 | CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf |
| 1532 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf |
| 1533 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. |
| 1534 | **/ |
| 1535 | typedef union { |
| 1536 | /// |
| 1537 | /// Individual bit fields |
| 1538 | /// |
| 1539 | struct { |
| 1540 | /// |
| 1541 | /// [Bit 1:0] Reserved. |
| 1542 | /// |
| 1543 | UINT32 Reserved1:2; |
| 1544 | /// |
| 1545 | /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.) |
| 1546 | /// |
| 1547 | UINT32 AVX512_4VNNIW:1; |
| 1548 | /// |
| 1549 | /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.) |
| 1550 | /// |
| 1551 | UINT32 AVX512_4FMAPS:1; |
| 1552 | /// |
| 1553 | /// [Bit 14:4] Reserved. |
| 1554 | /// |
| 1555 | UINT32 Reserved4:11; |
| 1556 | /// |
| 1557 | /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part. |
| 1558 | /// |
| 1559 | UINT32 Hybrid:1; |
| 1560 | /// |
| 1561 | /// [Bit 25:16] Reserved. |
| 1562 | /// |
| 1563 | UINT32 Reserved5:10; |
| 1564 | /// |
| 1565 | /// [Bit 26] Enumerates support for indirect branch restricted speculation |
| 1566 | /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors |
| 1567 | /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD |
| 1568 | /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and |
| 1569 | /// IA32_PRED_CMD[0] (IBPB). |
| 1570 | /// |
| 1571 | UINT32 EnumeratesSupportForIBRSAndIBPB:1; |
| 1572 | /// |
| 1573 | /// [Bit 27] Enumerates support for single thread indirect branch |
| 1574 | /// predictors (STIBP). Processors that set this bit support the |
| 1575 | /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1] |
| 1576 | /// (STIBP). |
| 1577 | /// |
| 1578 | UINT32 EnumeratesSupportForSTIBP:1; |
| 1579 | /// |
| 1580 | /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit |
| 1581 | /// support the IA32_FLUSH_CMD MSR. They allow software to set |
| 1582 | /// IA32_FLUSH_CMD[0] (L1D_FLUSH). |
| 1583 | /// |
| 1584 | UINT32 EnumeratesSupportForL1D_FLUSH:1; |
| 1585 | /// |
| 1586 | /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR. |
| 1587 | /// |
| 1588 | UINT32 EnumeratesSupportForCapability:1; |
| 1589 | /// |
| 1590 | /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR. |
| 1591 | /// |
| 1592 | UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1; |
| 1593 | /// |
| 1594 | /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD). |
| 1595 | /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow |
| 1596 | /// software to set IA32_SPEC_CTRL[2] (SSBD). |
| 1597 | /// |
| 1598 | UINT32 EnumeratesSupportForSSBD:1; |
| 1599 | } Bits; |
| 1600 | /// |
| 1601 | /// All bit fields as a 32-bit value |
| 1602 | /// |
| 1603 | UINT32 Uint32; |
| 1604 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX; |
| 1605 | |
| 1606 | /** |
| 1607 | CPUID Direct Cache Access Information |
| 1608 | |
| 1609 | @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09) |
| 1610 | |
| 1611 | @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H). |
| 1612 | @retval EBX Reserved. |
| 1613 | @retval ECX Reserved. |
| 1614 | @retval EDX Reserved. |
| 1615 | |
| 1616 | <b>Example usage</b> |
| 1617 | @code |
| 1618 | UINT32 Eax; |
| 1619 | |
| 1620 | AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL); |
| 1621 | @endcode |
| 1622 | **/ |
| 1623 | #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09 |
| 1624 | |
| 1625 | |
| 1626 | /** |
| 1627 | CPUID Architectural Performance Monitoring |
| 1628 | |
| 1629 | @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A) |
| 1630 | |
| 1631 | @retval EAX Architectural Performance Monitoring information described by |
| 1632 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX. |
| 1633 | @retval EBX Architectural Performance Monitoring information described by |
| 1634 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX. |
| 1635 | @retval ECX Reserved. |
| 1636 | @retval EDX Architectural Performance Monitoring information described by |
| 1637 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX. |
| 1638 | |
| 1639 | <b>Example usage</b> |
| 1640 | @code |
| 1641 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax; |
| 1642 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx; |
| 1643 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx; |
| 1644 | |
| 1645 | AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32); |
| 1646 | @endcode |
| 1647 | **/ |
| 1648 | #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A |
| 1649 | |
| 1650 | /** |
| 1651 | CPUID Architectural Performance Monitoring EAX for CPUID leaf |
| 1652 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. |
| 1653 | **/ |
| 1654 | typedef union { |
| 1655 | /// |
| 1656 | /// Individual bit fields |
| 1657 | /// |
| 1658 | struct { |
| 1659 | /// |
| 1660 | /// [Bit 7:0] Version ID of architectural performance monitoring. |
| 1661 | /// |
| 1662 | UINT32 ArchPerfMonVerID:8; |
| 1663 | /// |
| 1664 | /// [Bits 15:8] Number of general-purpose performance monitoring counter |
| 1665 | /// per logical processor. |
| 1666 | /// |
| 1667 | /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous |
| 1668 | /// block of MSR address space. Each performance event select register is |
| 1669 | /// paired with a corresponding performance counter in the 0C1H address |
| 1670 | /// block. |
| 1671 | /// |
| 1672 | UINT32 PerformanceMonitorCounters:8; |
| 1673 | /// |
| 1674 | /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter. |
| 1675 | /// |
| 1676 | /// The bit width of an IA32_PMCx MSR. This the number of valid bits for |
| 1677 | /// read operation. On write operations, the lower-order 32 bits of the MSR |
| 1678 | /// may be written with any value, and the high-order bits are sign-extended |
| 1679 | /// from the value of bit 31. |
| 1680 | /// |
| 1681 | UINT32 PerformanceMonitorCounterWidth:8; |
| 1682 | /// |
| 1683 | /// [Bits 31:24] Length of EBX bit vector to enumerate architectural |
| 1684 | /// performance monitoring events. |
| 1685 | /// |
| 1686 | UINT32 EbxBitVectorLength:8; |
| 1687 | } Bits; |
| 1688 | /// |
| 1689 | /// All bit fields as a 32-bit value |
| 1690 | /// |
| 1691 | UINT32 Uint32; |
| 1692 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX; |
| 1693 | |
| 1694 | /** |
| 1695 | CPUID Architectural Performance Monitoring EBX for CPUID leaf |
| 1696 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. |
| 1697 | **/ |
| 1698 | typedef union { |
| 1699 | /// |
| 1700 | /// Individual bit fields |
| 1701 | /// |
| 1702 | struct { |
| 1703 | /// |
| 1704 | /// [Bit 0] Core cycle event not available if 1. |
| 1705 | /// |
| 1706 | UINT32 UnhaltedCoreCycles:1; |
| 1707 | /// |
| 1708 | /// [Bit 1] Instruction retired event not available if 1. |
| 1709 | /// |
| 1710 | UINT32 InstructionsRetired:1; |
| 1711 | /// |
| 1712 | /// [Bit 2] Reference cycles event not available if 1. |
| 1713 | /// |
| 1714 | UINT32 UnhaltedReferenceCycles:1; |
| 1715 | /// |
| 1716 | /// [Bit 3] Last-level cache reference event not available if 1. |
| 1717 | /// |
| 1718 | UINT32 LastLevelCacheReferences:1; |
| 1719 | /// |
| 1720 | /// [Bit 4] Last-level cache misses event not available if 1. |
| 1721 | /// |
| 1722 | UINT32 LastLevelCacheMisses:1; |
| 1723 | /// |
| 1724 | /// [Bit 5] Branch instruction retired event not available if 1. |
| 1725 | /// |
| 1726 | UINT32 BranchInstructionsRetired:1; |
| 1727 | /// |
| 1728 | /// [Bit 6] Branch mispredict retired event not available if 1. |
| 1729 | /// |
| 1730 | UINT32 AllBranchMispredictRetired:1; |
| 1731 | UINT32 Reserved:25; |
| 1732 | } Bits; |
| 1733 | /// |
| 1734 | /// All bit fields as a 32-bit value |
| 1735 | /// |
| 1736 | UINT32 Uint32; |
| 1737 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX; |
| 1738 | |
| 1739 | /** |
| 1740 | CPUID Architectural Performance Monitoring EDX for CPUID leaf |
| 1741 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. |
| 1742 | **/ |
| 1743 | typedef union { |
| 1744 | /// |
| 1745 | /// Individual bit fields |
| 1746 | /// |
| 1747 | struct { |
| 1748 | /// |
| 1749 | /// [Bits 4:0] Number of fixed-function performance counters |
| 1750 | /// (if Version ID > 1). |
| 1751 | /// |
| 1752 | UINT32 FixedFunctionPerformanceCounters:5; |
| 1753 | /// |
| 1754 | /// [Bits 12:5] Bit width of fixed-function performance counters |
| 1755 | /// (if Version ID > 1). |
| 1756 | /// |
| 1757 | UINT32 FixedFunctionPerformanceCounterWidth:8; |
| 1758 | UINT32 Reserved1:2; |
| 1759 | /// |
| 1760 | /// [Bits 15] AnyThread deprecation. |
| 1761 | /// |
| 1762 | UINT32 AnyThreadDeprecation:1; |
| 1763 | UINT32 Reserved2:16; |
| 1764 | } Bits; |
| 1765 | /// |
| 1766 | /// All bit fields as a 32-bit value |
| 1767 | /// |
| 1768 | UINT32 Uint32; |
| 1769 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX; |
| 1770 | |
| 1771 | |
| 1772 | /** |
| 1773 | CPUID Extended Topology Information |
| 1774 | |
| 1775 | @note |
| 1776 | CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first |
| 1777 | checking for the existence of Leaf 1FH before using leaf 0BH. |
| 1778 | Most of Leaf 0BH output depends on the initial value in ECX. The EDX output |
| 1779 | of leaf 0BH is always valid and does not vary with input value in ECX. Output |
| 1780 | value in ECX[7:0] always equals input value in ECX[7:0]. |
| 1781 | Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index |
| 1782 | enumerates a higher-level topological entity in hierarchical order. |
| 1783 | For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and |
| 1784 | EBX will return 0. |
| 1785 | If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], |
| 1786 | other input values with ECX > n also return 0 in ECX[15:8]. |
| 1787 | |
| 1788 | @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B) |
| 1789 | @param ECX Level number |
| 1790 | |
| 1791 | @retval EAX Extended topology information described by the type |
| 1792 | CPUID_EXTENDED_TOPOLOGY_EAX. |
| 1793 | @retval EBX Extended topology information described by the type |
| 1794 | CPUID_EXTENDED_TOPOLOGY_EBX. |
| 1795 | @retval ECX Extended topology information described by the type |
| 1796 | CPUID_EXTENDED_TOPOLOGY_ECX. |
| 1797 | @retval EDX x2APIC ID the current logical processor. |
| 1798 | |
| 1799 | <b>Example usage</b> |
| 1800 | @code |
| 1801 | CPUID_EXTENDED_TOPOLOGY_EAX Eax; |
| 1802 | CPUID_EXTENDED_TOPOLOGY_EBX Ebx; |
| 1803 | CPUID_EXTENDED_TOPOLOGY_ECX Ecx; |
| 1804 | UINT32 Edx; |
| 1805 | UINT32 LevelNumber; |
| 1806 | |
| 1807 | LevelNumber = 0; |
| 1808 | do { |
| 1809 | AsmCpuidEx ( |
| 1810 | CPUID_EXTENDED_TOPOLOGY, LevelNumber, |
| 1811 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx |
| 1812 | ); |
| 1813 | LevelNumber++; |
| 1814 | } while (Eax.Bits.ApicIdShift != 0); |
| 1815 | @endcode |
| 1816 | **/ |
| 1817 | #define CPUID_EXTENDED_TOPOLOGY 0x0B |
| 1818 | |
| 1819 | /** |
| 1820 | CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. |
| 1821 | **/ |
| 1822 | typedef union { |
| 1823 | /// |
| 1824 | /// Individual bit fields |
| 1825 | /// |
| 1826 | struct { |
| 1827 | /// |
| 1828 | /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique |
| 1829 | /// topology ID of the next level type. All logical processors with the |
| 1830 | /// same next level ID share current level. |
| 1831 | /// |
| 1832 | /// @note |
| 1833 | /// Software should use this field (EAX[4:0]) to enumerate processor |
| 1834 | /// topology of the system. |
| 1835 | /// |
| 1836 | UINT32 ApicIdShift:5; |
| 1837 | UINT32 Reserved:27; |
| 1838 | } Bits; |
| 1839 | /// |
| 1840 | /// All bit fields as a 32-bit value |
| 1841 | /// |
| 1842 | UINT32 Uint32; |
| 1843 | } CPUID_EXTENDED_TOPOLOGY_EAX; |
| 1844 | |
| 1845 | /** |
| 1846 | CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. |
| 1847 | **/ |
| 1848 | typedef union { |
| 1849 | /// |
| 1850 | /// Individual bit fields |
| 1851 | /// |
| 1852 | struct { |
| 1853 | /// |
| 1854 | /// [Bits 15:0] Number of logical processors at this level type. The number |
| 1855 | /// reflects configuration as shipped by Intel. |
| 1856 | /// |
| 1857 | /// @note |
| 1858 | /// Software must not use EBX[15:0] to enumerate processor topology of the |
| 1859 | /// system. This value in this field (EBX[15:0]) is only intended for |
| 1860 | /// display/diagnostic purposes. The actual number of logical processors |
| 1861 | /// available to BIOS/OS/Applications may be different from the value of |
| 1862 | /// EBX[15:0], depending on software and platform hardware configurations. |
| 1863 | /// |
| 1864 | UINT32 LogicalProcessors:16; |
| 1865 | UINT32 Reserved:16; |
| 1866 | } Bits; |
| 1867 | /// |
| 1868 | /// All bit fields as a 32-bit value |
| 1869 | /// |
| 1870 | UINT32 Uint32; |
| 1871 | } CPUID_EXTENDED_TOPOLOGY_EBX; |
| 1872 | |
| 1873 | /** |
| 1874 | CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. |
| 1875 | **/ |
| 1876 | typedef union { |
| 1877 | /// |
| 1878 | /// Individual bit fields |
| 1879 | /// |
| 1880 | struct { |
| 1881 | /// |
| 1882 | /// [Bits 7:0] Level number. Same value in ECX input. |
| 1883 | /// |
| 1884 | UINT32 LevelNumber:8; |
| 1885 | /// |
| 1886 | /// [Bits 15:8] Level type. |
| 1887 | /// |
| 1888 | /// @note |
| 1889 | /// The value of the "level type" field is not related to level numbers in |
| 1890 | /// any way, higher "level type" values do not mean higher levels. |
| 1891 | /// |
| 1892 | UINT32 LevelType:8; |
| 1893 | UINT32 Reserved:16; |
| 1894 | } Bits; |
| 1895 | /// |
| 1896 | /// All bit fields as a 32-bit value |
| 1897 | /// |
| 1898 | UINT32 Uint32; |
| 1899 | } CPUID_EXTENDED_TOPOLOGY_ECX; |
| 1900 | |
| 1901 | /// |
| 1902 | /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType |
| 1903 | /// |
| 1904 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00 |
| 1905 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01 |
| 1906 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02 |
| 1907 | /// |
| 1908 | /// @} |
| 1909 | /// |
| 1910 | |
| 1911 | |
| 1912 | /** |
| 1913 | CPUID Extended State Information |
| 1914 | |
| 1915 | @param EAX CPUID_EXTENDED_STATE (0x0D) |
| 1916 | @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00). |
| 1917 | CPUID_EXTENDED_STATE_SUB_LEAF (0x01). |
| 1918 | CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). |
| 1919 | Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR. |
| 1920 | **/ |
| 1921 | #define CPUID_EXTENDED_STATE 0x0D |
| 1922 | |
| 1923 | /** |
| 1924 | CPUID Extended State Information Main Leaf |
| 1925 | |
| 1926 | @param EAX CPUID_EXTENDED_STATE (0x0D) |
| 1927 | @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00) |
| 1928 | |
| 1929 | @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] |
| 1930 | can be set to 1 only if EAX[n] is 1. The format of the extended |
| 1931 | state main leaf is described by the type |
| 1932 | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX. |
| 1933 | @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save |
| 1934 | area) required by enabled features in XCR0. May be different than |
| 1935 | ECX if some features at the end of the XSAVE save area are not |
| 1936 | enabled. |
| 1937 | @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save |
| 1938 | area) of the XSAVE/XRSTOR save area required by all supported |
| 1939 | features in the processor, i.e., all the valid bit fields in XCR0. |
| 1940 | @retval EDX Reports the supported bits of the upper 32 bits of XCR0. |
| 1941 | XCR0[n+32] can be set to 1 only if EDX[n] is 1. |
| 1942 | |
| 1943 | <b>Example usage</b> |
| 1944 | @code |
| 1945 | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax; |
| 1946 | UINT32 Ebx; |
| 1947 | UINT32 Ecx; |
| 1948 | UINT32 Edx; |
| 1949 | |
| 1950 | AsmCpuidEx ( |
| 1951 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF, |
| 1952 | &Eax.Uint32, &Ebx, &Ecx, &Edx |
| 1953 | ); |
| 1954 | @endcode |
| 1955 | **/ |
| 1956 | #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00 |
| 1957 | |
| 1958 | /** |
| 1959 | CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, |
| 1960 | sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF. |
| 1961 | **/ |
| 1962 | typedef union { |
| 1963 | /// |
| 1964 | /// Individual bit fields |
| 1965 | /// |
| 1966 | struct { |
| 1967 | /// |
| 1968 | /// [Bit 0] x87 state. |
| 1969 | /// |
| 1970 | UINT32 x87:1; |
| 1971 | /// |
| 1972 | /// [Bit 1] SSE state. |
| 1973 | /// |
| 1974 | UINT32 SSE:1; |
| 1975 | /// |
| 1976 | /// [Bit 2] AVX state. |
| 1977 | /// |
| 1978 | UINT32 AVX:1; |
| 1979 | /// |
| 1980 | /// [Bits 4:3] MPX state. |
| 1981 | /// |
| 1982 | UINT32 MPX:2; |
| 1983 | /// |
| 1984 | /// [Bits 7:5] AVX-512 state. |
| 1985 | /// |
| 1986 | UINT32 AVX_512:3; |
| 1987 | /// |
| 1988 | /// [Bit 8] Used for IA32_XSS. |
| 1989 | /// |
| 1990 | UINT32 IA32_XSS:1; |
| 1991 | /// |
| 1992 | /// [Bit 9] PKRU state. |
| 1993 | /// |
| 1994 | UINT32 PKRU:1; |
| 1995 | UINT32 Reserved1:3; |
| 1996 | /// |
| 1997 | /// [Bit 13] Used for IA32_XSS, part 2. |
| 1998 | /// |
| 1999 | UINT32 IA32_XSS_2:1; |
| 2000 | UINT32 Reserved2:18; |
| 2001 | } Bits; |
| 2002 | /// |
| 2003 | /// All bit fields as a 32-bit value |
| 2004 | /// |
| 2005 | UINT32 Uint32; |
| 2006 | } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX; |
| 2007 | |
| 2008 | /** |
| 2009 | CPUID Extended State Information Sub Leaf |
| 2010 | |
| 2011 | @param EAX CPUID_EXTENDED_STATE (0x0D) |
| 2012 | @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01) |
| 2013 | |
| 2014 | @retval EAX The format of the extended state sub-leaf is described by the |
| 2015 | type CPUID_EXTENDED_STATE_SUB_LEAF_EAX. |
| 2016 | @retval EBX The size in bytes of the XSAVE area containing all states |
| 2017 | enabled by XCRO | IA32_XSS. |
| 2018 | @retval ECX The format of the extended state sub-leaf is described by the |
| 2019 | type CPUID_EXTENDED_STATE_SUB_LEAF_ECX. |
| 2020 | @retval EDX Reports the supported bits of the upper 32 bits of the |
| 2021 | IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1. |
| 2022 | |
| 2023 | <b>Example usage</b> |
| 2024 | @code |
| 2025 | CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax; |
| 2026 | UINT32 Ebx; |
| 2027 | CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx; |
| 2028 | UINT32 Edx; |
| 2029 | |
| 2030 | AsmCpuidEx ( |
| 2031 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, |
| 2032 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx |
| 2033 | ); |
| 2034 | @endcode |
| 2035 | **/ |
| 2036 | #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01 |
| 2037 | |
| 2038 | /** |
| 2039 | CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, |
| 2040 | sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. |
| 2041 | **/ |
| 2042 | typedef union { |
| 2043 | /// |
| 2044 | /// Individual bit fields |
| 2045 | /// |
| 2046 | struct { |
| 2047 | /// |
| 2048 | /// [Bit 0] XSAVEOPT is available. |
| 2049 | /// |
| 2050 | UINT32 XSAVEOPT:1; |
| 2051 | /// |
| 2052 | /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set. |
| 2053 | /// |
| 2054 | UINT32 XSAVEC:1; |
| 2055 | /// |
| 2056 | /// [Bit 2] Supports XGETBV with ECX = 1 if set. |
| 2057 | /// |
| 2058 | UINT32 XGETBV:1; |
| 2059 | /// |
| 2060 | /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set. |
| 2061 | /// |
| 2062 | UINT32 XSAVES:1; |
| 2063 | UINT32 Reserved:28; |
| 2064 | } Bits; |
| 2065 | /// |
| 2066 | /// All bit fields as a 32-bit value |
| 2067 | /// |
| 2068 | UINT32 Uint32; |
| 2069 | } CPUID_EXTENDED_STATE_SUB_LEAF_EAX; |
| 2070 | |
| 2071 | /** |
| 2072 | CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, |
| 2073 | sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. |
| 2074 | **/ |
| 2075 | typedef union { |
| 2076 | /// |
| 2077 | /// Individual bit fields |
| 2078 | /// |
| 2079 | struct { |
| 2080 | /// |
| 2081 | /// [Bits 7:0] Used for XCR0. |
| 2082 | /// |
| 2083 | UINT32 XCR0:1; |
| 2084 | /// |
| 2085 | /// [Bit 8] PT STate. |
| 2086 | /// |
| 2087 | UINT32 PT:1; |
| 2088 | /// |
| 2089 | /// [Bit 9] Used for XCR0. |
| 2090 | /// |
| 2091 | UINT32 XCR0_1:1; |
| 2092 | UINT32 Reserved1:3; |
| 2093 | /// |
| 2094 | /// [Bit 13] HWP state. |
| 2095 | /// |
| 2096 | UINT32 HWPState:1; |
| 2097 | UINT32 Reserved8:18; |
| 2098 | } Bits; |
| 2099 | /// |
| 2100 | /// All bit fields as a 32-bit value |
| 2101 | /// |
| 2102 | UINT32 Uint32; |
| 2103 | } CPUID_EXTENDED_STATE_SUB_LEAF_ECX; |
| 2104 | |
| 2105 | /** |
| 2106 | CPUID Extended State Information Size and Offset Sub Leaf |
| 2107 | |
| 2108 | @note |
| 2109 | Leaf 0DH output depends on the initial value in ECX. |
| 2110 | Each sub-leaf index (starting at position 2) is supported if it corresponds to |
| 2111 | a supported bit in either the XCR0 register or the IA32_XSS MSR. |
| 2112 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf |
| 2113 | n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 |
| 2114 | returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0 |
| 2115 | returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32]. |
| 2116 | |
| 2117 | @param EAX CPUID_EXTENDED_STATE (0x0D) |
| 2118 | @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based |
| 2119 | on supported bits in XCR0 or IA32_XSS_MSR. |
| 2120 | |
| 2121 | @retval EAX The size in bytes (from the offset specified in EBX) of the save |
| 2122 | area for an extended state feature associated with a valid |
| 2123 | sub-leaf index, n. |
| 2124 | @retval EBX The offset in bytes of this extended state component's save area |
| 2125 | from the beginning of the XSAVE/XRSTOR area. This field reports |
| 2126 | 0 if the sub-leaf index, n, does not map to a valid bit in the |
| 2127 | XCR0 register. |
| 2128 | @retval ECX The format of the extended state components's save area as |
| 2129 | described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX. |
| 2130 | This field reports 0 if the sub-leaf index, n, is invalid. |
| 2131 | @retval EDX This field reports 0 if the sub-leaf index, n, is invalid; |
| 2132 | otherwise it is reserved. |
| 2133 | |
| 2134 | <b>Example usage</b> |
| 2135 | @code |
| 2136 | UINT32 Eax; |
| 2137 | UINT32 Ebx; |
| 2138 | CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx; |
| 2139 | UINT32 Edx; |
| 2140 | UINTN SubLeaf; |
| 2141 | |
| 2142 | for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) { |
| 2143 | AsmCpuidEx ( |
| 2144 | CPUID_EXTENDED_STATE, SubLeaf, |
| 2145 | &Eax, &Ebx, &Ecx.Uint32, &Edx |
| 2146 | ); |
| 2147 | } |
| 2148 | @endcode |
| 2149 | **/ |
| 2150 | #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02 |
| 2151 | |
| 2152 | /** |
| 2153 | CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, |
| 2154 | sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET. |
| 2155 | **/ |
| 2156 | typedef union { |
| 2157 | /// |
| 2158 | /// Individual bit fields |
| 2159 | /// |
| 2160 | struct { |
| 2161 | /// |
| 2162 | /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is |
| 2163 | /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported |
| 2164 | /// in XCR0. |
| 2165 | /// |
| 2166 | UINT32 XSS:1; |
| 2167 | /// |
| 2168 | /// [Bit 1] is set if, when the compacted format of an XSAVE area is used, |
| 2169 | /// this extended state component located on the next 64-byte boundary |
| 2170 | /// following the preceding state component (otherwise, it is located |
| 2171 | /// immediately following the preceding state component). |
| 2172 | /// |
| 2173 | UINT32 Compacted:1; |
| 2174 | UINT32 Reserved:30; |
| 2175 | } Bits; |
| 2176 | /// |
| 2177 | /// All bit fields as a 32-bit value |
| 2178 | /// |
| 2179 | UINT32 Uint32; |
| 2180 | } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX; |
| 2181 | |
| 2182 | |
| 2183 | /** |
| 2184 | CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information |
| 2185 | |
| 2186 | @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) |
| 2187 | @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00). |
| 2188 | CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01). |
| 2189 | |
| 2190 | **/ |
| 2191 | #define CPUID_INTEL_RDT_MONITORING 0x0F |
| 2192 | |
| 2193 | /** |
| 2194 | CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information |
| 2195 | Enumeration Sub-leaf |
| 2196 | |
| 2197 | @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) |
| 2198 | @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00) |
| 2199 | |
| 2200 | @retval EAX Reserved. |
| 2201 | @retval EBX Maximum range (zero-based) of RMID within this physical |
| 2202 | processor of all types. |
| 2203 | @retval ECX Reserved. |
| 2204 | @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by |
| 2205 | the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX. |
| 2206 | |
| 2207 | <b>Example usage</b> |
| 2208 | @code |
| 2209 | UINT32 Ebx; |
| 2210 | CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; |
| 2211 | |
| 2212 | AsmCpuidEx ( |
| 2213 | CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, |
| 2214 | NULL, &Ebx, NULL, &Edx.Uint32 |
| 2215 | ); |
| 2216 | @endcode |
| 2217 | **/ |
| 2218 | #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00 |
| 2219 | |
| 2220 | /** |
| 2221 | CPUID Intel RDT Monitoring Information EDX for CPUID leaf |
| 2222 | #CPUID_INTEL_RDT_MONITORING, sub-leaf |
| 2223 | #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF. |
| 2224 | **/ |
| 2225 | typedef union { |
| 2226 | /// |
| 2227 | /// Individual bit fields |
| 2228 | /// |
| 2229 | struct { |
| 2230 | UINT32 Reserved1:1; |
| 2231 | /// |
| 2232 | /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1. |
| 2233 | /// |
| 2234 | UINT32 L3CacheRDT_M:1; |
| 2235 | UINT32 Reserved2:30; |
| 2236 | } Bits; |
| 2237 | /// |
| 2238 | /// All bit fields as a 32-bit value |
| 2239 | /// |
| 2240 | UINT32 Uint32; |
| 2241 | } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX; |
| 2242 | |
| 2243 | /** |
| 2244 | CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf |
| 2245 | |
| 2246 | @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) |
| 2247 | @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01) |
| 2248 | |
| 2249 | @retval EAX Reserved. |
| 2250 | @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes). |
| 2251 | @retval ECX Maximum range (zero-based) of RMID of this resource type. |
| 2252 | @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the |
| 2253 | type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX. |
| 2254 | |
| 2255 | <b>Example usage</b> |
| 2256 | @code |
| 2257 | UINT32 Ebx; |
| 2258 | UINT32 Ecx; |
| 2259 | CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; |
| 2260 | |
| 2261 | AsmCpuidEx ( |
| 2262 | CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, |
| 2263 | NULL, &Ebx, &Ecx, &Edx.Uint32 |
| 2264 | ); |
| 2265 | @endcode |
| 2266 | **/ |
| 2267 | #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01 |
| 2268 | |
| 2269 | /** |
| 2270 | CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf |
| 2271 | #CPUID_INTEL_RDT_MONITORING, sub-leaf |
| 2272 | #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF. |
| 2273 | **/ |
| 2274 | typedef union { |
| 2275 | /// |
| 2276 | /// Individual bit fields |
| 2277 | /// |
| 2278 | struct { |
| 2279 | /// |
| 2280 | /// [Bit 0] Supports L3 occupancy monitoring if 1. |
| 2281 | /// |
| 2282 | UINT32 L3CacheOccupancyMonitoring:1; |
| 2283 | /// |
| 2284 | /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1. |
| 2285 | /// |
| 2286 | UINT32 L3CacheTotalBandwidthMonitoring:1; |
| 2287 | /// |
| 2288 | /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1. |
| 2289 | /// |
| 2290 | UINT32 L3CacheLocalBandwidthMonitoring:1; |
| 2291 | UINT32 Reserved:29; |
| 2292 | } Bits; |
| 2293 | /// |
| 2294 | /// All bit fields as a 32-bit value |
| 2295 | /// |
| 2296 | UINT32 Uint32; |
| 2297 | } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX; |
| 2298 | |
| 2299 | |
| 2300 | /** |
| 2301 | CPUID Intel Resource Director Technology (Intel RDT) Allocation Information |
| 2302 | |
| 2303 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10). |
| 2304 | @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). |
| 2305 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01). |
| 2306 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02). |
| 2307 | **/ |
| 2308 | #define CPUID_INTEL_RDT_ALLOCATION 0x10 |
| 2309 | |
| 2310 | /** |
| 2311 | Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf |
| 2312 | |
| 2313 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) |
| 2314 | @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). |
| 2315 | |
| 2316 | @retval EAX Reserved. |
| 2317 | @retval EBX L3 and L2 Cache Allocation Technology information described by |
| 2318 | the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX. |
| 2319 | @retval ECX Reserved. |
| 2320 | @retval EDX Reserved. |
| 2321 | |
| 2322 | <b>Example usage</b> |
| 2323 | @code |
| 2324 | CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx; |
| 2325 | |
| 2326 | AsmCpuidEx ( |
| 2327 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, |
| 2328 | NULL, &Ebx.Uint32, NULL, NULL |
| 2329 | ); |
| 2330 | @endcode |
| 2331 | **/ |
| 2332 | #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00 |
| 2333 | |
| 2334 | /** |
| 2335 | CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf |
| 2336 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2337 | #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF. |
| 2338 | **/ |
| 2339 | typedef union { |
| 2340 | /// |
| 2341 | /// Individual bit fields |
| 2342 | /// |
| 2343 | struct { |
| 2344 | UINT32 Reserved1:1; |
| 2345 | /// |
| 2346 | /// [Bit 1] Supports L3 Cache Allocation Technology if 1. |
| 2347 | /// |
| 2348 | UINT32 L3CacheAllocation:1; |
| 2349 | /// |
| 2350 | /// [Bit 2] Supports L2 Cache Allocation Technology if 1. |
| 2351 | /// |
| 2352 | UINT32 L2CacheAllocation:1; |
| 2353 | /// |
| 2354 | /// [Bit 3] Supports Memory Bandwidth Allocation if 1. |
| 2355 | /// |
| 2356 | UINT32 MemoryBandwidth:1; |
| 2357 | UINT32 Reserved3:28; |
| 2358 | } Bits; |
| 2359 | /// |
| 2360 | /// All bit fields as a 32-bit value |
| 2361 | /// |
| 2362 | UINT32 Uint32; |
| 2363 | } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX; |
| 2364 | |
| 2365 | |
| 2366 | /** |
| 2367 | L3 Cache Allocation Technology Enumeration Sub-leaf |
| 2368 | |
| 2369 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) |
| 2370 | @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01) |
| 2371 | |
| 2372 | @retval EAX RESID L3 Cache Allocation Technology information described by |
| 2373 | the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX. |
| 2374 | @retval EBX Bit-granular map of isolation/contention of allocation units. |
| 2375 | @retval ECX RESID L3 Cache Allocation Technology information described by |
| 2376 | the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX. |
| 2377 | @retval EDX RESID L3 Cache Allocation Technology information described by |
| 2378 | the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX. |
| 2379 | |
| 2380 | <b>Example usage</b> |
| 2381 | @code |
| 2382 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax; |
| 2383 | UINT32 Ebx; |
| 2384 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx; |
| 2385 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; |
| 2386 | |
| 2387 | AsmCpuidEx ( |
| 2388 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, |
| 2389 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 |
| 2390 | ); |
| 2391 | @endcode |
| 2392 | **/ |
| 2393 | #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 |
| 2394 | |
| 2395 | /** |
| 2396 | CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf |
| 2397 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2398 | #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. |
| 2399 | **/ |
| 2400 | typedef union { |
| 2401 | /// |
| 2402 | /// Individual bit fields |
| 2403 | /// |
| 2404 | struct { |
| 2405 | /// |
| 2406 | /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID |
| 2407 | /// using minus-one notation. |
| 2408 | /// |
| 2409 | UINT32 CapacityLength:5; |
| 2410 | UINT32 Reserved:27; |
| 2411 | } Bits; |
| 2412 | /// |
| 2413 | /// All bit fields as a 32-bit value |
| 2414 | /// |
| 2415 | UINT32 Uint32; |
| 2416 | } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX; |
| 2417 | |
| 2418 | /** |
| 2419 | CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf |
| 2420 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2421 | #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. |
| 2422 | **/ |
| 2423 | typedef union { |
| 2424 | /// |
| 2425 | /// Individual bit fields |
| 2426 | /// |
| 2427 | struct { |
| 2428 | UINT32 Reserved3:2; |
| 2429 | /// |
| 2430 | /// [Bit 2] Code and Data Prioritization Technology supported if 1. |
| 2431 | /// |
| 2432 | UINT32 CodeDataPrioritization:1; |
| 2433 | UINT32 Reserved2:29; |
| 2434 | } Bits; |
| 2435 | /// |
| 2436 | /// All bit fields as a 32-bit value |
| 2437 | /// |
| 2438 | UINT32 Uint32; |
| 2439 | } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX; |
| 2440 | |
| 2441 | /** |
| 2442 | CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf |
| 2443 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2444 | #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. |
| 2445 | **/ |
| 2446 | typedef union { |
| 2447 | /// |
| 2448 | /// Individual bit fields |
| 2449 | /// |
| 2450 | struct { |
| 2451 | /// |
| 2452 | /// [Bits 15:0] Highest COS number supported for this ResID. |
| 2453 | /// |
| 2454 | UINT32 HighestCosNumber:16; |
| 2455 | UINT32 Reserved:16; |
| 2456 | } Bits; |
| 2457 | /// |
| 2458 | /// All bit fields as a 32-bit value |
| 2459 | /// |
| 2460 | UINT32 Uint32; |
| 2461 | } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX; |
| 2462 | |
| 2463 | /** |
| 2464 | L2 Cache Allocation Technology Enumeration Sub-leaf |
| 2465 | |
| 2466 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) |
| 2467 | @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02) |
| 2468 | |
| 2469 | @retval EAX RESID L2 Cache Allocation Technology information described by |
| 2470 | the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX. |
| 2471 | @retval EBX Bit-granular map of isolation/contention of allocation units. |
| 2472 | @retval ECX Reserved. |
| 2473 | @retval EDX RESID L2 Cache Allocation Technology information described by |
| 2474 | the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX. |
| 2475 | |
| 2476 | <b>Example usage</b> |
| 2477 | @code |
| 2478 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax; |
| 2479 | UINT32 Ebx; |
| 2480 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; |
| 2481 | |
| 2482 | AsmCpuidEx ( |
| 2483 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, |
| 2484 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 |
| 2485 | ); |
| 2486 | @endcode |
| 2487 | **/ |
| 2488 | #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02 |
| 2489 | |
| 2490 | /** |
| 2491 | CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf |
| 2492 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2493 | #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. |
| 2494 | **/ |
| 2495 | typedef union { |
| 2496 | /// |
| 2497 | /// Individual bit fields |
| 2498 | /// |
| 2499 | struct { |
| 2500 | /// |
| 2501 | /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID |
| 2502 | /// using minus-one notation. |
| 2503 | /// |
| 2504 | UINT32 CapacityLength:5; |
| 2505 | UINT32 Reserved:27; |
| 2506 | } Bits; |
| 2507 | /// |
| 2508 | /// All bit fields as a 32-bit value |
| 2509 | /// |
| 2510 | UINT32 Uint32; |
| 2511 | } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX; |
| 2512 | |
| 2513 | /** |
| 2514 | CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf |
| 2515 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2516 | #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. |
| 2517 | **/ |
| 2518 | typedef union { |
| 2519 | /// |
| 2520 | /// Individual bit fields |
| 2521 | /// |
| 2522 | struct { |
| 2523 | /// |
| 2524 | /// [Bits 15:0] Highest COS number supported for this ResID. |
| 2525 | /// |
| 2526 | UINT32 HighestCosNumber:16; |
| 2527 | UINT32 Reserved:16; |
| 2528 | } Bits; |
| 2529 | /// |
| 2530 | /// All bit fields as a 32-bit value |
| 2531 | /// |
| 2532 | UINT32 Uint32; |
| 2533 | } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX; |
| 2534 | |
| 2535 | /** |
| 2536 | Memory Bandwidth Allocation Enumeration Sub-leaf |
| 2537 | |
| 2538 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) |
| 2539 | @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03) |
| 2540 | |
| 2541 | @retval EAX RESID memory bandwidth Allocation Technology information |
| 2542 | described by the type |
| 2543 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX. |
| 2544 | @retval EBX Reserved. |
| 2545 | @retval ECX RESID memory bandwidth Allocation Technology information |
| 2546 | described by the type |
| 2547 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX. |
| 2548 | @retval EDX RESID memory bandwidth Allocation Technology information |
| 2549 | described by the type |
| 2550 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX. |
| 2551 | |
| 2552 | <b>Example usage</b> |
| 2553 | @code |
| 2554 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax; |
| 2555 | UINT32 Ebx; |
| 2556 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx; |
| 2557 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx; |
| 2558 | |
| 2559 | |
| 2560 | AsmCpuidEx ( |
| 2561 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, |
| 2562 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 |
| 2563 | ); |
| 2564 | @endcode |
| 2565 | **/ |
| 2566 | #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03 |
| 2567 | |
| 2568 | /** |
| 2569 | CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf |
| 2570 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2571 | #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. |
| 2572 | **/ |
| 2573 | typedef union { |
| 2574 | /// |
| 2575 | /// Individual bit fields |
| 2576 | /// |
| 2577 | struct { |
| 2578 | /// |
| 2579 | /// [Bits 11:0] Reports the maximum MBA throttling value supported for |
| 2580 | /// the corresponding ResID using minus-one notation. |
| 2581 | /// |
| 2582 | UINT32 MaximumMBAThrottling:12; |
| 2583 | UINT32 Reserved:20; |
| 2584 | } Bits; |
| 2585 | /// |
| 2586 | /// All bit fields as a 32-bit value |
| 2587 | /// |
| 2588 | UINT32 Uint32; |
| 2589 | } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX; |
| 2590 | |
| 2591 | /** |
| 2592 | CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf |
| 2593 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2594 | #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. |
| 2595 | **/ |
| 2596 | typedef union { |
| 2597 | /// |
| 2598 | /// Individual bit fields |
| 2599 | /// |
| 2600 | struct { |
| 2601 | /// |
| 2602 | /// [Bits 1:0] Reserved. |
| 2603 | /// |
| 2604 | UINT32 Reserved1:2; |
| 2605 | /// |
| 2606 | /// [Bits 3] Reports whether the response of the delay values is linear. |
| 2607 | /// |
| 2608 | UINT32 Liner:1; |
| 2609 | UINT32 Reserved2:29; |
| 2610 | } Bits; |
| 2611 | /// |
| 2612 | /// All bit fields as a 32-bit value |
| 2613 | /// |
| 2614 | UINT32 Uint32; |
| 2615 | } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX; |
| 2616 | |
| 2617 | /** |
| 2618 | CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf |
| 2619 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf |
| 2620 | #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. |
| 2621 | **/ |
| 2622 | typedef union { |
| 2623 | /// |
| 2624 | /// Individual bit fields |
| 2625 | /// |
| 2626 | struct { |
| 2627 | /// |
| 2628 | /// [Bits 15:0] Highest COS number supported for this ResID. |
| 2629 | /// |
| 2630 | UINT32 HighestCosNumber:16; |
| 2631 | UINT32 Reserved:16; |
| 2632 | } Bits; |
| 2633 | /// |
| 2634 | /// All bit fields as a 32-bit value |
| 2635 | /// |
| 2636 | UINT32 Uint32; |
| 2637 | } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX; |
| 2638 | |
| 2639 | /** |
| 2640 | Intel SGX resource capability and configuration. |
| 2641 | See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves". |
| 2642 | |
| 2643 | If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying |
| 2644 | CPUID with EAX=12H on Intel SGX resource capability and configuration. |
| 2645 | |
| 2646 | @param EAX CPUID_INTEL_SGX (0x12) |
| 2647 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00). |
| 2648 | CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01). |
| 2649 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02). |
| 2650 | Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0]) |
| 2651 | until the sub-leaf type is invalid. |
| 2652 | |
| 2653 | **/ |
| 2654 | #define CPUID_INTEL_SGX 0x12 |
| 2655 | |
| 2656 | /** |
| 2657 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities. |
| 2658 | Enumerates Intel SGX capability, including enclave instruction opcode support. |
| 2659 | |
| 2660 | @param EAX CPUID_INTEL_SGX (0x12) |
| 2661 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00) |
| 2662 | |
| 2663 | @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is |
| 2664 | described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX. |
| 2665 | @retval EBX MISCSELECT: Reports the bit vector of supported extended features |
| 2666 | that can be written to the MISC region of the SSA. |
| 2667 | @retval ECX Reserved. |
| 2668 | @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is |
| 2669 | described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX. |
| 2670 | |
| 2671 | <b>Example usage</b> |
| 2672 | @code |
| 2673 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax; |
| 2674 | UINT32 Ebx; |
| 2675 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx; |
| 2676 | |
| 2677 | AsmCpuidEx ( |
| 2678 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, |
| 2679 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 |
| 2680 | ); |
| 2681 | @endcode |
| 2682 | **/ |
| 2683 | #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00 |
| 2684 | |
| 2685 | /** |
| 2686 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX, |
| 2687 | sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. |
| 2688 | **/ |
| 2689 | typedef union { |
| 2690 | /// |
| 2691 | /// Individual bit fields |
| 2692 | /// |
| 2693 | struct { |
| 2694 | /// |
| 2695 | /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported. |
| 2696 | /// |
| 2697 | UINT32 SGX1:1; |
| 2698 | /// |
| 2699 | /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported. |
| 2700 | /// |
| 2701 | UINT32 SGX2:1; |
| 2702 | UINT32 Reserved1:3; |
| 2703 | /// |
| 2704 | /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves |
| 2705 | /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT. |
| 2706 | /// |
| 2707 | UINT32 ENCLV:1; |
| 2708 | /// |
| 2709 | /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC, |
| 2710 | /// ERDINFO, ELDBC, and ELDUC. |
| 2711 | /// |
| 2712 | UINT32 ENCLS:1; |
| 2713 | UINT32 Reserved2:25; |
| 2714 | } Bits; |
| 2715 | /// |
| 2716 | /// All bit fields as a 32-bit value |
| 2717 | /// |
| 2718 | UINT32 Uint32; |
| 2719 | } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX; |
| 2720 | |
| 2721 | /** |
| 2722 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX, |
| 2723 | sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. |
| 2724 | **/ |
| 2725 | typedef union { |
| 2726 | /// |
| 2727 | /// Individual bit fields |
| 2728 | /// |
| 2729 | struct { |
| 2730 | /// |
| 2731 | /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes |
| 2732 | /// when not in 64-bit mode. |
| 2733 | /// |
| 2734 | UINT32 MaxEnclaveSize_Not64:8; |
| 2735 | /// |
| 2736 | /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes |
| 2737 | /// when operating in 64-bit mode. |
| 2738 | /// |
| 2739 | UINT32 MaxEnclaveSize_64:8; |
| 2740 | UINT32 Reserved:16; |
| 2741 | } Bits; |
| 2742 | /// |
| 2743 | /// All bit fields as a 32-bit value |
| 2744 | /// |
| 2745 | UINT32 Uint32; |
| 2746 | } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX; |
| 2747 | |
| 2748 | |
| 2749 | /** |
| 2750 | Sub-Leaf 1 Enumeration of Intel SGX Capabilities. |
| 2751 | Enumerates Intel SGX capability of processor state configuration and enclave |
| 2752 | configuration in the SECS structure. |
| 2753 | |
| 2754 | @param EAX CPUID_INTEL_SGX (0x12) |
| 2755 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01) |
| 2756 | |
| 2757 | @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can |
| 2758 | set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE |
| 2759 | only if EAX[n] is 1, where n < 32. |
| 2760 | @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can |
| 2761 | set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE |
| 2762 | only if EBX[n] is 1, where n < 32. |
| 2763 | @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can |
| 2764 | set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE |
| 2765 | only if ECX[n] is 1, where n < 32. |
| 2766 | @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can |
| 2767 | set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE |
| 2768 | only if EDX[n] is 1, where n < 32. |
| 2769 | |
| 2770 | <b>Example usage</b> |
| 2771 | @code |
| 2772 | UINT32 Eax; |
| 2773 | UINT32 Ebx; |
| 2774 | UINT32 Ecx; |
| 2775 | UINT32 Edx; |
| 2776 | |
| 2777 | AsmCpuidEx ( |
| 2778 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, |
| 2779 | &Eax, &Ebx, &Ecx, &Edx |
| 2780 | ); |
| 2781 | @endcode |
| 2782 | **/ |
| 2783 | #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01 |
| 2784 | |
| 2785 | |
| 2786 | /** |
| 2787 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources. |
| 2788 | Enumerates available EPC resources. |
| 2789 | |
| 2790 | @param EAX CPUID_INTEL_SGX (0x12) |
| 2791 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02) |
| 2792 | |
| 2793 | @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX |
| 2794 | Resources is described by the type |
| 2795 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX. |
| 2796 | @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX |
| 2797 | Resources is described by the type |
| 2798 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX. |
| 2799 | @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX |
| 2800 | Resources is described by the type |
| 2801 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX. |
| 2802 | @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX |
| 2803 | Resources is described by the type |
| 2804 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX. |
| 2805 | |
| 2806 | <b>Example usage</b> |
| 2807 | @code |
| 2808 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax; |
| 2809 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx; |
| 2810 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx; |
| 2811 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx; |
| 2812 | |
| 2813 | AsmCpuidEx ( |
| 2814 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF, |
| 2815 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 |
| 2816 | ); |
| 2817 | @endcode |
| 2818 | **/ |
| 2819 | #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02 |
| 2820 | |
| 2821 | /** |
| 2822 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID |
| 2823 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. |
| 2824 | **/ |
| 2825 | typedef union { |
| 2826 | /// |
| 2827 | /// Individual bit fields |
| 2828 | /// |
| 2829 | struct { |
| 2830 | /// |
| 2831 | /// [Bit 3:0] Sub-leaf-type encoding. |
| 2832 | /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0. |
| 2833 | /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC) |
| 2834 | /// in EBX:EAX and EDX:ECX. |
| 2835 | /// All other encoding are reserved. |
| 2836 | /// |
| 2837 | UINT32 SubLeafType:4; |
| 2838 | UINT32 Reserved:8; |
| 2839 | /// |
| 2840 | /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of |
| 2841 | /// the base of the EPC section. |
| 2842 | /// |
| 2843 | UINT32 LowAddressOfEpcSection:20; |
| 2844 | } Bits; |
| 2845 | /// |
| 2846 | /// All bit fields as a 32-bit value |
| 2847 | /// |
| 2848 | UINT32 Uint32; |
| 2849 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX; |
| 2850 | |
| 2851 | /** |
| 2852 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID |
| 2853 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. |
| 2854 | **/ |
| 2855 | typedef union { |
| 2856 | /// |
| 2857 | /// Individual bit fields |
| 2858 | /// |
| 2859 | struct { |
| 2860 | /// |
| 2861 | /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of |
| 2862 | /// the base of the EPC section. |
| 2863 | /// |
| 2864 | UINT32 HighAddressOfEpcSection:20; |
| 2865 | UINT32 Reserved:12; |
| 2866 | } Bits; |
| 2867 | /// |
| 2868 | /// All bit fields as a 32-bit value |
| 2869 | /// |
| 2870 | UINT32 Uint32; |
| 2871 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX; |
| 2872 | |
| 2873 | /** |
| 2874 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID |
| 2875 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. |
| 2876 | **/ |
| 2877 | typedef union { |
| 2878 | /// |
| 2879 | /// Individual bit fields |
| 2880 | /// |
| 2881 | struct { |
| 2882 | /// |
| 2883 | /// [Bit 3:0] The EPC section encoding. |
| 2884 | /// 0000b: Not valid. |
| 2885 | /// 0001b: The EPC section is confidentiality, integrity and replay protected. |
| 2886 | /// All other encoding are reserved. |
| 2887 | /// |
| 2888 | UINT32 EpcSection:4; |
| 2889 | UINT32 Reserved:8; |
| 2890 | /// |
| 2891 | /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the |
| 2892 | /// corresponding EPC section within the Processor Reserved Memory. |
| 2893 | /// |
| 2894 | UINT32 LowSizeOfEpcSection:20; |
| 2895 | } Bits; |
| 2896 | /// |
| 2897 | /// All bit fields as a 32-bit value |
| 2898 | /// |
| 2899 | UINT32 Uint32; |
| 2900 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX; |
| 2901 | |
| 2902 | /** |
| 2903 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID |
| 2904 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. |
| 2905 | **/ |
| 2906 | typedef union { |
| 2907 | /// |
| 2908 | /// Individual bit fields |
| 2909 | /// |
| 2910 | struct { |
| 2911 | /// |
| 2912 | /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the |
| 2913 | /// corresponding EPC section within the Processor Reserved Memory. |
| 2914 | /// |
| 2915 | UINT32 HighSizeOfEpcSection:20; |
| 2916 | UINT32 Reserved:12; |
| 2917 | } Bits; |
| 2918 | /// |
| 2919 | /// All bit fields as a 32-bit value |
| 2920 | /// |
| 2921 | UINT32 Uint32; |
| 2922 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX; |
| 2923 | |
| 2924 | |
| 2925 | /** |
| 2926 | CPUID Intel Processor Trace Information |
| 2927 | |
| 2928 | @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14) |
| 2929 | @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00). |
| 2930 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01). |
| 2931 | |
| 2932 | **/ |
| 2933 | #define CPUID_INTEL_PROCESSOR_TRACE 0x14 |
| 2934 | |
| 2935 | /** |
| 2936 | CPUID Intel Processor Trace Information Main Leaf |
| 2937 | |
| 2938 | @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) |
| 2939 | @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00) |
| 2940 | |
| 2941 | @retval EAX Reports the maximum sub-leaf supported in leaf 14H. |
| 2942 | @retval EBX Returns Intel processor trace information described by the |
| 2943 | type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX. |
| 2944 | @retval ECX Returns Intel processor trace information described by the |
| 2945 | type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX. |
| 2946 | @retval EDX Reserved. |
| 2947 | |
| 2948 | <b>Example usage</b> |
| 2949 | @code |
| 2950 | UINT32 Eax; |
| 2951 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx; |
| 2952 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; |
| 2953 | |
| 2954 | AsmCpuidEx ( |
| 2955 | CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, |
| 2956 | &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL |
| 2957 | ); |
| 2958 | @endcode |
| 2959 | **/ |
| 2960 | #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00 |
| 2961 | |
| 2962 | /** |
| 2963 | CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, |
| 2964 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. |
| 2965 | **/ |
| 2966 | typedef union { |
| 2967 | /// |
| 2968 | /// Individual bit fields |
| 2969 | /// |
| 2970 | struct { |
| 2971 | /// |
| 2972 | /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, |
| 2973 | /// and that IA32_RTIT_CR3_MATCH MSR can be accessed. |
| 2974 | /// |
| 2975 | UINT32 Cr3Filter:1; |
| 2976 | /// |
| 2977 | /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate |
| 2978 | /// Mode. |
| 2979 | /// |
| 2980 | UINT32 ConfigurablePsb:1; |
| 2981 | /// |
| 2982 | /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering, |
| 2983 | /// and preservation of Intel PT MSRs across warm reset. |
| 2984 | /// |
| 2985 | UINT32 IpTraceStopFiltering:1; |
| 2986 | /// |
| 2987 | /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of |
| 2988 | /// COFI-based packets. |
| 2989 | /// |
| 2990 | UINT32 Mtc:1; |
| 2991 | /// |
| 2992 | /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set |
| 2993 | /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE |
| 2994 | /// can generate packets. |
| 2995 | /// |
| 2996 | UINT32 PTWrite:1; |
| 2997 | /// |
| 2998 | /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set |
| 2999 | /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet |
| 3000 | /// generation. |
| 3001 | /// |
| 3002 | UINT32 PowerEventTrace:1; |
| 3003 | UINT32 Reserved:26; |
| 3004 | } Bits; |
| 3005 | /// |
| 3006 | /// All bit fields as a 32-bit value |
| 3007 | /// |
| 3008 | UINT32 Uint32; |
| 3009 | } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX; |
| 3010 | |
| 3011 | /** |
| 3012 | CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, |
| 3013 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. |
| 3014 | **/ |
| 3015 | typedef union { |
| 3016 | /// |
| 3017 | /// Individual bit fields |
| 3018 | /// |
| 3019 | struct { |
| 3020 | /// |
| 3021 | /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence |
| 3022 | /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and |
| 3023 | /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed. |
| 3024 | /// |
| 3025 | UINT32 RTIT:1; |
| 3026 | /// |
| 3027 | /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to |
| 3028 | /// the maximum allowed by the MaskOrTableOffset field of |
| 3029 | /// IA32_RTIT_OUTPUT_MASK_PTRS. |
| 3030 | /// |
| 3031 | UINT32 ToPA:1; |
| 3032 | /// |
| 3033 | /// [Bit 2] If 1, indicates support of Single-Range Output scheme. |
| 3034 | /// |
| 3035 | UINT32 SingleRangeOutput:1; |
| 3036 | /// |
| 3037 | /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem. |
| 3038 | /// |
| 3039 | UINT32 TraceTransportSubsystem:1; |
| 3040 | UINT32 Reserved:27; |
| 3041 | /// |
| 3042 | /// [Bit 31] If 1, generated packets which contain IP payloads have LIP |
| 3043 | /// values, which include the CS base component. |
| 3044 | /// |
| 3045 | UINT32 LIP:1; |
| 3046 | } Bits; |
| 3047 | /// |
| 3048 | /// All bit fields as a 32-bit value |
| 3049 | /// |
| 3050 | UINT32 Uint32; |
| 3051 | } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX; |
| 3052 | |
| 3053 | |
| 3054 | /** |
| 3055 | CPUID Intel Processor Trace Information Sub-leaf |
| 3056 | |
| 3057 | @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) |
| 3058 | @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01) |
| 3059 | |
| 3060 | @retval EAX Returns Intel processor trace information described by the |
| 3061 | type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX. |
| 3062 | @retval EBX Returns Intel processor trace information described by the |
| 3063 | type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX. |
| 3064 | @retval ECX Reserved. |
| 3065 | @retval EDX Reserved. |
| 3066 | |
| 3067 | <b>Example usage</b> |
| 3068 | @code |
| 3069 | UINT32 MaximumSubLeaf; |
| 3070 | UINT32 SubLeaf; |
| 3071 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax; |
| 3072 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx; |
| 3073 | |
| 3074 | AsmCpuidEx ( |
| 3075 | CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, |
| 3076 | &MaximumSubLeaf, NULL, NULL, NULL |
| 3077 | ); |
| 3078 | |
| 3079 | for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) { |
| 3080 | AsmCpuidEx ( |
| 3081 | CPUID_INTEL_PROCESSOR_TRACE, SubLeaf, |
| 3082 | &Eax.Uint32, &Ebx.Uint32, NULL, NULL |
| 3083 | ); |
| 3084 | } |
| 3085 | @endcode |
| 3086 | **/ |
| 3087 | #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01 |
| 3088 | |
| 3089 | /** |
| 3090 | CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, |
| 3091 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. |
| 3092 | **/ |
| 3093 | typedef union { |
| 3094 | /// |
| 3095 | /// Individual bit fields |
| 3096 | /// |
| 3097 | struct { |
| 3098 | /// |
| 3099 | /// [Bits 2:0] Number of configurable Address Ranges for filtering. |
| 3100 | /// |
| 3101 | UINT32 ConfigurableAddressRanges:3; |
| 3102 | UINT32 Reserved:13; |
| 3103 | /// |
| 3104 | /// [Bits 31:16] Bitmap of supported MTC period encodings |
| 3105 | /// |
| 3106 | UINT32 MtcPeriodEncodings:16; |
| 3107 | |
| 3108 | } Bits; |
| 3109 | /// |
| 3110 | /// All bit fields as a 32-bit value |
| 3111 | /// |
| 3112 | UINT32 Uint32; |
| 3113 | } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX; |
| 3114 | |
| 3115 | /** |
| 3116 | CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, |
| 3117 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. |
| 3118 | **/ |
| 3119 | typedef union { |
| 3120 | /// |
| 3121 | /// Individual bit fields |
| 3122 | /// |
| 3123 | struct { |
| 3124 | /// |
| 3125 | /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings. |
| 3126 | /// |
| 3127 | UINT32 CycleThresholdEncodings:16; |
| 3128 | /// |
| 3129 | /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings. |
| 3130 | /// |
| 3131 | UINT32 PsbFrequencyEncodings:16; |
| 3132 | |
| 3133 | } Bits; |
| 3134 | /// |
| 3135 | /// All bit fields as a 32-bit value |
| 3136 | /// |
| 3137 | UINT32 Uint32; |
| 3138 | } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX; |
| 3139 | |
| 3140 | |
| 3141 | /** |
| 3142 | CPUID Time Stamp Counter and Nominal Core Crystal Clock Information |
| 3143 | |
| 3144 | @note |
| 3145 | If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated. |
| 3146 | EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core |
| 3147 | crystal clock frequency. |
| 3148 | If ECX is 0, the nominal core crystal clock frequency is not enumerated. |
| 3149 | "TSC frequency" = "core crystal clock frequency" * EBX/EAX. |
| 3150 | The core crystal clock may differ from the reference clock, bus clock, or core |
| 3151 | clock frequencies. |
| 3152 | |
| 3153 | @param EAX CPUID_TIME_STAMP_COUNTER (0x15) |
| 3154 | |
| 3155 | @retval EAX An unsigned integer which is the denominator of the |
| 3156 | TSC/"core crystal clock" ratio |
| 3157 | @retval EBX An unsigned integer which is the numerator of the |
| 3158 | TSC/"core crystal clock" ratio. |
| 3159 | @retval ECX An unsigned integer which is the nominal frequency |
| 3160 | of the core crystal clock in Hz. |
| 3161 | @retval EDX Reserved. |
| 3162 | |
| 3163 | <b>Example usage</b> |
| 3164 | @code |
| 3165 | UINT32 Eax; |
| 3166 | UINT32 Ebx; |
| 3167 | UINT32 Ecx; |
| 3168 | |
| 3169 | AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL); |
| 3170 | @endcode |
| 3171 | **/ |
| 3172 | #define CPUID_TIME_STAMP_COUNTER 0x15 |
| 3173 | |
| 3174 | |
| 3175 | /** |
| 3176 | CPUID Processor Frequency Information |
| 3177 | |
| 3178 | @note |
| 3179 | Data is returned from this interface in accordance with the processor's |
| 3180 | specification and does not reflect actual values. Suitable use of this data |
| 3181 | includes the display of processor information in like manner to the processor |
| 3182 | brand string and for determining the appropriate range to use when displaying |
| 3183 | processor information e.g. frequency history graphs. The returned information |
| 3184 | should not be used for any other purpose as the returned information does not |
| 3185 | accurately correlate to information / counters returned by other processor |
| 3186 | interfaces. While a processor may support the Processor Frequency Information |
| 3187 | leaf, fields that return a value of zero are not supported. |
| 3188 | |
| 3189 | @param EAX CPUID_TIME_STAMP_COUNTER (0x16) |
| 3190 | |
| 3191 | @retval EAX Returns processor base frequency information described by the |
| 3192 | type CPUID_PROCESSOR_FREQUENCY_EAX. |
| 3193 | @retval EBX Returns maximum frequency information described by the type |
| 3194 | CPUID_PROCESSOR_FREQUENCY_EBX. |
| 3195 | @retval ECX Returns bus frequency information described by the type |
| 3196 | CPUID_PROCESSOR_FREQUENCY_ECX. |
| 3197 | @retval EDX Reserved. |
| 3198 | |
| 3199 | <b>Example usage</b> |
| 3200 | @code |
| 3201 | CPUID_PROCESSOR_FREQUENCY_EAX Eax; |
| 3202 | CPUID_PROCESSOR_FREQUENCY_EBX Ebx; |
| 3203 | CPUID_PROCESSOR_FREQUENCY_ECX Ecx; |
| 3204 | |
| 3205 | AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); |
| 3206 | @endcode |
| 3207 | **/ |
| 3208 | #define CPUID_PROCESSOR_FREQUENCY 0x16 |
| 3209 | |
| 3210 | /** |
| 3211 | CPUID Processor Frequency Information EAX for CPUID leaf |
| 3212 | #CPUID_PROCESSOR_FREQUENCY. |
| 3213 | **/ |
| 3214 | typedef union { |
| 3215 | /// |
| 3216 | /// Individual bit fields |
| 3217 | /// |
| 3218 | struct { |
| 3219 | /// |
| 3220 | /// [Bits 15:0] Processor Base Frequency (in MHz). |
| 3221 | /// |
| 3222 | UINT32 ProcessorBaseFrequency:16; |
| 3223 | UINT32 Reserved:16; |
| 3224 | } Bits; |
| 3225 | /// |
| 3226 | /// All bit fields as a 32-bit value |
| 3227 | /// |
| 3228 | UINT32 Uint32; |
| 3229 | } CPUID_PROCESSOR_FREQUENCY_EAX; |
| 3230 | |
| 3231 | /** |
| 3232 | CPUID Processor Frequency Information EBX for CPUID leaf |
| 3233 | #CPUID_PROCESSOR_FREQUENCY. |
| 3234 | **/ |
| 3235 | typedef union { |
| 3236 | /// |
| 3237 | /// Individual bit fields |
| 3238 | /// |
| 3239 | struct { |
| 3240 | /// |
| 3241 | /// [Bits 15:0] Maximum Frequency (in MHz). |
| 3242 | /// |
| 3243 | UINT32 MaximumFrequency:16; |
| 3244 | UINT32 Reserved:16; |
| 3245 | } Bits; |
| 3246 | /// |
| 3247 | /// All bit fields as a 32-bit value |
| 3248 | /// |
| 3249 | UINT32 Uint32; |
| 3250 | } CPUID_PROCESSOR_FREQUENCY_EBX; |
| 3251 | |
| 3252 | /** |
| 3253 | CPUID Processor Frequency Information ECX for CPUID leaf |
| 3254 | #CPUID_PROCESSOR_FREQUENCY. |
| 3255 | **/ |
| 3256 | typedef union { |
| 3257 | /// |
| 3258 | /// Individual bit fields |
| 3259 | /// |
| 3260 | struct { |
| 3261 | /// |
| 3262 | /// [Bits 15:0] Bus (Reference) Frequency (in MHz). |
| 3263 | /// |
| 3264 | UINT32 BusFrequency:16; |
| 3265 | UINT32 Reserved:16; |
| 3266 | } Bits; |
| 3267 | /// |
| 3268 | /// All bit fields as a 32-bit value |
| 3269 | /// |
| 3270 | UINT32 Uint32; |
| 3271 | } CPUID_PROCESSOR_FREQUENCY_ECX; |
| 3272 | |
| 3273 | |
| 3274 | /** |
| 3275 | CPUID SoC Vendor Information |
| 3276 | |
| 3277 | @param EAX CPUID_SOC_VENDOR (0x17) |
| 3278 | @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) |
| 3279 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) |
| 3280 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x02) |
| 3281 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x03) |
| 3282 | |
| 3283 | @note |
| 3284 | Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String |
| 3285 | is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC |
| 3286 | Vendor Brand String is constructed by concatenating in ascending order of |
| 3287 | EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3. |
| 3288 | |
| 3289 | **/ |
| 3290 | #define CPUID_SOC_VENDOR 0x17 |
| 3291 | |
| 3292 | /** |
| 3293 | CPUID SoC Vendor Information |
| 3294 | |
| 3295 | @param EAX CPUID_SOC_VENDOR (0x17) |
| 3296 | @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) |
| 3297 | |
| 3298 | @retval EAX MaxSOCID_Index. Reports the maximum input value of supported |
| 3299 | sub-leaf in leaf 17H. |
| 3300 | @retval EBX Returns SoC Vendor information described by the type |
| 3301 | CPUID_SOC_VENDOR_MAIN_LEAF_EBX. |
| 3302 | @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC |
| 3303 | projects. |
| 3304 | @retval EDX Stepping ID. A unique number within an SOC project that an SOC |
| 3305 | vendor assigns. |
| 3306 | |
| 3307 | <b>Example usage</b> |
| 3308 | @code |
| 3309 | UINT32 Eax; |
| 3310 | CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx; |
| 3311 | UINT32 Ecx; |
| 3312 | UINT32 Edx; |
| 3313 | |
| 3314 | AsmCpuidEx ( |
| 3315 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF, |
| 3316 | &Eax, &Ebx.Uint32, &Ecx, &Edx |
| 3317 | ); |
| 3318 | @endcode |
| 3319 | **/ |
| 3320 | #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00 |
| 3321 | |
| 3322 | /** |
| 3323 | CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf |
| 3324 | #CPUID_SOC_VENDOR_MAIN_LEAF. |
| 3325 | **/ |
| 3326 | typedef union { |
| 3327 | /// |
| 3328 | /// Individual bit fields |
| 3329 | /// |
| 3330 | struct { |
| 3331 | /// |
| 3332 | /// [Bits 15:0] SOC Vendor ID. |
| 3333 | /// |
| 3334 | UINT32 SocVendorId:16; |
| 3335 | /// |
| 3336 | /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry |
| 3337 | /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is |
| 3338 | /// assigned by Intel. |
| 3339 | /// |
| 3340 | UINT32 IsVendorScheme:1; |
| 3341 | UINT32 Reserved:15; |
| 3342 | } Bits; |
| 3343 | /// |
| 3344 | /// All bit fields as a 32-bit value |
| 3345 | /// |
| 3346 | UINT32 Uint32; |
| 3347 | } CPUID_SOC_VENDOR_MAIN_LEAF_EBX; |
| 3348 | |
| 3349 | /** |
| 3350 | CPUID SoC Vendor Information |
| 3351 | |
| 3352 | @param EAX CPUID_SOC_VENDOR (0x17) |
| 3353 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) |
| 3354 | |
| 3355 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3356 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3357 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3358 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3359 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3360 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3361 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3362 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3363 | |
| 3364 | <b>Example usage</b> |
| 3365 | @code |
| 3366 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; |
| 3367 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; |
| 3368 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; |
| 3369 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; |
| 3370 | |
| 3371 | AsmCpuidEx ( |
| 3372 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1, |
| 3373 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 |
| 3374 | ); |
| 3375 | @endcode |
| 3376 | **/ |
| 3377 | #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01 |
| 3378 | |
| 3379 | /** |
| 3380 | CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1, |
| 3381 | #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3. |
| 3382 | **/ |
| 3383 | typedef union { |
| 3384 | /// |
| 3385 | /// 4 UTF-8 characters of Soc Vendor Brand String |
| 3386 | /// |
| 3387 | CHAR8 BrandString[4]; |
| 3388 | /// |
| 3389 | /// All fields as a 32-bit value |
| 3390 | /// |
| 3391 | UINT32 Uint32; |
| 3392 | } CPUID_SOC_VENDOR_BRAND_STRING_DATA; |
| 3393 | |
| 3394 | /** |
| 3395 | CPUID SoC Vendor Information |
| 3396 | |
| 3397 | @param EAX CPUID_SOC_VENDOR (0x17) |
| 3398 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02) |
| 3399 | |
| 3400 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3401 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3402 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3403 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3404 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3405 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3406 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3407 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3408 | |
| 3409 | <b>Example usage</b> |
| 3410 | @code |
| 3411 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; |
| 3412 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; |
| 3413 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; |
| 3414 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; |
| 3415 | |
| 3416 | AsmCpuidEx ( |
| 3417 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2, |
| 3418 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 |
| 3419 | ); |
| 3420 | @endcode |
| 3421 | **/ |
| 3422 | #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02 |
| 3423 | |
| 3424 | /** |
| 3425 | CPUID SoC Vendor Information |
| 3426 | |
| 3427 | @param EAX CPUID_SOC_VENDOR (0x17) |
| 3428 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03) |
| 3429 | |
| 3430 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3431 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3432 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3433 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3434 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3435 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3436 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type |
| 3437 | CPUID_SOC_VENDOR_BRAND_STRING_DATA. |
| 3438 | |
| 3439 | <b>Example usage</b> |
| 3440 | @code |
| 3441 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; |
| 3442 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; |
| 3443 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; |
| 3444 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; |
| 3445 | |
| 3446 | AsmCpuidEx ( |
| 3447 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3, |
| 3448 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 |
| 3449 | ); |
| 3450 | @endcode |
| 3451 | **/ |
| 3452 | #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03 |
| 3453 | |
| 3454 | /** |
| 3455 | CPUID Deterministic Address Translation Parameters |
| 3456 | |
| 3457 | @note |
| 3458 | Each sub-leaf enumerates a different address translation structure. |
| 3459 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf |
| 3460 | index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A |
| 3461 | sub-leaf index is also invalid if EDX[4:0] returns 0. |
| 3462 | Valid sub-leaves do not need to be contiguous or in any particular order. A |
| 3463 | valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or |
| 3464 | than a valid sub-leaf of a higher or lower-level structure. |
| 3465 | * Some unified TLBs will allow a single TLB entry to satisfy data read/write |
| 3466 | and instruction fetches. Others will require separate entries (e.g., one |
| 3467 | loaded on data read/write and another loaded on an instruction fetch). |
| 3468 | Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual |
| 3469 | for details of a particular product. |
| 3470 | ** Add one to the return value to get the result. |
| 3471 | |
| 3472 | @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) |
| 3473 | @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) |
| 3474 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*) |
| 3475 | |
| 3476 | **/ |
| 3477 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 |
| 3478 | |
| 3479 | /** |
| 3480 | CPUID Deterministic Address Translation Parameters |
| 3481 | |
| 3482 | @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) |
| 3483 | @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) |
| 3484 | |
| 3485 | @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H. |
| 3486 | @retval EBX Returns Deterministic Address Translation Parameters described by |
| 3487 | the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX. |
| 3488 | @retval ECX Number of Sets. |
| 3489 | @retval EDX Returns Deterministic Address Translation Parameters described by |
| 3490 | the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX. |
| 3491 | |
| 3492 | <b>Example usage</b> |
| 3493 | @code |
| 3494 | UINT32 Eax; |
| 3495 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx; |
| 3496 | UINT32 Ecx; |
| 3497 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx; |
| 3498 | |
| 3499 | AsmCpuidEx ( |
| 3500 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, |
| 3501 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF, |
| 3502 | &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32 |
| 3503 | ); |
| 3504 | @endcode |
| 3505 | **/ |
| 3506 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00 |
| 3507 | |
| 3508 | /** |
| 3509 | CPUID Deterministic Address Translation Parameters EBX for CPUID leafs. |
| 3510 | **/ |
| 3511 | typedef union { |
| 3512 | /// |
| 3513 | /// Individual bit fields |
| 3514 | /// |
| 3515 | struct { |
| 3516 | /// |
| 3517 | /// [Bits 0] 4K page size entries supported by this structure. |
| 3518 | /// |
| 3519 | UINT32 Page4K:1; |
| 3520 | /// |
| 3521 | /// [Bits 1] 2MB page size entries supported by this structure. |
| 3522 | /// |
| 3523 | UINT32 Page2M:1; |
| 3524 | /// |
| 3525 | /// [Bits 2] 4MB page size entries supported by this structure. |
| 3526 | /// |
| 3527 | UINT32 Page4M:1; |
| 3528 | /// |
| 3529 | /// [Bits 3] 1 GB page size entries supported by this structure. |
| 3530 | /// |
| 3531 | UINT32 Page1G:1; |
| 3532 | /// |
| 3533 | /// [Bits 7:4] Reserved. |
| 3534 | /// |
| 3535 | UINT32 Reserved1:4; |
| 3536 | /// |
| 3537 | /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical |
| 3538 | /// processors sharing this structure) |
| 3539 | /// |
| 3540 | UINT32 Partitioning:3; |
| 3541 | /// |
| 3542 | /// [Bits 15:11] Reserved. |
| 3543 | /// |
| 3544 | UINT32 Reserved2:5; |
| 3545 | /// |
| 3546 | /// [Bits 31:16] W = Ways of associativity. |
| 3547 | /// |
| 3548 | UINT32 Way:16; |
| 3549 | } Bits; |
| 3550 | /// |
| 3551 | /// All bit fields as a 32-bit value |
| 3552 | /// |
| 3553 | UINT32 Uint32; |
| 3554 | } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX; |
| 3555 | |
| 3556 | /** |
| 3557 | CPUID Deterministic Address Translation Parameters EDX for CPUID leafs. |
| 3558 | **/ |
| 3559 | typedef union { |
| 3560 | /// |
| 3561 | /// Individual bit fields |
| 3562 | /// |
| 3563 | struct { |
| 3564 | /// |
| 3565 | /// [Bits 4:0] Translation cache type field. |
| 3566 | /// |
| 3567 | UINT32 TranslationCacheType:5; |
| 3568 | /// |
| 3569 | /// [Bits 7:5] Translation cache level (starts at 1). |
| 3570 | /// |
| 3571 | UINT32 TranslationCacheLevel:3; |
| 3572 | /// |
| 3573 | /// [Bits 8] Fully associative structure. |
| 3574 | /// |
| 3575 | UINT32 FullyAssociative:1; |
| 3576 | /// |
| 3577 | /// [Bits 13:9] Reserved. |
| 3578 | /// |
| 3579 | UINT32 Reserved1:5; |
| 3580 | /// |
| 3581 | /// [Bits 25:14] Maximum number of addressable IDs for logical |
| 3582 | /// processors sharing this translation cache. |
| 3583 | /// |
| 3584 | UINT32 MaximumNum:12; |
| 3585 | /// |
| 3586 | /// [Bits 31:26] Reserved. |
| 3587 | /// |
| 3588 | UINT32 Reserved2:6; |
| 3589 | } Bits; |
| 3590 | /// |
| 3591 | /// All bit fields as a 32-bit value |
| 3592 | /// |
| 3593 | UINT32 Uint32; |
| 3594 | } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX; |
| 3595 | |
| 3596 | /// |
| 3597 | /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType |
| 3598 | /// |
| 3599 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00 |
| 3600 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01 |
| 3601 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02 |
| 3602 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03 |
| 3603 | /// |
| 3604 | /// @} |
| 3605 | /// |
| 3606 | |
| 3607 | |
| 3608 | /** |
| 3609 | CPUID Hybrid Information Enumeration Leaf |
| 3610 | |
| 3611 | @param EAX CPUID_HYBRID_INFORMATION (0x1A) |
| 3612 | @param ECX CPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00). |
| 3613 | |
| 3614 | @retval EAX Enumerates the native model ID and core type described |
| 3615 | by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX |
| 3616 | @retval EBX Reserved. |
| 3617 | @retval ECX Reserved. |
| 3618 | @retval EDX Reserved. |
| 3619 | |
| 3620 | <b>Example usage</b> |
| 3621 | @code |
| 3622 | CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX Eax; |
| 3623 | |
| 3624 | AsmCpuidEx ( |
| 3625 | CPUID_HYBRID_INFORMATION, |
| 3626 | CPUID_HYBRID_INFORMATION_MAIN_LEAF, |
| 3627 | &Eax, NULL, NULL, NULL |
| 3628 | ); |
| 3629 | @endcode |
| 3630 | |
| 3631 | **/ |
| 3632 | #define CPUID_HYBRID_INFORMATION 0x1A |
| 3633 | |
| 3634 | /// |
| 3635 | /// CPUID Hybrid Information Enumeration main leaf |
| 3636 | /// |
| 3637 | #define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00 |
| 3638 | |
| 3639 | /** |
| 3640 | CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION, |
| 3641 | main leaf #CPUID_HYBRID_INFORMATION_MAIN_LEAF. |
| 3642 | **/ |
| 3643 | typedef union { |
| 3644 | /// |
| 3645 | /// Individual bit fields |
| 3646 | /// |
| 3647 | struct { |
| 3648 | /// |
| 3649 | /// [Bit 23:0] Native model ID of the core. |
| 3650 | /// |
| 3651 | /// The core-type and native mode ID can be used to uniquely identify |
| 3652 | /// the microarchitecture of the core.This native model ID is not unique |
| 3653 | /// across core types, and not related to the model ID reported in CPUID |
| 3654 | /// leaf 01H, and does not identify the SOC. |
| 3655 | /// |
| 3656 | UINT32 NativeModelId:24; |
| 3657 | /// |
| 3658 | /// [Bit 31:24] Core type |
| 3659 | /// |
| 3660 | UINT32 CoreType:8; |
| 3661 | } Bits; |
| 3662 | /// |
| 3663 | /// All bit fields as a 32-bit value |
| 3664 | /// |
| 3665 | UINT32 Uint32; |
| 3666 | } CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX; |
| 3667 | |
| 3668 | /// |
| 3669 | /// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType |
| 3670 | /// |
| 3671 | #define CPUID_CORE_TYPE_INTEL_ATOM 0x20 |
| 3672 | #define CPUID_CORE_TYPE_INTEL_CORE 0x40 |
| 3673 | /// |
| 3674 | /// @} |
| 3675 | /// |
| 3676 | |
| 3677 | |
| 3678 | /** |
| 3679 | CPUID V2 Extended Topology Enumeration Leaf |
| 3680 | |
| 3681 | @note |
| 3682 | CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking |
| 3683 | for the existence of Leaf 1FH and using this if available. |
| 3684 | Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf |
| 3685 | 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0] |
| 3686 | always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each |
| 3687 | subsequent higher sub-leaf index enumerates a higher-level topological entity in |
| 3688 | hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; |
| 3689 | EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of |
| 3690 | 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8]. |
| 3691 | |
| 3692 | Software should use this field (EAX[4:0]) to enumerate processor topology of the system. |
| 3693 | Software must not use EBX[15:0] to enumerate processor topology of the system. This value |
| 3694 | in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual |
| 3695 | number of logical processors available to BIOS/OS/Applications may be different from the |
| 3696 | value of EBX[15:0], depending on software and platform hardware configurations. |
| 3697 | |
| 3698 | @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F) |
| 3699 | @param ECX Level number |
| 3700 | |
| 3701 | **/ |
| 3702 | #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F |
| 3703 | |
| 3704 | /// |
| 3705 | /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType |
| 3706 | /// The value of the "level type" field is not related to level numbers in |
| 3707 | /// any way, higher "level type" values do not mean higher levels. |
| 3708 | /// |
| 3709 | #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03 |
| 3710 | #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04 |
| 3711 | #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05 |
| 3712 | /// |
| 3713 | /// @} |
| 3714 | /// |
| 3715 | |
| 3716 | /** |
| 3717 | CPUID Extended Function |
| 3718 | |
| 3719 | @param EAX CPUID_EXTENDED_FUNCTION (0x80000000) |
| 3720 | |
| 3721 | @retval EAX Maximum Input Value for Extended Function CPUID Information. |
| 3722 | @retval EBX Reserved. |
| 3723 | @retval ECX Reserved. |
| 3724 | @retval EDX Reserved. |
| 3725 | |
| 3726 | <b>Example usage</b> |
| 3727 | @code |
| 3728 | UINT32 Eax; |
| 3729 | |
| 3730 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); |
| 3731 | @endcode |
| 3732 | **/ |
| 3733 | #define CPUID_EXTENDED_FUNCTION 0x80000000 |
| 3734 | |
| 3735 | |
| 3736 | /** |
| 3737 | CPUID Extended Processor Signature and Feature Bits |
| 3738 | |
| 3739 | @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) |
| 3740 | |
| 3741 | @retval EAX CPUID_EXTENDED_CPU_SIG. |
| 3742 | @retval EBX Reserved. |
| 3743 | @retval ECX Extended Processor Signature and Feature Bits information |
| 3744 | described by the type CPUID_EXTENDED_CPU_SIG_ECX. |
| 3745 | @retval EDX Extended Processor Signature and Feature Bits information |
| 3746 | described by the type CPUID_EXTENDED_CPU_SIG_EDX. |
| 3747 | |
| 3748 | <b>Example usage</b> |
| 3749 | @code |
| 3750 | UINT32 Eax; |
| 3751 | CPUID_EXTENDED_CPU_SIG_ECX Ecx; |
| 3752 | CPUID_EXTENDED_CPU_SIG_EDX Edx; |
| 3753 | |
| 3754 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32); |
| 3755 | @endcode |
| 3756 | **/ |
| 3757 | #define CPUID_EXTENDED_CPU_SIG 0x80000001 |
| 3758 | |
| 3759 | /** |
| 3760 | CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf |
| 3761 | #CPUID_EXTENDED_CPU_SIG. |
| 3762 | **/ |
| 3763 | typedef union { |
| 3764 | /// |
| 3765 | /// Individual bit fields |
| 3766 | /// |
| 3767 | struct { |
| 3768 | /// |
| 3769 | /// [Bit 0] LAHF/SAHF available in 64-bit mode. |
| 3770 | /// |
| 3771 | UINT32 LAHF_SAHF:1; |
| 3772 | UINT32 Reserved1:4; |
| 3773 | /// |
| 3774 | /// [Bit 5] LZCNT. |
| 3775 | /// |
| 3776 | UINT32 LZCNT:1; |
| 3777 | UINT32 Reserved2:2; |
| 3778 | /// |
| 3779 | /// [Bit 8] PREFETCHW. |
| 3780 | /// |
| 3781 | UINT32 PREFETCHW:1; |
| 3782 | UINT32 Reserved3:23; |
| 3783 | } Bits; |
| 3784 | /// |
| 3785 | /// All bit fields as a 32-bit value |
| 3786 | /// |
| 3787 | UINT32 Uint32; |
| 3788 | } CPUID_EXTENDED_CPU_SIG_ECX; |
| 3789 | |
| 3790 | /** |
| 3791 | CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf |
| 3792 | #CPUID_EXTENDED_CPU_SIG. |
| 3793 | **/ |
| 3794 | typedef union { |
| 3795 | /// |
| 3796 | /// Individual bit fields |
| 3797 | /// |
| 3798 | struct { |
| 3799 | UINT32 Reserved1:11; |
| 3800 | /// |
| 3801 | /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode. |
| 3802 | /// |
| 3803 | UINT32 SYSCALL_SYSRET:1; |
| 3804 | UINT32 Reserved2:8; |
| 3805 | /// |
| 3806 | /// [Bit 20] Execute Disable Bit available. |
| 3807 | /// |
| 3808 | UINT32 NX:1; |
| 3809 | UINT32 Reserved3:5; |
| 3810 | /// |
| 3811 | /// [Bit 26] 1-GByte pages are available if 1. |
| 3812 | /// |
| 3813 | UINT32 Page1GB:1; |
| 3814 | /// |
| 3815 | /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1. |
| 3816 | /// |
| 3817 | UINT32 RDTSCP:1; |
| 3818 | UINT32 Reserved4:1; |
| 3819 | /// |
| 3820 | /// [Bit 29] Intel(R) 64 Architecture available if 1. |
| 3821 | /// |
| 3822 | UINT32 LM:1; |
| 3823 | UINT32 Reserved5:2; |
| 3824 | } Bits; |
| 3825 | /// |
| 3826 | /// All bit fields as a 32-bit value |
| 3827 | /// |
| 3828 | UINT32 Uint32; |
| 3829 | } CPUID_EXTENDED_CPU_SIG_EDX; |
| 3830 | |
| 3831 | |
| 3832 | /** |
| 3833 | CPUID Processor Brand String |
| 3834 | |
| 3835 | @param EAX CPUID_BRAND_STRING1 (0x80000002) |
| 3836 | |
| 3837 | @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA. |
| 3838 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3839 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3840 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3841 | |
| 3842 | <b>Example usage</b> |
| 3843 | @code |
| 3844 | CPUID_BRAND_STRING_DATA Eax; |
| 3845 | CPUID_BRAND_STRING_DATA Ebx; |
| 3846 | CPUID_BRAND_STRING_DATA Ecx; |
| 3847 | CPUID_BRAND_STRING_DATA Edx; |
| 3848 | |
| 3849 | AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); |
| 3850 | @endcode |
| 3851 | **/ |
| 3852 | #define CPUID_BRAND_STRING1 0x80000002 |
| 3853 | |
| 3854 | /** |
| 3855 | CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1, |
| 3856 | #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3. |
| 3857 | **/ |
| 3858 | typedef union { |
| 3859 | /// |
| 3860 | /// 4 ASCII characters of Processor Brand String |
| 3861 | /// |
| 3862 | CHAR8 BrandString[4]; |
| 3863 | /// |
| 3864 | /// All fields as a 32-bit value |
| 3865 | /// |
| 3866 | UINT32 Uint32; |
| 3867 | } CPUID_BRAND_STRING_DATA; |
| 3868 | |
| 3869 | /** |
| 3870 | CPUID Processor Brand String |
| 3871 | |
| 3872 | @param EAX CPUID_BRAND_STRING2 (0x80000003) |
| 3873 | |
| 3874 | @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3875 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3876 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3877 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3878 | |
| 3879 | <b>Example usage</b> |
| 3880 | @code |
| 3881 | CPUID_BRAND_STRING_DATA Eax; |
| 3882 | CPUID_BRAND_STRING_DATA Ebx; |
| 3883 | CPUID_BRAND_STRING_DATA Ecx; |
| 3884 | CPUID_BRAND_STRING_DATA Edx; |
| 3885 | |
| 3886 | AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); |
| 3887 | @endcode |
| 3888 | **/ |
| 3889 | #define CPUID_BRAND_STRING2 0x80000003 |
| 3890 | |
| 3891 | /** |
| 3892 | CPUID Processor Brand String |
| 3893 | |
| 3894 | @param EAX CPUID_BRAND_STRING3 (0x80000004) |
| 3895 | |
| 3896 | @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3897 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3898 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3899 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. |
| 3900 | |
| 3901 | <b>Example usage</b> |
| 3902 | @code |
| 3903 | CPUID_BRAND_STRING_DATA Eax; |
| 3904 | CPUID_BRAND_STRING_DATA Ebx; |
| 3905 | CPUID_BRAND_STRING_DATA Ecx; |
| 3906 | CPUID_BRAND_STRING_DATA Edx; |
| 3907 | |
| 3908 | AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); |
| 3909 | @endcode |
| 3910 | **/ |
| 3911 | #define CPUID_BRAND_STRING3 0x80000004 |
| 3912 | |
| 3913 | |
| 3914 | /** |
| 3915 | CPUID Extended Cache information |
| 3916 | |
| 3917 | @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006) |
| 3918 | |
| 3919 | @retval EAX Reserved. |
| 3920 | @retval EBX Reserved. |
| 3921 | @retval ECX Extended cache information described by the type |
| 3922 | CPUID_EXTENDED_CACHE_INFO_ECX. |
| 3923 | @retval EDX Reserved. |
| 3924 | |
| 3925 | <b>Example usage</b> |
| 3926 | @code |
| 3927 | CPUID_EXTENDED_CACHE_INFO_ECX Ecx; |
| 3928 | |
| 3929 | AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL); |
| 3930 | @endcode |
| 3931 | **/ |
| 3932 | #define CPUID_EXTENDED_CACHE_INFO 0x80000006 |
| 3933 | |
| 3934 | /** |
| 3935 | CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO. |
| 3936 | **/ |
| 3937 | typedef union { |
| 3938 | /// |
| 3939 | /// Individual bit fields |
| 3940 | /// |
| 3941 | struct { |
| 3942 | /// |
| 3943 | /// [Bits 7:0] Cache line size in bytes. |
| 3944 | /// |
| 3945 | UINT32 CacheLineSize:8; |
| 3946 | UINT32 Reserved:4; |
| 3947 | /// |
| 3948 | /// [Bits 15:12] L2 Associativity field. Supported values are in the range |
| 3949 | /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to |
| 3950 | /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL |
| 3951 | /// |
| 3952 | UINT32 L2Associativity:4; |
| 3953 | /// |
| 3954 | /// [Bits 31:16] Cache size in 1K units. |
| 3955 | /// |
| 3956 | UINT32 CacheSize:16; |
| 3957 | } Bits; |
| 3958 | /// |
| 3959 | /// All bit fields as a 32-bit value |
| 3960 | /// |
| 3961 | UINT32 Uint32; |
| 3962 | } CPUID_EXTENDED_CACHE_INFO_ECX; |
| 3963 | |
| 3964 | /// |
| 3965 | /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity |
| 3966 | /// |
| 3967 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00 |
| 3968 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01 |
| 3969 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02 |
| 3970 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04 |
| 3971 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06 |
| 3972 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08 |
| 3973 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A |
| 3974 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B |
| 3975 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C |
| 3976 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D |
| 3977 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E |
| 3978 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F |
| 3979 | /// |
| 3980 | /// @} |
| 3981 | /// |
| 3982 | |
| 3983 | /** |
| 3984 | CPUID Extended Time Stamp Counter information |
| 3985 | |
| 3986 | @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007) |
| 3987 | |
| 3988 | @retval EAX Reserved. |
| 3989 | @retval EBX Reserved. |
| 3990 | @retval ECX Reserved. |
| 3991 | @retval EDX Extended time stamp counter (TSC) information described by the |
| 3992 | type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX. |
| 3993 | |
| 3994 | <b>Example usage</b> |
| 3995 | @code |
| 3996 | CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx; |
| 3997 | |
| 3998 | AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32); |
| 3999 | @endcode |
| 4000 | **/ |
| 4001 | #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007 |
| 4002 | |
| 4003 | /** |
| 4004 | CPUID Extended Time Stamp Counter information EDX for CPUID leaf |
| 4005 | #CPUID_EXTENDED_TIME_STAMP_COUNTER. |
| 4006 | **/ |
| 4007 | typedef union { |
| 4008 | /// |
| 4009 | /// Individual bit fields |
| 4010 | /// |
| 4011 | struct { |
| 4012 | UINT32 Reserved1:8; |
| 4013 | /// |
| 4014 | /// [Bit 8] Invariant TSC available if 1. |
| 4015 | /// |
| 4016 | UINT32 InvariantTsc:1; |
| 4017 | UINT32 Reserved2:23; |
| 4018 | } Bits; |
| 4019 | /// |
| 4020 | /// All bit fields as a 32-bit value |
| 4021 | /// |
| 4022 | UINT32 Uint32; |
| 4023 | } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX; |
| 4024 | |
| 4025 | |
| 4026 | /** |
| 4027 | CPUID Linear Physical Address Size |
| 4028 | |
| 4029 | @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) |
| 4030 | |
| 4031 | @retval EAX Linear/Physical Address Size described by the type |
| 4032 | CPUID_VIR_PHY_ADDRESS_SIZE_EAX. |
| 4033 | @retval EBX Reserved. |
| 4034 | @retval ECX Reserved. |
| 4035 | @retval EDX Reserved. |
| 4036 | |
| 4037 | <b>Example usage</b> |
| 4038 | @code |
| 4039 | CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax; |
| 4040 | |
| 4041 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL); |
| 4042 | @endcode |
| 4043 | **/ |
| 4044 | #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008 |
| 4045 | |
| 4046 | /** |
| 4047 | CPUID Linear Physical Address Size EAX for CPUID leaf |
| 4048 | #CPUID_VIR_PHY_ADDRESS_SIZE. |
| 4049 | **/ |
| 4050 | typedef union { |
| 4051 | /// |
| 4052 | /// Individual bit fields |
| 4053 | /// |
| 4054 | struct { |
| 4055 | /// |
| 4056 | /// [Bits 7:0] Number of physical address bits. |
| 4057 | /// |
| 4058 | /// @note |
| 4059 | /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address |
| 4060 | /// number supported should come from this field. |
| 4061 | /// |
| 4062 | UINT32 PhysicalAddressBits:8; |
| 4063 | /// |
| 4064 | /// [Bits 15:8] Number of linear address bits. |
| 4065 | /// |
| 4066 | UINT32 LinearAddressBits:8; |
| 4067 | UINT32 Reserved:16; |
| 4068 | } Bits; |
| 4069 | /// |
| 4070 | /// All bit fields as a 32-bit value |
| 4071 | /// |
| 4072 | UINT32 Uint32; |
| 4073 | } CPUID_VIR_PHY_ADDRESS_SIZE_EAX; |
| 4074 | |
| 4075 | #endif |