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review.coreboot.org / coreboot / f6ae1a908034ad4320efba9742fbc505b993c347 / . / src / vendorcode / intel / edk2 / edk2-stable202111 / MdePkg / Include / IndustryStandard / Nvme.h
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Subrata Banik20fe24b2021-12-09 02:46:38 +0530[diff] [blame]1/** @file
2 Definitions based on NVMe spec. version 1.1.
3
4 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
5 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 @par Specification Reference:
9 NVMe Specification 1.1
10
11**/
12
13#ifndef __NVM_E_H__
14#define __NVM_E_H__
15
16#pragma pack(1)
17
18//
19// controller register offsets
20//
21#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
22#define NVME_VER_OFFSET 0x0008 // Version
23#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
24#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
25#define NVME_CC_OFFSET 0x0014 // Controller Configuration
26#define NVME_CSTS_OFFSET 0x001c // Controller Status
27#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
28#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
29#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
30#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
31#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
32#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
33
34//
35// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
36// Get the doorbell stride bit shift value from the controller capabilities.
37//
38#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
39#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
40
41
42#pragma pack(1)
43
44//
45// 3.1.1 Offset 00h: CAP - Controller Capabilities
46//
47typedef struct {
48 UINT16 Mqes; // Maximum Queue Entries Supported
49 UINT8 Cqr:1; // Contiguous Queues Required
50 UINT8 Ams:2; // Arbitration Mechanism Supported
51 UINT8 Rsvd1:5;
52 UINT8 To; // Timeout
53 UINT16 Dstrd:4;
54 UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS
55 UINT16 Css:4; // Command Sets Supported - Bit 37
56 UINT16 Rsvd3:7;
57 UINT8 Mpsmin:4;
58 UINT8 Mpsmax:4;
59 UINT8 Rsvd4;
60} NVME_CAP;
61
62//
63// 3.1.2 Offset 08h: VS - Version
64//
65typedef struct {
66 UINT16 Mnr; // Minor version number
67 UINT16 Mjr; // Major version number
68} NVME_VER;
69
70//
71// 3.1.5 Offset 14h: CC - Controller Configuration
72//
73typedef struct {
74 UINT16 En:1; // Enable
75 UINT16 Rsvd1:3;
76 UINT16 Css:3; // I/O Command Set Selected
77 UINT16 Mps:4; // Memory Page Size
78 UINT16 Ams:3; // Arbitration Mechanism Selected
79 UINT16 Shn:2; // Shutdown Notification
80 UINT8 Iosqes:4; // I/O Submission Queue Entry Size
81 UINT8 Iocqes:4; // I/O Completion Queue Entry Size
82 UINT8 Rsvd2;
83} NVME_CC;
84#define NVME_CC_SHN_NORMAL_SHUTDOWN 1
85#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
86
87//
88// 3.1.6 Offset 1Ch: CSTS - Controller Status
89//
90typedef struct {
91 UINT32 Rdy:1; // Ready
92 UINT32 Cfs:1; // Controller Fatal Status
93 UINT32 Shst:2; // Shutdown Status
94 UINT32 Nssro:1; // NVM Subsystem Reset Occurred
95 UINT32 Rsvd1:27;
96} NVME_CSTS;
97#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
98#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
99//
100// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
101//
102typedef struct {
103 UINT16 Asqs:12; // Submission Queue Size
104 UINT16 Rsvd1:4;
105 UINT16 Acqs:12; // Completion Queue Size
106 UINT16 Rsvd2:4;
107} NVME_AQA;
108
109//
110// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
111//
112#define NVME_ASQ UINT64
113//
114// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
115//
116#define NVME_ACQ UINT64
117
118//
119// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
120//
121typedef struct {
122 UINT16 Sqt;
123 UINT16 Rsvd1;
124} NVME_SQTDBL;
125
126//
127// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
128//
129typedef struct {
130 UINT16 Cqh;
131 UINT16 Rsvd1;
132} NVME_CQHDBL;
133
134//
135// NVM command set structures
136//
137// Read Command
138//
139typedef struct {
140 //
141 // CDW 10, 11
142 //
143 UINT64 Slba; /* Starting Sector Address */
144 //
145 // CDW 12
146 //
147 UINT16 Nlb; /* Number of Sectors */
148 UINT16 Rsvd1:10;
149 UINT16 Prinfo:4; /* Protection Info Check */
150 UINT16 Fua:1; /* Force Unit Access */
151 UINT16 Lr:1; /* Limited Retry */
152 //
153 // CDW 13
154 //
155 UINT32 Af:4; /* Access Frequency */
156 UINT32 Al:2; /* Access Latency */
157 UINT32 Sr:1; /* Sequential Request */
158 UINT32 In:1; /* Incompressible */
159 UINT32 Rsvd2:24;
160 //
161 // CDW 14
162 //
163 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
164 //
165 // CDW 15
166 //
167 UINT16 Elbat; /* Expected Logical Block Application Tag */
168 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
169} NVME_READ;
170
171//
172// Write Command
173//
174typedef struct {
175 //
176 // CDW 10, 11
177 //
178 UINT64 Slba; /* Starting Sector Address */
179 //
180 // CDW 12
181 //
182 UINT16 Nlb; /* Number of Sectors */
183 UINT16 Rsvd1:10;
184 UINT16 Prinfo:4; /* Protection Info Check */
185 UINT16 Fua:1; /* Force Unit Access */
186 UINT16 Lr:1; /* Limited Retry */
187 //
188 // CDW 13
189 //
190 UINT32 Af:4; /* Access Frequency */
191 UINT32 Al:2; /* Access Latency */
192 UINT32 Sr:1; /* Sequential Request */
193 UINT32 In:1; /* Incompressible */
194 UINT32 Rsvd2:24;
195 //
196 // CDW 14
197 //
198 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
199 //
200 // CDW 15
201 //
202 UINT16 Lbat; /* Logical Block Application Tag */
203 UINT16 Lbatm; /* Logical Block Application Tag Mask */
204} NVME_WRITE;
205
206//
207// Flush
208//
209typedef struct {
210 //
211 // CDW 10
212 //
213 UINT32 Flush; /* Flush */
214} NVME_FLUSH;
215
216//
217// Write Uncorrectable command
218//
219typedef struct {
220 //
221 // CDW 10, 11
222 //
223 UINT64 Slba; /* Starting LBA */
224 //
225 // CDW 12
226 //
227 UINT32 Nlb:16; /* Number of Logical Blocks */
228 UINT32 Rsvd1:16;
229} NVME_WRITE_UNCORRECTABLE;
230
231//
232// Write Zeroes command
233//
234typedef struct {
235 //
236 // CDW 10, 11
237 //
238 UINT64 Slba; /* Starting LBA */
239 //
240 // CDW 12
241 //
242 UINT16 Nlb; /* Number of Logical Blocks */
243 UINT16 Rsvd1:10;
244 UINT16 Prinfo:4; /* Protection Info Check */
245 UINT16 Fua:1; /* Force Unit Access */
246 UINT16 Lr:1; /* Limited Retry */
247 //
248 // CDW 13
249 //
250 UINT32 Rsvd2;
251 //
252 // CDW 14
253 //
254 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
255 //
256 // CDW 15
257 //
258 UINT16 Lbat; /* Logical Block Application Tag */
259 UINT16 Lbatm; /* Logical Block Application Tag Mask */
260} NVME_WRITE_ZEROES;
261
262//
263// Compare command
264//
265typedef struct {
266 //
267 // CDW 10, 11
268 //
269 UINT64 Slba; /* Starting LBA */
270 //
271 // CDW 12
272 //
273 UINT16 Nlb; /* Number of Logical Blocks */
274 UINT16 Rsvd1:10;
275 UINT16 Prinfo:4; /* Protection Info Check */
276 UINT16 Fua:1; /* Force Unit Access */
277 UINT16 Lr:1; /* Limited Retry */
278 //
279 // CDW 13
280 //
281 UINT32 Rsvd2;
282 //
283 // CDW 14
284 //
285 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
286 //
287 // CDW 15
288 //
289 UINT16 Elbat; /* Expected Logical Block Application Tag */
290 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
291} NVME_COMPARE;
292
293typedef union {
294 NVME_READ Read;
295 NVME_WRITE Write;
296 NVME_FLUSH Flush;
297 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
298 NVME_WRITE_ZEROES WriteZeros;
299 NVME_COMPARE Compare;
300} NVME_CMD;
301
302typedef struct {
303 UINT16 Mp; /* Maximum Power */
304 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
305 UINT8 Mps:1; /* Max Power Scale */
306 UINT8 Nops:1; /* Non-Operational State */
307 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */
308 UINT32 Enlat; /* Entry Latency */
309 UINT32 Exlat; /* Exit Latency */
310 UINT8 Rrt:5; /* Relative Read Throughput */
311 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
312 UINT8 Rrl:5; /* Relative Read Latency */
313 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
314 UINT8 Rwt:5; /* Relative Write Throughput */
315 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
316 UINT8 Rwl:5; /* Relative Write Latency */
317 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
318 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
319} NVME_PSDESCRIPTOR;
320
321//
322// Identify Controller Data
323//
324typedef struct {
325 //
326 // Controller Capabilities and Features 0-255
327 //
328 UINT16 Vid; /* PCI Vendor ID */
329 UINT16 Ssvid; /* PCI sub-system vendor ID */
330 UINT8 Sn[20]; /* Product serial number */
331
332 UINT8 Mn[40]; /* Product model number */
333 UINT8 Fr[8]; /* Firmware Revision */
334 UINT8 Rab; /* Recommended Arbitration Burst */
335 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
336 UINT8 Cmic; /* Multi-interface Capabilities */
337 UINT8 Mdts; /* Maximum Data Transfer Size */
338 UINT8 Cntlid[2]; /* Controller ID */
339 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
340 //
341 // Admin Command Set Attributes
342 //
343 UINT16 Oacs; /* Optional Admin Command Support */
344 #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
345 #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
346 #define FORMAT_NVM_SUPPORTED BIT1
347 #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
348 UINT8 Acl; /* Abort Command Limit */
349 UINT8 Aerl; /* Async Event Request Limit */
350 UINT8 Frmw; /* Firmware updates */
351 UINT8 Lpa; /* Log Page Attributes */
352 UINT8 Elpe; /* Error Log Page Entries */
353 UINT8 Npss; /* Number of Power States Support */
354 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
355 UINT8 Apsta; /* Autonomous Power State Transition Attributes */
356 //
357 // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec
358 //
359 UINT16 Wctemp; /* Warning Composite Temperature Threshold */
360 UINT16 Cctemp; /* Critical Composite Temperature Threshold */
361 UINT16 Mtfa; /* Maximum Time for Firmware Activation */
362 UINT32 Hmpre; /* Host Memory Buffer Preferred Size */
363 UINT32 Hmmin; /* Host Memory Buffer Minimum Size */
364 UINT8 Tnvmcap[16]; /* Total NVM Capacity */
365 UINT8 Rsvd2[216]; /* Reserved as of NVM Express */
366 //
367 // NVM Command Set Attributes
368 //
369 UINT8 Sqes; /* Submission Queue Entry Size */
370 UINT8 Cqes; /* Completion Queue Entry Size */
371 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
372 UINT32 Nn; /* Number of Namespaces */
373 UINT16 Oncs; /* Optional NVM Command Support */
374 UINT16 Fuses; /* Fused Operation Support */
375 UINT8 Fna; /* Format NVM Attributes */
376 UINT8 Vwc; /* Volatile Write Cache */
377 UINT16 Awun; /* Atomic Write Unit Normal */
378 UINT16 Awupf; /* Atomic Write Unit Power Fail */
379 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
380 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
381 UINT16 Acwu; /* Atomic Compare & Write Unit */
382 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
383 UINT32 Sgls; /* SGL Support */
384 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
385 //
386 // I/O Command set Attributes
387 //
388 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
389 //
390 // Power State Descriptors
391 //
392 NVME_PSDESCRIPTOR PsDescriptor[32];
393
394 UINT8 VendorData[1024]; /* Vendor specific data */
395} NVME_ADMIN_CONTROLLER_DATA;
396
397typedef struct {
398 UINT16 Ms; /* Metadata Size */
399 UINT8 Lbads; /* LBA Data Size */
400 UINT8 Rp:2; /* Relative Performance */
401 #define LBAF_RP_BEST 00b
402 #define LBAF_RP_BETTER 01b
403 #define LBAF_RP_GOOD 10b
404 #define LBAF_RP_DEGRADED 11b
405 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */
406} NVME_LBAFORMAT;
407
408//
409// Identify Namespace Data
410//
411typedef struct {
412 //
413 // NVM Command Set Specific
414 //
415 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
416 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
417 UINT64 Nuse; /* Namespace Utilization */
418 UINT8 Nsfeat; /* Namespace Features */
419 UINT8 Nlbaf; /* Number of LBA Formats */
420 UINT8 Flbas; /* Formatted LBA size */
421 UINT8 Mc; /* Metadata Capabilities */
422 UINT8 Dpc; /* End-to-end Data Protection capabilities */
423 UINT8 Dps; /* End-to-end Data Protection Type Settings */
424 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
425 UINT8 Rescap; /* Reservation Capabilities */
426 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
427 UINT64 Eui64; /* IEEE Extended Unique Identifier */
428 //
429 // LBA Format
430 //
431 NVME_LBAFORMAT LbaFormat[16];
432
433 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
434 UINT8 VendorData[3712]; /* Vendor specific data */
435} NVME_ADMIN_NAMESPACE_DATA;
436
437//
438// NvmExpress Admin Identify Cmd
439//
440typedef struct {
441 //
442 // CDW 10
443 //
444 UINT32 Cns:2;
445 UINT32 Rsvd1:30;
446} NVME_ADMIN_IDENTIFY;
447
448//
449// NvmExpress Admin Create I/O Completion Queue
450//
451typedef struct {
452 //
453 // CDW 10
454 //
455 UINT32 Qid:16; /* Queue Identifier */
456 UINT32 Qsize:16; /* Queue Size */
457
458 //
459 // CDW 11
460 //
461 UINT32 Pc:1; /* Physically Contiguous */
462 UINT32 Ien:1; /* Interrupts Enabled */
463 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */
464 UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/
465} NVME_ADMIN_CRIOCQ;
466
467//
468// NvmExpress Admin Create I/O Submission Queue
469//
470typedef struct {
471 //
472 // CDW 10
473 //
474 UINT32 Qid:16; /* Queue Identifier */
475 UINT32 Qsize:16; /* Queue Size */
476
477 //
478 // CDW 11
479 //
480 UINT32 Pc:1; /* Physically Contiguous */
481 UINT32 Qprio:2; /* Queue Priority */
482 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */
483 UINT32 Cqid:16; /* Completion Queue ID */
484} NVME_ADMIN_CRIOSQ;
485
486//
487// NvmExpress Admin Delete I/O Completion Queue
488//
489typedef struct {
490 //
491 // CDW 10
492 //
493 UINT16 Qid;
494 UINT16 Rsvd1;
495} NVME_ADMIN_DEIOCQ;
496
497//
498// NvmExpress Admin Delete I/O Submission Queue
499//
500typedef struct {
501 //
502 // CDW 10
503 //
504 UINT16 Qid;
505 UINT16 Rsvd1;
506} NVME_ADMIN_DEIOSQ;
507
508//
509// NvmExpress Admin Abort Command
510//
511typedef struct {
512 //
513 // CDW 10
514 //
515 UINT32 Sqid:16; /* Submission Queue identifier */
516 UINT32 Cid:16; /* Command Identifier */
517} NVME_ADMIN_ABORT;
518
519//
520// NvmExpress Admin Firmware Activate Command
521//
522typedef struct {
523 //
524 // CDW 10
525 //
526 UINT32 Fs:3; /* Submission Queue identifier */
527 UINT32 Aa:2; /* Command Identifier */
528 UINT32 Rsvd1:27;
529} NVME_ADMIN_FIRMWARE_ACTIVATE;
530
531//
532// NvmExpress Admin Firmware Image Download Command
533//
534typedef struct {
535 //
536 // CDW 10
537 //
538 UINT32 Numd; /* Number of Dwords */
539 //
540 // CDW 11
541 //
542 UINT32 Ofst; /* Offset */
543} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
544
545//
546// NvmExpress Admin Get Features Command
547//
548typedef struct {
549 //
550 // CDW 10
551 //
552 UINT32 Fid:8; /* Feature Identifier */
553 UINT32 Sel:3; /* Select */
554 UINT32 Rsvd1:21;
555} NVME_ADMIN_GET_FEATURES;
556
557//
558// NvmExpress Admin Get Log Page Command
559//
560typedef struct {
561 //
562 // CDW 10
563 //
564 UINT32 Lid:8; /* Log Page Identifier */
565 #define LID_ERROR_INFO 0x1
566 #define LID_SMART_INFO 0x2
567 #define LID_FW_SLOT_INFO 0x3
568 UINT32 Rsvd1:8;
569 UINT32 Numd:12; /* Number of Dwords */
570 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */
571} NVME_ADMIN_GET_LOG_PAGE;
572
573//
574// NvmExpress Admin Set Features Command
575//
576typedef struct {
577 //
578 // CDW 10
579 //
580 UINT32 Fid:8; /* Feature Identifier */
581 UINT32 Rsvd1:23;
582 UINT32 Sv:1; /* Save */
583} NVME_ADMIN_SET_FEATURES;
584
585//
586// NvmExpress Admin Format NVM Command
587//
588typedef struct {
589 //
590 // CDW 10
591 //
592 UINT32 Lbaf:4; /* LBA Format */
593 UINT32 Ms:1; /* Metadata Settings */
594 UINT32 Pi:3; /* Protection Information */
595 UINT32 Pil:1; /* Protection Information Location */
596 UINT32 Ses:3; /* Secure Erase Settings */
597 UINT32 Rsvd1:20;
598} NVME_ADMIN_FORMAT_NVM;
599
600//
601// NvmExpress Admin Security Receive Command
602//
603typedef struct {
604 //
605 // CDW 10
606 //
607 UINT32 Rsvd1:8;
608 UINT32 Spsp:16; /* SP Specific */
609 UINT32 Secp:8; /* Security Protocol */
610 //
611 // CDW 11
612 //
613 UINT32 Al; /* Allocation Length */
614} NVME_ADMIN_SECURITY_RECEIVE;
615
616//
617// NvmExpress Admin Security Send Command
618//
619typedef struct {
620 //
621 // CDW 10
622 //
623 UINT32 Rsvd1:8;
624 UINT32 Spsp:16; /* SP Specific */
625 UINT32 Secp:8; /* Security Protocol */
626 //
627 // CDW 11
628 //
629 UINT32 Tl; /* Transfer Length */
630} NVME_ADMIN_SECURITY_SEND;
631
632typedef union {
633 NVME_ADMIN_IDENTIFY Identify;
634 NVME_ADMIN_CRIOCQ CrIoCq;
635 NVME_ADMIN_CRIOSQ CrIoSq;
636 NVME_ADMIN_DEIOCQ DeIoCq;
637 NVME_ADMIN_DEIOSQ DeIoSq;
638 NVME_ADMIN_ABORT Abort;
639 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
640 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
641 NVME_ADMIN_GET_FEATURES GetFeatures;
642 NVME_ADMIN_GET_LOG_PAGE GetLogPage;
643 NVME_ADMIN_SET_FEATURES SetFeatures;
644 NVME_ADMIN_FORMAT_NVM FormatNvm;
645 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
646 NVME_ADMIN_SECURITY_SEND SecuritySend;
647} NVME_ADMIN_CMD;
648
649typedef struct {
650 UINT32 Cdw10;
651 UINT32 Cdw11;
652 UINT32 Cdw12;
653 UINT32 Cdw13;
654 UINT32 Cdw14;
655 UINT32 Cdw15;
656} NVME_RAW;
657
658typedef union {
659 NVME_ADMIN_CMD Admin; // Union of Admin commands
660 NVME_CMD Nvm; // Union of Nvm commands
661 NVME_RAW Raw;
662} NVME_PAYLOAD;
663
664//
665// Submission Queue
666//
667typedef struct {
668 //
669 // CDW 0, Common to all commands
670 //
671 UINT8 Opc; // Opcode
672 UINT8 Fuse:2; // Fused Operation
673 UINT8 Rsvd1:5;
674 UINT8 Psdt:1; // PRP or SGL for Data Transfer
675 UINT16 Cid; // Command Identifier
676
677 //
678 // CDW 1
679 //
680 UINT32 Nsid; // Namespace Identifier
681
682 //
683 // CDW 2,3
684 //
685 UINT64 Rsvd2;
686
687 //
688 // CDW 4,5
689 //
690 UINT64 Mptr; // Metadata Pointer
691
692 //
693 // CDW 6-9
694 //
695 UINT64 Prp[2]; // First and second PRP entries
696
697 NVME_PAYLOAD Payload;
698
699} NVME_SQ;
700
701//
702// Completion Queue
703//
704typedef struct {
705 //
706 // CDW 0
707 //
708 UINT32 Dword0;
709 //
710 // CDW 1
711 //
712 UINT32 Rsvd1;
713 //
714 // CDW 2
715 //
716 UINT16 Sqhd; // Submission Queue Head Pointer
717 UINT16 Sqid; // Submission Queue Identifier
718 //
719 // CDW 3
720 //
721 UINT16 Cid; // Command Identifier
722 UINT16 Pt:1; // Phase Tag
723 UINT16 Sc:8; // Status Code
724 UINT16 Sct:3; // Status Code Type
725 UINT16 Rsvd2:2;
726 UINT16 Mo:1; // More
727 UINT16 Dnr:1; // Do Not Retry
728} NVME_CQ;
729
730//
731// Nvm Express Admin cmd opcodes
732//
733#define NVME_ADMIN_DEIOSQ_CMD 0x00
734#define NVME_ADMIN_CRIOSQ_CMD 0x01
735#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
736#define NVME_ADMIN_DEIOCQ_CMD 0x04
737#define NVME_ADMIN_CRIOCQ_CMD 0x05
738#define NVME_ADMIN_IDENTIFY_CMD 0x06
739#define NVME_ADMIN_ABORT_CMD 0x08
740#define NVME_ADMIN_SET_FEATURES_CMD 0x09
741#define NVME_ADMIN_GET_FEATURES_CMD 0x0A
742#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
743#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
744#define NVME_ADMIN_FW_COMMIT_CMD 0x10
745#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
746#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
747#define NVME_ADMIN_FORMAT_NVM_CMD 0x80
748#define NVME_ADMIN_SECURITY_SEND_CMD 0x81
749#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
750
751#define NVME_IO_FLUSH_OPC 0
752#define NVME_IO_WRITE_OPC 1
753#define NVME_IO_READ_OPC 2
754
755typedef enum {
756 DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
757 CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
758 GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
759 DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
760 CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
761 IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
762 AbortOpcode = NVME_ADMIN_ABORT_CMD,
763 SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
764 GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
765 AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
766 NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
767 FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
768 FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
769 NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
770 FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
771 SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
772 SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
773} NVME_ADMIN_COMMAND_OPCODE;
774
775//
776// Controller or Namespace Structure (CNS) field
777// (ref. spec. v1.1 figure 82).
778//
779typedef enum {
780IdentifyNamespaceCns = 0x0,
781IdentifyControllerCns = 0x1,
782IdentifyActiveNsListCns = 0x2
783} NVME_ADMIN_IDENTIFY_CNS;
784
785//
786// Commit Action
787// (ref. spec. 1.1 figure 60).
788//
789typedef enum {
790 ActivateActionReplace = 0x0,
791 ActivateActionReplaceActivate = 0x1,
792 ActivateActionActivate = 0x2
793} NVME_FW_ACTIVATE_ACTION;
794
795//
796// Firmware Slot
797// (ref. spec. 1.1 Figure 60).
798//
799typedef enum {
800 FirmwareSlotCtrlChooses = 0x0,
801 FirmwareSlot1 = 0x1,
802 FirmwareSlot2 = 0x2,
803 FirmwareSlot3 = 0x3,
804 FirmwareSlot4 = 0x4,
805 FirmwareSlot5 = 0x5,
806 FirmwareSlot6 = 0x6,
807 FirmwareSlot7 = 0x7
808} NVME_FW_ACTIVATE_SLOT;
809
810//
811// Get Log Page ? Log Page Identifiers
812// (ref. spec. v1.1 Figure 73).
813//
814typedef enum {
815 ErrorInfoLogID = LID_ERROR_INFO,
816 SmartHealthInfoLogID = LID_SMART_INFO,
817 FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
818} NVME_LOG_ID;
819
820//
821// Get Log Page ? Firmware Slot Information Log
822// (ref. spec. v1.1 Figure 77).
823//
824typedef struct {
825 //
826 // Indicates the firmware slot from which the actively running firmware revision was loaded.
827 //
828 UINT8 ActivelyRunningFwSlot:3;
829 UINT8 :1;
830 //
831 // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
832 //
833 UINT8 NextActiveFwSlot:3;
834 UINT8 :1;
835} NVME_ACTIVE_FW_INFO;
836
837//
838// Get Log Page ? Firmware Slot Information Log
839// (ref. spec. v1.1 Figure 77).
840//
841typedef struct {
842 //
843 // Specifies information about the active firmware revision.
844 //s
845 NVME_ACTIVE_FW_INFO ActiveFwInfo;
846 UINT8 Reserved1[7];
847 //
848 // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
849 //
850 CHAR8 FwRevisionSlot[7][8];
851 UINT8 Reserved2[448];
852} NVME_FW_SLOT_INFO_LOG;
853
854//
855// SMART / Health Information (Log Identifier 02h)
856// (ref. spec. v1.1 5.10.1.2)
857//
858typedef struct {
859 //
860 // This field indicates critical warnings for the state of the controller.
861 //
862 UINT8 CriticalWarningAvailableSpare:1;
863 UINT8 CriticalWarningTemperature:1;
864 UINT8 CriticalWarningReliability:1;
865 UINT8 CriticalWarningMediaReadOnly:1;
866 UINT8 CriticalWarningVolatileBackup:1;
867 UINT8 CriticalWarningReserved:3;
868 //
869 // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
870 //
871 UINT16 CompositeTemp;
872 //
873 // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
874 //
875 UINT8 AvailableSpare;
876 //
877 // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
878 //
879 UINT8 AvailableSpareThreshold;
880 //
881 // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
882 //
883 UINT8 PercentageUsed;
884 UINT8 Reserved1[26];
885 //
886 // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
887 //
888 UINT8 DataUnitsRead[16];
889 //
890 // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
891 //
892 UINT8 DataUnitsWritten[16];
893 //
894 // Contains the number of read commands completed by the controller.
895 //
896 UINT8 HostReadCommands[16];
897 //
898 // Contains the number of write commands completed by the controller.
899 //
900 UINT8 HostWriteCommands[16];
901 //
902 // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
903 //
904 UINT8 ControllerBusyTime[16];
905 //
906 // Contains the number of power cycles.
907 //
908 UINT8 PowerCycles[16];
909 //
910 // Contains the number of power-on hours.
911 //
912 UINT8 PowerOnHours[16];
913 //
914 // Contains the number of unsafe shutdowns.
915 //
916 UINT8 UnsafeShutdowns[16];
917 //
918 // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
919 //
920 UINT8 MediaAndDataIntegrityErrors[16];
921 //
922 // Contains the number of Error Information log entries over the life of the controller.
923 //
924 UINT8 NumberErrorInformationLogEntries[16];
925 //
926 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
927 //
928 UINT32 WarningCompositeTemperatureTime;
929 //
930 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
931 //
932 UINT32 CriticalCompositeTemperatureTime;
933 //
934 // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
935 //
936 UINT16 TemperatureSensor[8];
937 UINT8 Reserved2[296];
938} NVME_SMART_HEALTH_INFO_LOG;
939
940#pragma pack()
941
942#endif