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review.coreboot.org / coreboot / f6ae1a908034ad4320efba9742fbc505b993c347 / . / src / vendorcode / intel / edk2 / edk2-stable202111 / MdePkg / Include / IndustryStandard / Cxl11.h
blob: c3d88d3816904f12b1a126145327842e73933bb8 [file] [log] [blame]
Subrata Banik20fe24b2021-12-09 02:46:38 +0530[diff] [blame]1/** @file
2 CXL 1.1 Register definitions
3
4 This file contains the register definitions based on the Compute Express Link
5 (CXL) Specification Revision 1.1.
6
7Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
8SPDX-License-Identifier: BSD-2-Clause-Patent
9
10**/
11
12#ifndef _CXL11_H_
13#define _CXL11_H_
14
15#include <IndustryStandard/Pci.h>
16//
17// DVSEC Vendor ID
18// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58
19// (subject to change as per CXL assigned Vendor ID)
20//
21#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086
22
23//
24// CXL Flex Bus Device default device and function number
25// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1
26//
27#define CXL_DEV_DEV 0
28#define CXL_DEV_FUNC 0
29
30//
31// Ensure proper structure formats
32//
33#pragma pack(1)
34
35/**
36 Macro used to verify the size of a data type at compile time and trigger a
37 STATIC_ASSERT() with an error message if the size of the data type does not
38 match the expected size.
39
40 @param TypeName Type name of data type to verify.
41 @param ExpectedSize The expected size, in bytes, of the data type specified
42 by TypeName.
43**/
44#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \
45 STATIC_ASSERT ( \
46 sizeof (TypeName) == ExpectedSize, \
47 "Size of " #TypeName \
48 " does not meet CXL 1.1 Specification requirements." \
49 )
50
51/**
52 Macro used to verify the offset of a field in a data type at compile time and
53 trigger a STATIC_ASSERT() with an error message if the offset of the field in
54 the data type does not match the expected offset.
55
56 @param TypeName Type name of data type to verify.
57 @param FieldName Field name in the data type specified by TypeName to
58 verify.
59 @param ExpectedOffset The expected offset, in bytes, of the field specified
60 by TypeName and FieldName.
61**/
62#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \
63 STATIC_ASSERT ( \
64 OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \
65 "Offset of " #TypeName "." #FieldName \
66 " does not meet CXL 1.1 Specification requirements." \
67 )
68
69///
70/// The PCIe DVSEC for Flex Bus Device
71///@{
72typedef union {
73 struct {
74 UINT16 CacheCapable : 1; // bit 0
75 UINT16 IoCapable : 1; // bit 1
76 UINT16 MemCapable : 1; // bit 2
77 UINT16 MemHwInitMode : 1; // bit 3
78 UINT16 HdmCount : 2; // bit 4..5
79 UINT16 Reserved1 : 8; // bit 6..13
80 UINT16 ViralCapable : 1; // bit 14
81 UINT16 Reserved2 : 1; // bit 15
82 } Bits;
83 UINT16 Uint16;
84} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;
85
86typedef union {
87 struct {
88 UINT16 CacheEnable : 1; // bit 0
89 UINT16 IoEnable : 1; // bit 1
90 UINT16 MemEnable : 1; // bit 2
91 UINT16 CacheSfCoverage : 5; // bit 3..7
92 UINT16 CacheSfGranularity : 3; // bit 8..10
93 UINT16 CacheCleanEviction : 1; // bit 11
94 UINT16 Reserved1 : 2; // bit 12..13
95 UINT16 ViralEnable : 1; // bit 14
96 UINT16 Reserved2 : 1; // bit 15
97 } Bits;
98 UINT16 Uint16;
99} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;
100
101typedef union {
102 struct {
103 UINT16 Reserved1 : 14; // bit 0..13
104 UINT16 ViralStatus : 1; // bit 14
105 UINT16 Reserved2 : 1; // bit 15
106 } Bits;
107 UINT16 Uint16;
108} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;
109
110typedef union {
111 struct {
112 UINT16 Reserved1 : 1; // bit 0
113 UINT16 Reserved2 : 1; // bit 1
114 UINT16 Reserved3 : 1; // bit 2
115 UINT16 Reserved4 : 13; // bit 3..15
116 } Bits;
117 UINT16 Uint16;
118} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;
119
120typedef union {
121 struct {
122 UINT16 Reserved1 : 1; // bit 0
123 UINT16 Reserved2 : 1; // bit 1
124 UINT16 Reserved3 : 14; // bit 2..15
125 } Bits;
126 UINT16 Uint16;
127} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;
128
129typedef union {
130 struct {
131 UINT16 ConfigLock : 1; // bit 0
132 UINT16 Reserved1 : 15; // bit 1..15
133 } Bits;
134 UINT16 Uint16;
135} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;
136
137typedef union {
138 struct {
139 UINT32 MemorySizeHigh : 32; // bit 0..31
140 } Bits;
141 UINT32 Uint32;
142} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;
143
144typedef union {
145 struct {
146 UINT32 MemoryInfoValid : 1; // bit 0
147 UINT32 MemoryActive : 1; // bit 1
148 UINT32 MediaType : 3; // bit 2..4
149 UINT32 MemoryClass : 3; // bit 5..7
150 UINT32 DesiredInterleave : 3; // bit 8..10
151 UINT32 Reserved : 17; // bit 11..27
152 UINT32 MemorySizeLow : 4; // bit 28..31
153 } Bits;
154 UINT32 Uint32;
155} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;
156
157typedef union {
158 struct {
159 UINT32 MemoryBaseHigh : 32; // bit 0..31
160 } Bits;
161 UINT32 Uint32;
162} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;
163
164typedef union {
165 struct {
166 UINT32 Reserved : 28; // bit 0..27
167 UINT32 MemoryBaseLow : 4; // bit 28..31
168 } Bits;
169 UINT32 Uint32;
170} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;
171
172
173typedef union {
174 struct {
175 UINT32 MemorySizeHigh : 32; // bit 0..31
176 } Bits;
177 UINT32 Uint32;
178} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;
179
180typedef union {
181 struct {
182 UINT32 MemoryInfoValid : 1; // bit 0
183 UINT32 MemoryActive : 1; // bit 1
184 UINT32 MediaType : 3; // bit 2..4
185 UINT32 MemoryClass : 3; // bit 5..7
186 UINT32 DesiredInterleave : 3; // bit 8..10
187 UINT32 Reserved : 17; // bit 11..27
188 UINT32 MemorySizeLow : 4; // bit 28..31
189 } Bits;
190 UINT32 Uint32;
191} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;
192
193typedef union {
194 struct {
195 UINT32 MemoryBaseHigh : 32; // bit 0..31
196 } Bits;
197 UINT32 Uint32;
198} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;
199
200typedef union {
201 struct {
202 UINT32 Reserved : 28; // bit 0..27
203 UINT32 MemoryBaseLow : 4; // bit 28..31
204 } Bits;
205 UINT32 Uint32;
206} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;
207
208//
209// Flex Bus Device DVSEC ID
210// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58
211//
212#define FLEX_BUS_DEVICE_DVSEC_ID 0
213
214//
215// PCIe DVSEC for Flex Bus Device
216// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95
217//
218typedef struct {
219 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
220 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
221 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
222 CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10
223 CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12
224 CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14
225 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16
226 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18
227 CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20
228 UINT16 Reserved; // offset 22
229 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24
230 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28
231 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32
232 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36
233 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40
234 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44
235 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48
236 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52
237} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;
238
239CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header , 0x00);
240CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);
241CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);
242CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability , 0x0A);
243CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl , 0x0C);
244CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus , 0x0E);
245CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 , 0x10);
246CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 , 0x12);
247CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock , 0x14);
248CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh , 0x18);
249CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow , 0x1C);
250CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh , 0x20);
251CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow , 0x24);
252CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh , 0x28);
253CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow , 0x2C);
254CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh , 0x30);
255CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow , 0x34);
256CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38);
257///@}
258
259///
260/// PCIe DVSEC for FLex Bus Port
261///@{
262typedef union {
263 struct {
264 UINT16 CacheCapable : 1; // bit 0
265 UINT16 IoCapable : 1; // bit 1
266 UINT16 MemCapable : 1; // bit 2
267 UINT16 Reserved : 13; // bit 3..15
268 } Bits;
269 UINT16 Uint16;
270} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;
271
272typedef union {
273 struct {
274 UINT16 CacheEnable : 1; // bit 0
275 UINT16 IoEnable : 1; // bit 1
276 UINT16 MemEnable : 1; // bit 2
277 UINT16 CxlSyncBypassEnable : 1; // bit 3
278 UINT16 DriftBufferEnable : 1; // bit 4
279 UINT16 Reserved : 3; // bit 5..7
280 UINT16 Retimer1Present : 1; // bit 8
281 UINT16 Retimer2Present : 1; // bit 9
282 UINT16 Reserved2 : 6; // bit 10..15
283 } Bits;
284 UINT16 Uint16;
285} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;
286
287typedef union {
288 struct {
289 UINT16 CacheEnable : 1; // bit 0
290 UINT16 IoEnable : 1; // bit 1
291 UINT16 MemEnable : 1; // bit 2
292 UINT16 CxlSyncBypassEnable : 1; // bit 3
293 UINT16 DriftBufferEnable : 1; // bit 4
294 UINT16 Reserved : 3; // bit 5..7
295 UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8
296 UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9
297 UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10
298 UINT16 Reserved2 : 5; // bit 11..15
299 } Bits;
300 UINT16 Uint16;
301} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;
302
303//
304// Flex Bus Port DVSEC ID
305// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62
306//
307#define FLEX_BUS_PORT_DVSEC_ID 7
308
309//
310// PCIe DVSEC for Flex Bus Port
311// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99
312//
313typedef struct {
314 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
315 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
316 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
317 CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10
318 CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12
319 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14
320} CXL_1_1_DVSEC_FLEX_BUS_PORT;
321
322CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header , 0x00);
323CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);
324CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);
325CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability , 0x0A);
326CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl , 0x0C);
327CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus , 0x0E);
328CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT , 0x10);
329///@}
330
331///
332/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
333///
334
335/// The CXL.Cache and CXL.Memory Architectural register definitions
336/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1
337///@{
338
339#define CXL_CAPABILITY_HEADER_OFFSET 0
340typedef union {
341 struct {
342 UINT32 CxlCapabilityId : 16; // bit 0..15
343 UINT32 CxlCapabilityVersion : 4; // bit 16..19
344 UINT32 CxlCacheMemVersion : 4; // bit 20..23
345 UINT32 ArraySize : 8; // bit 24..31
346 } Bits;
347 UINT32 Uint32;
348} CXL_CAPABILITY_HEADER;
349
350#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4
351typedef union {
352 struct {
353 UINT32 CxlCapabilityId : 16; // bit 0..15
354 UINT32 CxlCapabilityVersion : 4; // bit 16..19
355 UINT32 CxlRasCapabilityPointer : 12; // bit 20..31
356 } Bits;
357 UINT32 Uint32;
358} CXL_RAS_CAPABILITY_HEADER;
359
360#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8
361typedef union {
362 struct {
363 UINT32 CxlCapabilityId : 16; // bit 0..15
364 UINT32 CxlCapabilityVersion : 4; // bit 16..19
365 UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31
366 } Bits;
367 UINT32 Uint32;
368} CXL_SECURITY_CAPABILITY_HEADER;
369
370#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC
371typedef union {
372 struct {
373 UINT32 CxlCapabilityId : 16; // bit 0..15
374 UINT32 CxlCapabilityVersion : 4; // bit 16..19
375 UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31
376 } Bits;
377 UINT32 Uint32;
378} CXL_LINK_CAPABILITY_HEADER;
379
380typedef union {
381 struct {
382 UINT32 CacheDataParity : 1; // bit 0..0
383 UINT32 CacheAddressParity : 1; // bit 1..1
384 UINT32 CacheByteEnableParity : 1; // bit 2..2
385 UINT32 CacheDataEcc : 1; // bit 3..3
386 UINT32 MemDataParity : 1; // bit 4..4
387 UINT32 MemAddressParity : 1; // bit 5..5
388 UINT32 MemByteEnableParity : 1; // bit 6..6
389 UINT32 MemDataEcc : 1; // bit 7..7
390 UINT32 ReInitThreshold : 1; // bit 8..8
391 UINT32 RsvdEncodingViolation : 1; // bit 9..9
392 UINT32 PoisonReceived : 1; // bit 10..10
393 UINT32 ReceiverOverflow : 1; // bit 11..11
394 UINT32 Reserved : 20; // bit 12..31
395 } Bits;
396 UINT32 Uint32;
397} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;
398
399typedef union {
400 struct {
401 UINT32 CacheDataParityMask : 1; // bit 0..0
402 UINT32 CacheAddressParityMask : 1; // bit 1..1
403 UINT32 CacheByteEnableParityMask : 1; // bit 2..2
404 UINT32 CacheDataEccMask : 1; // bit 3..3
405 UINT32 MemDataParityMask : 1; // bit 4..4
406 UINT32 MemAddressParityMask : 1; // bit 5..5
407 UINT32 MemByteEnableParityMask : 1; // bit 6..6
408 UINT32 MemDataEccMask : 1; // bit 7..7
409 UINT32 ReInitThresholdMask : 1; // bit 8..8
410 UINT32 RsvdEncodingViolationMask : 1; // bit 9..9
411 UINT32 PoisonReceivedMask : 1; // bit 10..10
412 UINT32 ReceiverOverflowMask : 1; // bit 11..11
413 UINT32 Reserved : 20; // bit 12..31
414 } Bits;
415 UINT32 Uint32;
416} CXL_1_1_UNCORRECTABLE_ERROR_MASK;
417
418typedef union {
419 struct {
420 UINT32 CacheDataParitySeverity : 1; // bit 0..0
421 UINT32 CacheAddressParitySeverity : 1; // bit 1..1
422 UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2
423 UINT32 CacheDataEccSeverity : 1; // bit 3..3
424 UINT32 MemDataParitySeverity : 1; // bit 4..4
425 UINT32 MemAddressParitySeverity : 1; // bit 5..5
426 UINT32 MemByteEnableParitySeverity : 1; // bit 6..6
427 UINT32 MemDataEccSeverity : 1; // bit 7..7
428 UINT32 ReInitThresholdSeverity : 1; // bit 8..8
429 UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9
430 UINT32 PoisonReceivedSeverity : 1; // bit 10..10
431 UINT32 ReceiverOverflowSeverity : 1; // bit 11..11
432 UINT32 Reserved : 20; // bit 12..31
433 } Bits;
434 UINT32 Uint32;
435} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;
436
437typedef union {
438 struct {
439 UINT32 CacheDataEcc : 1; // bit 0..0
440 UINT32 MemoryDataEcc : 1; // bit 1..1
441 UINT32 CrcThreshold : 1; // bit 2..2
442 UINT32 RetryThreshold : 1; // bit 3..3
443 UINT32 CachePoisonReceived : 1; // bit 4..4
444 UINT32 MemoryPoisonReceived : 1; // bit 5..5
445 UINT32 PhysicalLayerError : 1; // bit 6..6
446 UINT32 Reserved : 25; // bit 7..31
447 } Bits;
448 UINT32 Uint32;
449} CXL_CORRECTABLE_ERROR_STATUS;
450
451typedef union {
452 struct {
453 UINT32 CacheDataEccMask : 1; // bit 0..0
454 UINT32 MemoryDataEccMask : 1; // bit 1..1
455 UINT32 CrcThresholdMask : 1; // bit 2..2
456 UINT32 RetryThresholdMask : 1; // bit 3..3
457 UINT32 CachePoisonReceivedMask : 1; // bit 4..4
458 UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5
459 UINT32 PhysicalLayerErrorMask : 1; // bit 6..6
460 UINT32 Reserved : 25; // bit 7..31
461 } Bits;
462 UINT32 Uint32;
463} CXL_CORRECTABLE_ERROR_MASK;
464
465typedef union {
466 struct {
467 UINT32 FirstErrorPointer : 4; // bit 0..3
468 UINT32 Reserved1 : 5; // bit 4..8
469 UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9
470 UINT32 Reserved2 : 3; // bit 10..12
471 UINT32 PoisonEnabled : 1; // bit 13..13
472 UINT32 Reserved3 : 18; // bit 14..31
473 } Bits;
474 UINT32 Uint32;
475} CXL_ERROR_CAPABILITIES_AND_CONTROL;
476
477typedef struct {
478 CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;
479 CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;
480 CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;
481 CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;
482 CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;
483 CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;
484 UINT32 HeaderLog[16];
485} CXL_1_1_RAS_CAPABILITY_STRUCTURE;
486
487CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus , 0x00);
488CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask , 0x04);
489CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity , 0x08);
490CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus , 0x0C);
491CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask , 0x10);
492CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);
493CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog , 0x18);
494CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58);
495
496typedef union {
497 struct {
498 UINT32 DeviceTrustLevel : 2; // bit 0..1
499 UINT32 Reserved : 30; // bit 2..31
500 } Bits;
501 UINT32 Uint32;
502} CXL_1_1_SECURITY_POLICY;
503
504typedef struct {
505 CXL_1_1_SECURITY_POLICY SecurityPolicy;
506} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;
507
508CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);
509CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);
510
511typedef union {
512 struct {
513 UINT64 CxlLinkVersionSupported : 4; // bit 0..3
514 UINT64 CxlLinkVersionReceived : 4; // bit 4..7
515 UINT64 LlrWrapValueSupported : 8; // bit 8..15
516 UINT64 LlrWrapValueReceived : 8; // bit 16..23
517 UINT64 NumRetryReceived : 5; // bit 24..28
518 UINT64 NumPhyReinitReceived : 5; // bit 29..33
519 UINT64 WrPtrReceived : 8; // bit 34..41
520 UINT64 EchoEseqReceived : 8; // bit 42..49
521 UINT64 NumFreeBufReceived : 8; // bit 50..57
522 UINT64 Reserved : 6; // bit 58..63
523 } Bits;
524 UINT64 Uint64;
525} CXL_LINK_LAYER_CAPABILITY;
526
527typedef union {
528 struct {
529 UINT16 LlReset : 1; // bit 0..0
530 UINT16 LlInitStall : 1; // bit 1..1
531 UINT16 LlCrdStall : 1; // bit 2..2
532 UINT16 InitState : 2; // bit 3..4
533 UINT16 LlRetryBufferConsumed : 8; // bit 5..12
534 UINT16 Reserved : 3; // bit 13..15
535 } Bits;
536 UINT64 Uint64;
537} CXL_LINK_LAYER_CONTROL_AND_STATUS;
538
539typedef union {
540 struct {
541 UINT64 CacheReqCredits : 10; // bit 0..9
542 UINT64 CacheRspCredits : 10; // bit 10..19
543 UINT64 CacheDataCredits : 10; // bit 20..29
544 UINT64 MemReqRspCredits : 10; // bit 30..39
545 UINT64 MemDataCredits : 10; // bit 40..49
546 } Bits;
547 UINT64 Uint64;
548} CXL_LINK_LAYER_RX_CREDIT_CONTROL;
549
550typedef union {
551 struct {
552 UINT64 CacheReqCredits : 10; // bit 0..9
553 UINT64 CacheRspCredits : 10; // bit 10..19
554 UINT64 CacheDataCredits : 10; // bit 20..29
555 UINT64 MemReqRspCredits : 10; // bit 30..39
556 UINT64 MemDataCredits : 10; // bit 40..49
557 } Bits;
558 UINT64 Uint64;
559} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;
560
561typedef union {
562 struct {
563 UINT64 CacheReqCredits : 10; // bit 0..9
564 UINT64 CacheRspCredits : 10; // bit 10..19
565 UINT64 CacheDataCredits : 10; // bit 20..29
566 UINT64 MemReqRspCredits : 10; // bit 30..39
567 UINT64 MemDataCredits : 10; // bit 40..49
568 } Bits;
569 UINT64 Uint64;
570} CXL_LINK_LAYER_TX_CREDIT_STATUS;
571
572typedef union {
573 struct {
574 UINT32 AckForceThreshold : 8; // bit 0..7
575 UINT32 AckFLushRetimer : 10; // bit 8..17
576 } Bits;
577 UINT64 Uint64;
578} CXL_LINK_LAYER_ACK_TIMER_CONTROL;
579
580typedef union {
581 struct {
582 UINT32 MdhDisable : 1; // bit 0..0
583 UINT32 Reserved : 31; // bit 1..31
584 } Bits;
585 UINT64 Uint64;
586} CXL_LINK_LAYER_DEFEATURE;
587
588typedef struct {
589 CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;
590 CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;
591 CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;
592 CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;
593 CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;
594 CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;
595 CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;
596} CXL_1_1_LINK_CAPABILITY_STRUCTURE;
597
598CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability , 0x00);
599CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus , 0x08);
600CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl , 0x10);
601CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);
602CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus , 0x20);
603CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl , 0x28);
604CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature , 0x30);
605CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38);
606
607#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180
608typedef union {
609 struct {
610 UINT32 Reserved1 : 4; // bit 0..3
611 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
612 UINT32 Reserved2 : 24; // bit 8..31
613 } Bits;
614 UINT32 Uint32;
615} CXL_IO_ARBITRATION_CONTROL;
616
617CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);
618
619#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0
620typedef union {
621 struct {
622 UINT32 Reserved1 : 4; // bit 0..3
623 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
624 UINT32 Reserved2 : 24; // bit 8..31
625 } Bits;
626 UINT32 Uint32;
627} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;
628
629CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);
630
631///@}
632
633/// The CXL.RCRB base register definition
634/// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1
635///@{
636typedef union {
637 struct {
638 UINT64 RcrbEnable : 1; // bit 0..0
639 UINT64 Reserved : 12; // bit 1..12
640 UINT64 RcrbBaseAddress : 51; // bit 13..63
641 } Bits;
642 UINT64 Uint64;
643} CXL_RCRB_BASE;
644
645CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);
646
647///@}
648
649#pragma pack()
650
651//
652// CXL Downstream / Upstream Port RCRB space register offsets
653// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97
654//
655#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010
656#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014
657#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100
658
659#endif