Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <arch/romcc_io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <cpu/x86/smm.h> |
| 24 | #include <southbridge/intel/lynxpoint/nvs.h> |
| 25 | #include <southbridge/intel/lynxpoint/pch.h> |
| 26 | #include <southbridge/intel/lynxpoint/me.h> |
| 27 | #include <northbridge/intel/haswell/haswell.h> |
| 28 | #include <cpu/intel/haswell/haswell.h> |
| 29 | |
| 30 | int mainboard_io_trap_handler(int smif) |
| 31 | { |
| 32 | switch (smif) { |
| 33 | case 0x99: |
| 34 | printk(BIOS_DEBUG, "Sample\n"); |
| 35 | smm_get_gnvs()->smif = 0; |
| 36 | break; |
| 37 | default: |
| 38 | return 0; |
| 39 | } |
| 40 | |
| 41 | /* On success, the IO Trap Handler returns 0 |
| 42 | * On failure, the IO Trap Handler returns a value != 0 |
| 43 | * |
| 44 | * For now, we force the return value to 0 and log all traps to |
| 45 | * see what's going on. |
| 46 | */ |
| 47 | //gnvs->smif = 0; |
| 48 | return 1; |
| 49 | } |
| 50 | |
| 51 | /* |
| 52 | * Change LED_POWER# (SIO GPIO 45) state based on sleep type. |
| 53 | * The IO address is hardcoded as we don't have device path in SMM. |
| 54 | */ |
| 55 | #define SIO_GPIO_BASE_SET4 (0x730 + 3) |
| 56 | #define SIO_GPIO_BLINK_GPIO45 0x25 |
| 57 | void mainboard_smi_sleep(u8 slp_typ) |
| 58 | { |
| 59 | u8 reg8; |
| 60 | |
| 61 | switch (slp_typ) { |
| 62 | case SLP_TYP_S3: |
| 63 | case SLP_TYP_S4: |
| 64 | break; |
| 65 | |
| 66 | case SLP_TYP_S5: |
| 67 | /* Turn off LED */ |
| 68 | reg8 = inb(SIO_GPIO_BASE_SET4); |
| 69 | reg8 |= (1 << 5); |
| 70 | outb(reg8, SIO_GPIO_BASE_SET4); |
| 71 | break; |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | #define APMC_FINALIZE 0xcb |
| 76 | |
| 77 | static int mainboard_finalized = 0; |
| 78 | |
| 79 | int mainboard_smi_apmc(u8 apmc) |
| 80 | { |
| 81 | switch (apmc) { |
| 82 | case APMC_FINALIZE: |
| 83 | if (mainboard_finalized) { |
| 84 | printk(BIOS_DEBUG, "SMI#: Already finalized\n"); |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | intel_me_finalize_smm(); |
| 89 | intel_pch_finalize_smm(); |
| 90 | intel_northbridge_haswell_finalize_smm(); |
| 91 | intel_cpu_haswell_finalize_smm(); |
| 92 | |
| 93 | mainboard_finalized = 1; |
| 94 | break; |
| 95 | } |
| 96 | return 0; |
| 97 | } |