Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef GRAYSREEF_GPIO_H |
| 21 | #define GRAYSREEF_GPIO_H |
| 22 | |
| 23 | #include "southbridge/intel/lynxpoint/gpio.h" |
| 24 | |
| 25 | const struct pch_gpio_set1 pch_gpio_set1_mode = { |
| 26 | .gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F5 */ |
| 27 | .gpio1 = GPIO_MODE_GPIO, /* SMC_EXTSMI_N */ |
| 28 | .gpio2 = GPIO_MODE_GPIO, /* TP_RSVD_TESTMODE - float */ |
| 29 | .gpio3 = GPIO_MODE_NATIVE, /* SATA_ODD_DA_N -> PIRQF# */ |
| 30 | .gpio4 = GPIO_MODE_GPIO, /* EXTTS_SNI_DRV0_PCH - float */ |
| 31 | .gpio5 = GPIO_MODE_GPIO, /* EXTTS_SNI_DRV1_PCH - float */ |
| 32 | .gpio6 = GPIO_MODE_GPIO, /* DGPU_HPD_INTR_N */ |
| 33 | .gpio7 = GPIO_MODE_GPIO, /* SMC_RUNTIME_SCI_N */ |
| 34 | .gpio8 = GPIO_MODE_GPIO, /* PCH_GPIO8 -> DDR Voltage Select Bit 0 */ |
| 35 | .gpio9 = GPIO_MODE_NATIVE, /* USB_OC_10_11_R_N */ |
| 36 | .gpio10 = GPIO_MODE_NATIVE, /* USB_OC_12_13_R_N */ |
| 37 | .gpio11 = GPIO_MODE_GPIO, /* PCH_GPIO11 -> HOST_ALERT2_N -> PCIE_RSVD_2_N (3GIO_X1) slot 4 */ |
| 38 | .gpio12 = GPIO_MODE_GPIO, /* PM_LANPHY_ENABLE */ |
| 39 | .gpio13 = GPIO_MODE_NATIVE, /* HDA_DOCK_RST_N */ |
| 40 | .gpio14 = GPIO_MODE_GPIO, /* SMC_WAKE_SCI_R_N */ |
| 41 | .gpio15 = GPIO_MODE_GPIO, /* Always GPIO: HOST_ALERT1_R_N -> PCIE_RSV_1_N */ |
| 42 | .gpio16 = GPIO_MODE_NATIVE, /* SATA_DET4_R_N */ |
| 43 | .gpio17 = GPIO_MODE_GPIO, /* DGPU_PWROK */ |
| 44 | .gpio18 = GPIO_MODE_NATIVE, /* CK_SLOT1_OE_N_R */ |
| 45 | .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0_R - STRAP */ |
| 46 | .gpio20 = GPIO_MODE_GPIO, /* CK_SLOT2_OE_N_R */ |
| 47 | .gpio21 = GPIO_MODE_GPIO, /* SATA_DET0_R_N -> J9H4 */ |
| 48 | .gpio22 = GPIO_MODE_GPIO, /* BIOS_REC -> J8G1 */ |
| 49 | .gpio23 = GPIO_MODE_NATIVE, /* PCH_DRQ1_N */ |
| 50 | .gpio24 = GPIO_MODE_GPIO, /* Always GPIO: PCH_GPIO24_R1 -> DDR Voltage Select Bit 2 */ |
| 51 | .gpio25 = GPIO_MODE_NATIVE, /* CK_SLOT3_OE_N */ |
| 52 | .gpio26 = GPIO_MODE_NATIVE, /* CK_SLOT4_OE_N */ |
| 53 | .gpio27 = GPIO_MODE_GPIO, /* Always GPIO: PCH_GPIO_27 -> SMC_WAKE_SCI_N & LANWAKE_N */ |
| 54 | .gpio28 = GPIO_MODE_GPIO, /* Always GPIO: PLL_ODVR_EN */ |
| 55 | .gpio29 = GPIO_MODE_NATIVE, /* PCH_SLP_WLAN_N */ |
| 56 | .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK_R */ |
| 57 | .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT_R */ |
| 58 | }; |
| 59 | |
| 60 | const struct pch_gpio_set1 pch_gpio_set1_direction = { |
| 61 | .gpio0 = GPIO_DIR_INPUT, |
| 62 | .gpio1 = GPIO_DIR_INPUT, |
| 63 | .gpio2 = GPIO_DIR_OUTPUT, |
| 64 | /* .gpio3 NATIVE */ |
| 65 | .gpio4 = GPIO_DIR_OUTPUT, |
| 66 | .gpio5 = GPIO_DIR_OUTPUT, |
| 67 | .gpio6 = GPIO_DIR_INPUT, |
| 68 | .gpio7 = GPIO_DIR_INPUT, |
| 69 | .gpio8 = GPIO_DIR_OUTPUT, |
| 70 | .gpio9 = GPIO_DIR_INPUT, |
| 71 | /* .gpio10 NATIVE */ |
| 72 | .gpio11 = GPIO_DIR_INPUT, |
| 73 | .gpio12 = GPIO_DIR_OUTPUT, |
| 74 | /* .gpio13 NATIVE */ |
| 75 | .gpio14 = GPIO_DIR_INPUT, |
| 76 | .gpio15 = GPIO_DIR_INPUT, |
| 77 | /* .gpio16 NATIVE */ |
| 78 | .gpio17 = GPIO_DIR_INPUT, |
| 79 | /* .gpio18 NATIVE */ |
| 80 | .gpio19 = GPIO_DIR_INPUT, |
| 81 | .gpio20 = GPIO_DIR_INPUT, |
| 82 | .gpio21 = GPIO_DIR_INPUT, |
| 83 | .gpio22 = GPIO_DIR_INPUT, |
| 84 | /* .gpio23 NATIVE */ |
| 85 | .gpio24 = GPIO_DIR_OUTPUT, |
| 86 | /* .gpio25 NATIVE */ |
| 87 | /* .gpio26 NATIVE */ |
| 88 | .gpio27 = GPIO_DIR_INPUT, |
| 89 | .gpio28 = GPIO_DIR_INPUT, |
| 90 | /* .gpio29 NATIVE */ |
| 91 | /* .gpio30 NATIVE */ |
| 92 | /* .gpio31 NATIVE */ |
| 93 | }; |
| 94 | |
| 95 | const struct pch_gpio_set1 pch_gpio_set1_level = { |
| 96 | .gpio2 = GPIO_LEVEL_HIGH, |
| 97 | .gpio4 = GPIO_LEVEL_HIGH, |
| 98 | .gpio5 = GPIO_LEVEL_HIGH, |
| 99 | .gpio8 = GPIO_LEVEL_HIGH, |
| 100 | .gpio12 = GPIO_LEVEL_LOW, |
| 101 | .gpio24 = GPIO_LEVEL_LOW, |
| 102 | }; |
| 103 | |
| 104 | const struct pch_gpio_set1 pch_gpio_set1_invert = { |
| 105 | }; |
| 106 | |
| 107 | const struct pch_gpio_set2 pch_gpio_set2_mode = { |
| 108 | .gpio32 = GPIO_MODE_NATIVE, /* Always GPIO on desktop. Mobile Native. PM_CLKRUN_N */ |
| 109 | .gpio33 = GPIO_MODE_NATIVE, /* HDADOCKEN_R_N */ |
| 110 | .gpio34 = GPIO_MODE_GPIO, /* PCH_GPIO34 -> SATA_PWR_EN0_N */ |
| 111 | .gpio35 = GPIO_MODE_GPIO, /* Always GPIO. SATA_PWR_EN1_R_N */ |
| 112 | .gpio36 = GPIO_MODE_NATIVE, /* SATA_ODD_PRSNT_R_N */ |
| 113 | .gpio37 = GPIO_MODE_GPIO, /* FDI_OVRVLTG */ |
| 114 | .gpio38 = GPIO_MODE_GPIO, /* MFG_MODE */ |
| 115 | .gpio39 = GPIO_MODE_GPIO, /* GFX_CRB_DET */ |
| 116 | .gpio40 = GPIO_MODE_NATIVE, /* USB_OC_2_R_N */ |
| 117 | .gpio41 = GPIO_MODE_NATIVE, /* USB_OC_5_R_N */ |
| 118 | .gpio42 = GPIO_MODE_NATIVE, /* USB_OC_6_7_R_N */ |
| 119 | .gpio43 = GPIO_MODE_NATIVE, /* USB_OSC_8_9_R_N */ |
| 120 | .gpio44 = GPIO_MODE_NATIVE, /* CK_SLOT5_OE_N */ |
| 121 | .gpio45 = GPIO_MODE_NATIVE, /* CK_PCIE_LAN_REQ_N */ |
| 122 | .gpio46 = GPIO_MODE_GPIO, /* PCH_GPIO46_R -> DDR Voltage Select Bit 1 */ |
| 123 | .gpio47 = GPIO_MODE_NATIVE, /* PEGA_CKREQ_N */ |
| 124 | .gpio48 = GPIO_MODE_GPIO, /* BIOS_RESP -> J8E6 */ |
| 125 | .gpio49 = GPIO_MODE_GPIO, /* PCH_GP_49 -> CRIT_TEMP_REP_N */ |
| 126 | .gpio50 = GPIO_MODE_GPIO, /* DGPU_HOLD_RST_N */ |
| 127 | .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 Strap */ |
| 128 | .gpio52 = GPIO_MODE_GPIO, /* DGPU_SELECT_N */ |
| 129 | .gpio53 = GPIO_MODE_GPIO, /* DGPU_PWM_SELECT_N -> PEG_JTAG5 */ |
| 130 | .gpio54 = GPIO_MODE_GPIO, /* DGPU_PWR_EN_N -> PEG_RSVD5 */ |
| 131 | .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR Strap */ |
| 132 | .gpio56 = GPIO_MODE_NATIVE, /* MC_CKREQ_N */ |
| 133 | .gpio57 = GPIO_MODE_GPIO, /* Always GPIO. NFC_IRQ_R */ |
| 134 | .gpio58 = GPIO_MODE_NATIVE, /* SML1_CK */ |
| 135 | .gpio59 = GPIO_MODE_NATIVE, /* USB_OC_0_1_R_N */ |
| 136 | .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ |
| 137 | .gpio61 = GPIO_MODE_NATIVE, /* PM_SUS_STAT_N */ |
| 138 | .gpio62 = GPIO_MODE_NATIVE, /* SUS_CK */ |
| 139 | .gpio63 = GPIO_MODE_NATIVE, /* SLP_S5_R_N */ |
| 140 | }; |
| 141 | |
| 142 | const struct pch_gpio_set2 pch_gpio_set2_direction = { |
| 143 | /* .gpio32 NATIVE */ |
| 144 | /* .gpio33 NATIVE */ |
| 145 | .gpio34 = GPIO_DIR_OUTPUT, |
| 146 | .gpio35 = GPIO_DIR_OUTPUT, |
| 147 | /* .gpio36 NATIVE */ |
| 148 | .gpio37 = GPIO_DIR_INPUT, |
| 149 | .gpio38 = GPIO_DIR_INPUT, |
| 150 | .gpio39 = GPIO_DIR_INPUT, |
| 151 | /* .gpio40 NATIVE */ |
| 152 | /* .gpio41 NATIVE */ |
| 153 | /* .gpio42 NATIVE */ |
| 154 | /* .gpio43 NATIVE */ |
| 155 | /* .gpio44 NATIVE */ |
| 156 | /* .gpio45 NATIVE */ |
| 157 | .gpio46 = GPIO_DIR_OUTPUT, |
| 158 | /* .gpio47 NATIVE */ |
| 159 | .gpio48 = GPIO_DIR_INPUT, |
| 160 | .gpio49 = GPIO_DIR_OUTPUT, |
| 161 | .gpio50 = GPIO_DIR_OUTPUT, |
| 162 | .gpio51 = GPIO_DIR_OUTPUT, |
| 163 | .gpio52 = GPIO_DIR_OUTPUT, |
| 164 | .gpio53 = GPIO_DIR_OUTPUT, |
| 165 | .gpio54 = GPIO_DIR_OUTPUT, |
| 166 | .gpio55 = GPIO_DIR_OUTPUT, |
| 167 | /* .gpio56 NATIVE */ |
| 168 | .gpio57 = GPIO_DIR_INPUT, |
| 169 | /* .gpio58 NATIVE */ |
| 170 | /* .gpio59 NATIVE */ |
| 171 | .gpio60 = GPIO_DIR_OUTPUT, |
| 172 | /* .gpio61 NATIVE */ |
| 173 | /* .gpio62 NATIVE */ |
| 174 | /* .gpio63 NATIVE */ |
| 175 | }; |
| 176 | |
| 177 | const struct pch_gpio_set2 pch_gpio_set2_level = { |
| 178 | .gpio34 = GPIO_LEVEL_LOW, |
| 179 | .gpio35 = GPIO_LEVEL_LOW, |
| 180 | .gpio46 = GPIO_LEVEL_HIGH, |
| 181 | .gpio49 = GPIO_LEVEL_HIGH, |
| 182 | .gpio50 = GPIO_LEVEL_HIGH, |
| 183 | .gpio51 = GPIO_LEVEL_LOW, |
| 184 | .gpio52 = GPIO_LEVEL_LOW, |
| 185 | .gpio53 = GPIO_LEVEL_LOW, |
| 186 | .gpio54 = GPIO_LEVEL_LOW, |
| 187 | .gpio55 = GPIO_LEVEL_LOW, |
| 188 | .gpio60 = GPIO_LEVEL_HIGH, |
| 189 | }; |
| 190 | |
| 191 | const struct pch_gpio_set3 pch_gpio_set3_mode = { |
| 192 | .gpio64 = GPIO_MODE_GPIO, /* CK_PCH_SIO_DOCK_R -> TP_CK_PCI_SIO_DOCK */ |
| 193 | .gpio65 = GPIO_MODE_NATIVE, /* CK_FLEX1 */ |
| 194 | .gpio66 = GPIO_MODE_GPIO, /* TP_CK_FLEX2 */ |
| 195 | .gpio67 = GPIO_MODE_GPIO, /* DGPU_PRSNT_N -> PEG_RSVD3 */ |
| 196 | .gpio68 = GPIO_MODE_GPIO, /* SATA_ODD_PWRGT */ |
| 197 | .gpio69 = GPIO_MODE_GPIO, /* SV_DET -> J8E5 */ |
| 198 | .gpio70 = GPIO_MODE_GPIO, /* USB3_DET_P2_N */ |
| 199 | .gpio71 = GPIO_MODE_GPIO, /* USB3_DET_P3_N */ |
| 200 | .gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW_R_N */ |
| 201 | .gpio73 = GPIO_MODE_NATIVE, /* CK_REQ_DOCK_N */ |
| 202 | .gpio74 = GPIO_MODE_NATIVE, /* PCH_GPIO74_R -> AMB_THM2_R_N */ |
| 203 | .gpio75 = GPIO_MODE_NATIVE, /* SM1_DATA */ |
| 204 | }; |
| 205 | |
| 206 | const struct pch_gpio_set3 pch_gpio_set3_direction = { |
| 207 | .gpio64 = GPIO_DIR_OUTPUT, |
| 208 | /* .gpio65 NATIVE */ |
| 209 | .gpio66 = GPIO_DIR_OUTPUT, |
| 210 | .gpio67 = GPIO_DIR_INPUT, |
| 211 | .gpio68 = GPIO_DIR_OUTPUT, |
| 212 | .gpio69 = GPIO_DIR_INPUT, |
| 213 | .gpio70 = GPIO_DIR_INPUT, |
| 214 | .gpio71 = GPIO_DIR_INPUT, |
| 215 | /* .gpio72 NATIVE */ |
| 216 | /* .gpio73 NATIVE */ |
| 217 | /* .gpio74 NATIVE */ |
| 218 | /* .gpio75 NATIVE */ |
| 219 | }; |
| 220 | |
| 221 | const struct pch_gpio_set3 pch_gpio_set3_level = { |
| 222 | .gpio64 = GPIO_LEVEL_LOW, |
| 223 | .gpio66 = GPIO_LEVEL_LOW, |
| 224 | .gpio68 = GPIO_LEVEL_HIGH, |
| 225 | }; |
| 226 | |
| 227 | const struct pch_gpio_map graysreef_gpio_map = { |
| 228 | .set1 = { |
| 229 | .mode = &pch_gpio_set1_mode, |
| 230 | .direction = &pch_gpio_set1_direction, |
| 231 | .level = &pch_gpio_set1_level, |
| 232 | .invert = &pch_gpio_set1_invert, |
| 233 | }, |
| 234 | .set2 = { |
| 235 | .mode = &pch_gpio_set2_mode, |
| 236 | .direction = &pch_gpio_set2_direction, |
| 237 | .level = &pch_gpio_set2_level, |
| 238 | }, |
| 239 | .set3 = { |
| 240 | .mode = &pch_gpio_set3_mode, |
| 241 | .direction = &pch_gpio_set3_direction, |
| 242 | .level = &pch_gpio_set3_level, |
| 243 | }, |
| 244 | }; |
| 245 | |
| 246 | #endif |